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7. BLOCK DIAGRAM
7. BLOCK DIAGRAM
ip s
lc h
b i
M o
Figure 7-1. block diagram
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8. CIRCUIT DIAGRAM
8. CIRCUIT DIAGRAM
8.1 MAIN
1 2 3 4 5 6 7 8 9 10
2V45_VCORE 2V8_VMEM 2V45_VCORE 2V45_VRTC 2V45_VAN
VBAT
1K
C114 10uF
C167 10uF
C102 C103 C104 C105 C106 C107 C110 C108 C101 C109 C166 C111 C112 BAT101
47n 47n 47n 47n 47n 47n 47n 47n 100p R101
NBL621-TZ1 2012
TP134 47n 47n 47n 47n
VCHARGE
KEYROW(0)
C117
10uF
C115 C116
R102
2.4K
MVBAT MIDI_A0
K14
N13
B14
B10
10uF
H1
C8
N5
N9
C6
D5
A2
P7
E3
L9
L2
23
20
0.1u
5
V102
LCD_RS 0 DATA(0:15)
39p
SP101
R103 C118
RESET ADD(0:20)
VBAT
VBAT_2
VRTCIN
VCC1
VCC2
VCC3
VCC4
VSIM
VMEM1
VMEM2
VMEM3
VMEM4
VEXT1
VEXT2
VEXT3
VEXT4
VPEG1
VDDRTC
2012 39p
2012 H4 N6 DATA(0)
R104
100 C119 ADD0 DATA0 MIC101
C121
A 2 3 ADD(0) J3 P6 DATA(1) A
R106
POWERKEY PWRONKEY ROWX 100p ADD1 DATA1 C120 L101
0.33
2012 4 C122 R105
ADD(1) J2 M6DATA(2) 1
SIMEN SIMEN 100p ADD2 DATA2
8 ADD(2) J4 N7 DATA(3) 0.1u 100nH 2
MVBAT ADD3 DATA3 C125 100 C123
10 ADD(3) K3 M7DATA(4) 39p 39p
CHRIN ADD4 DATA4 R107 C124 L102
VBAT 14 18 ADD(4) K2 L7 DATA(5) OBG-15S40-C2
ISENSE RESET ADD5 DATA5
ADD(5) K4 P8 DATA(6) 100nH
C127
Q102 100 0.1u
C126 ADD6 DATA6
NDC652P 19 ADD(6) L4 N8 DATA(7) R108
1000p 12 ADP3408
VSIM 2V9_SIM ADD7 DATA7
M8DATA(8) 2V45_VAN 2V45_VCORE
C128
ADD(7) L1 3K
6
V101
SP102
S2 GATEDR ADD8 DATA8 39p
U101 21 ADD(8) L3 P9 DATA(9)
39p
CUS02
7
VMEM 2V8_VMEM ADD9 DATA9
2V45_VAN
D101 4 ADD(9) L5 M9DATA(10)
S1 BATSNS ADD10 DATA10
3 22 ADD(10)M1 P10
DATA(11) MICBAIS
G
17
VCORE 2V45_VCORE ADD11 DATA11 Q101
1 D3 ADD(11)M2 N10
47n
47n
47n
47n
47n
47n
2SC5585
R112 1K
DATA(12) 3
RESCAP ADD12 DATA12 R109
2 D2 24 ADD(12) N1 M10
DATA(13) 2
R111
VAN 2V45_VAN ADD13 DATA13
NC
R110
ADD(13) P1 P11
5
D1 DATA(14)
ADD14 DATA14 C129 1
1.5K
25 ADD(14) N2 N11
C131
C132
C133
C134
C135
C136
DATA(15)
R113
100K
C130 VTCXO 2V7_VTCXO ADD15 DATA15 100K 10uF
ADD(15) P2
0.1u ADD16
6 ADD(16) N3
VRTC 2V45_VRTC ADD17 47 2012
2K
ADD(17)M3 L14
PWRONIN
ADD18 GPIO_32 DSR
F10
REFOUT
G1
A9
A1
K5
J8
CHRDET
TCXOEN