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CONFIDENTIAL
10 Schematic Diagrams
10-1 CPU Block & Signal Processing Part Schematic Diagram
PAG(0:7)
PAR(0:7) TO DPTV DIGITAL INPUT
AD(0:7) +3.3V_A
PAB(0:7)
PAR(7)
PAR(6)
PAR(5)
PAR(4)
PAR(3)
PAR(2)
PAR(1)
PAR(0)
PAB(7)
PAB(6)
PAB(5)
PAB(4)
PAB(3)
PAB(2)
PAB(1)
PAB(0)
+5V IC002 IC003 TO DPTV
2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 MCAD(0:7) MCAD(0:7)
+3.3V_BD C336 SUPLECODE SUPLECODE C602
IC004 IC005 PARALLEL COMM
100uF 100nF
DGCPU DGCPU
16V SUPLECODE 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 SUPLECODE
IC001 MCA(0:19)
D98
MCA(0:19)
FST16233MTDX +3.3V_A
54
51
48
10
45
15
40
18
37
21
34
24
31
MCAD(5)
MCAD(0)
MCAD(6)
MCAD(7)
1
4
7
MCA(12)
MCA(15)
MCA(16)
MCA(18)
MCA(17)
10A
12A
13A
14A
15A
16A
MCA(0)
MCA(1)
MCA(2)
MCA(10)
MCA(3)
MCA(4)
MCA(5)
MCA(9)
MCA(6)