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processors TDA8360; TDA8361; TDA8362
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INTEGRATED CIRCUITS
DATA SHEET
TDA8360; TDA8361; TDA8362 Integrated PAL and PAL/NTSC TV processors
Objective specification File under Integrated Circuits, IC02 March 1994
Philips Semiconductors
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
FEATURES Available in TDA8360, TDA8361 and TDA8362 · Vision IF amplifier with high sensitivity and good differential gain and phase · Multistandard FM sound demodulator (4.5 MHz to 6.5 MHz) · Integrated chrominance trap and bandpass filters (automatically calibrated) · Integrated luminance delay line · RGB control circuit with linear RGB inputs and fast blanking · Horizontal synchronization with two control loops and alignment-free horizontal oscillator without external components · Vertical count-down circuit (50/60 Hz) and vertical preamplifier · Low dissipation (700 mW) · Small amount of peripheral components compared with competition ICs · Only one adjustment (vision IF demodulator) · The supply voltage for the ICs is 8 V. They are mounted in a shrink DIL envelope with 52 pins and are pin compatible. Additional features TDA8360
TDA8360; TDA8361; TDA8362
GENERAL DESCRIPTION The TDA8360, TDA8361 and TDA8362 are single-chip TV processors which contain nearly all small signal functions that are required for a colour television receiver. For a complete receiver the following circuits need to be added: a base-band delay line (TDA4661), a tuner and output stages for audio, video and horizontal and vertical deflection. Because of the different functional contents of the ICs the set maker can make the optimum choice depending on the requirements for the receiver. The TDA8360 is intended for simple PAL receivers (all PAL standards, including PAL-N and PAL-M are possible). The TDA8361 contains a PAL/NTSC decoder and has an A/V switch. For real multistandard applications the TDA8362 is available. In addition to the extra functions which are available in the TDA8361, the TDA8362 can handle signals with positive modulation and it supplies the signals which are required for the SECAM decoder TDA8395.
· Alignment-free PAL colour decoder for all PAL standards, including PAL-N and PAL-M. TDA8361 · PAL/NTSC colour decoder with automatic search system · Source selection for external audio/video (A/V) inputs (separate Y/C signals can also be applied). TDA8362 · Multistandard vision IF circuit (positive and negative modulation) · PAL/NTSC colour decoder with automatic search system · Source selection for external A/V inputs (separate Y/C signals can also be applied) · Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications.
ORDERING INFORMATION EXTENDED TYPE NUMBER TDA8360 TDA8361 TDA8362 PACKAGE PINS 52 52 52 PIN POSITION shrink DIL shrink DIL shrink DIL MATERIAL plastic plastic plastic CODE SOT247AG SOT247AG SOT247AG
March 1994
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Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
QUICK REFERENCE DATA SYMBOL VP IP Input voltages V45,46(rms) V5(rms) V6(rms) V15(p-p) V22,23,24(p-p) VO(p-p) I47 V44 V50(rms) V18,19,20(p-p) I37 I43 Vcontrol video IF amplifier sensitivity (RMS value) sound IF amplifier sensitivity (RMS value) external audio input (RMS value) external CVBS input (peak-to-peak value) RGB inputs (peak-to-peak value) supply voltage supply current PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS
MIN. 7.2 - - -
TYP. 8.0 80
MAX. 8.8 -
UNIT V mA µV mV mV V V
70 1 350 1 0.7
100 - - - - - 5 - - - - -
TDA8361, TDA8362 TDA8361, TDA8362
- - - - 0 - - - 10 1
Output signals demodulated CVBS output (peak-to-peak value) tuner AGC control current AFC output voltage swing audio output voltage (RMS value) RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current 2.4 - 6 700 4 - - - V mA V mV V mA mA
Control voltages control voltages for Volume, Contrast, Saturation, Brightness, Hue and Peaking 0 5 V
March 1994
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March 1994
flyback VRAMP DEC AGC VOUT VFB VSTART 42 40 36 39 38 37 34 35 HOUT 49 48 43 41 XTAL1 XTAL2 PH1LF PH2LF FBI/SCO sandcastle AGC VERTICAL OUTPUT PHASE 1 PHASE 2 XTAL OSCILLATOR VERTICAL DIVIDER TUNING LINE OSCILLATOR COLOUR KILLERS PHASE DETECTOR 33 DET
Philips Semiconductors
TUNE ADJ
AGCOUT
47
IFIN1
45
IFIN2
46
IF AMPLIFIER
IFDEM1
2
DEMODULATOR
3
AFC AND SAMPLEAND-HOLD
IFDEM2
AFCOUT
44 30 H AND V SEPARATION COINCIDENCE DETECTOR ACC AMPLIFIER PAL IDENTIFICATION DEMODULATOR 31 26 28 NOISE DETECTOR POWER RESET CHROMINANCE BANDPASS MATRIX CLAMPS SET 29
Integrated PAL and PAL/NTSC TV processors
IFOUT
7
VIDEO AMPLIFIER
VIDEO IDENTIFICATION
R-Y output to TDA4661 B-Y output SAT
4
TUNING TRAP AND BYPASS Y DELAY PEAKING PLL
IDENT
4 8
DEC DIG
TEST
SUPPLY
AUDEEM
B-Y input from TDA4661 R-Y input
1
AUOUT
50
VOLUME
PREAMPLIFIER MUTE
LUMINANCE MATRIX
CLAMP SWITCH
22 23 24 21
RIN GIN BIN RGBIN
DEC DEM
51
LIMITER
TDA8360
10 12 13 CVBS INT 52 14 PEAKIN
PWL
OUTPUT STAGES 25 CON 17 BRI
18 19 20
5
BOUT GOUT ROUT
MLA621 - 1
11
9
SOIF
volume control VP DEC BG DEC FT
GND2 GND1
TDA8360; TDA8361; TDA8362
Objective specification
Fig.1 Block diagram for TDA8360.
March 1994
flayback sandcastle FBI/SCO XTAL1 VFB VSTART HOUT 36 27 HUE 39 38 37 34 35 42 40 47 49 48 43 41 XTAL2 VRAMP DEC AGC VOUT PH1LF PH2LF AGC VERTICAL OUTPUT PHASE 1 PHASE 2 XTAL OSCILLATOR HUE CONTROL VERTICAL DIVIDER TUNING LINE OSCILLATOR COLOUR KILLERS PHASE DETECTOR 33 DET
Philips Semiconductors
TUNE ADJ
AGCOUT
IFIN1
45
IFIN2
46
IF AMPLIFIER
IFDEM1
2
DEMODULATOR
3
AFC AND SAMPLEAND-HOLD
IFDEM2
AFCOUT
44 30 H AND V SEPARATION COINCIDENCE DETECTOR ACC AMPLIFIER SYSTEM MANAGER DEMODULATOR 31 26 28 SUPPLY NOISE DETECTOR POWER RESET CHROMINANCE BANDPASS MATRIX CLAMPS SET 29
Integrated PAL and PAL/NTSC TV processors
IFOUT
7
VIDEO AMPLIFIER
VIDEO IDENTIFICATION
R-Y output to TDA4661 B-Y output SAT
IDENT
5
TUNING TRAP AND BYPASS Y DELAY PEAKING PLL
4 8
DEC DIG
TEST
AUDEEM
1
B-Y input from TDA4661 R-Y input
EXTAU
6
AUOUT
50
VOLUME
PREAMPLIFIER MUTE
LUMINANCE MATRIX
CLAMP SWITCH
22 23 24 21
RIN GIN BIN RGBIN
DEC DEM
51
LIMITER
TDA8361
LUMINANCE SWITCH 13 CVBS INT 15 CVBS EXT 10 12 52
5 9
CHROMINANCE SWITCH 14 16 CHROMA PEAKIN
PWL
OUTPUT STAGES 25 17 CON BRI
18 19 20
BOUT GOUT ROUT
MLA622 - 1
SOIF
11
volume control VP DEC BG DEC FT
GND2 GND1
TDA8360; TDA8361; TDA8362
Objective specification
Fig.2 Block diagram for TDA8361.
March 1994
flyback sandcastle FBI/SCO XTAL1 VFB VSTART HOUT 36 39 38 37 34 35 32 27 42 40 XTALOUT 43 41 HUE XTAL2 VRAMP DEC AGC VOUT AFCOUT 48 44 PH1LF PH2LF AGC VERTICAL OUTPUT PHASE 1 PHASE 2 XTAL OSCILLATOR HUE CONTROL VERTICAL DIVIDER TUNING LINE OSCILLATOR SYSTEM MANAGER PHASE DETECTOR 33 DET
Philips Semiconductors
AUOUT
IDENT
AGCOUT
4
50
47
IFIN1
45
IFIN2
46
IF AMPLIFIER
TUNE ADJ
49
IFDEM1
2
DEMODULATOR
3
AFC AND SAMPLEAND-HOLD
IFDEM2 IFOUT
7 30 POWER RESET H AND V SEPARATION COINCIDENCE DETECTOR COLOUR KILLERS DEMODULATOR 31 R-Y output to TDA4661 B-Y output
Integrated PAL and PAL/NTSC TV processors
VIDEO IDENTIFICATION
VIDEO AMPLIFIER
1 28
6
TDA8362
NOISE DETECTOR ACC AMPLIFIER MATRIX PLL TRAP AND BYPASS CHROMINANCE SWITCH CHROMINANCE BANDPASS TEST TUNING LUMINANCE SWITCH 16 CVBS INT CVBSEXT CHROMA DEC FT 13 15 Y DELAY PEAKING 14 PEAKIN PWL 12
AUDEEM EXTAU
6 CLAMPS SET
SWITCH VOLUME
PREAMPLIFIER MUTE
29
B-Y input from TDA4661 R-Y input
DEC DEM
51
5
LIMITER
LUMINANCE MATRIX
CLAMP SWITCH
22 23 24
SOIF
RIN GIN BIN
volume control OUTPUT STAGES 26 21 25 CON SAT RGBIN 17 BRI
8
SUPPLY
DEC DIG
18 19 20
BOUT GOUT ROUT
MBC214 - 1
11
9
10
52
GND2
GND1
VP
DEC BG
TDA8360; TDA8361; TDA8362
Objective specification
Fig.3 Block diagram for TDA8362.
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
PINNING (TDA8362) SYMBOL AUDEEM IFDEM1 IFDEM2 IDENT
AUDEEM IFDEM1 IFDEM2 IDENT SOIF EXTAU IFOUT DEC DIG GND1 1 2 3 4 5 6 7 8 9 52 DEC BG 51 DEC DEM 50 AUOUT 49 TUNEADJ 48 DECAGC 47 AGCOUT 46 IFIN2 45 IFIN1 44 AFCOUT 43 VOUT 42 VRAMP 41 VFB 40 PH1LF TDA8362 PEAKIN 14 CVBS EXT 15 CHROMA 16 BRI 17 BOUT 18 GOUT 19 ROUT 20 RGBIN 21 RIN 22 GIN 23 BIN 24 CON 25 SAT 26
MBC203
TDA8360; TDA8361; TDA8362
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 7
DESCRIPTION audio de-emphasis and ± modulation switch IF demodulator tuned circuit IF demodulator tuned circuit video identification output/MUTE input sound IF input and volume control external audio input IF video output decoupling digital supply ground 1 supply voltage (+8 V) ground 2 decoupling filter tuning internal CVBS input peaking control input external CVBS input chrominance and A/V switch input brightness control input blue output green output red output RGB insertion and blanking input red input green input blue input contrast control input saturation control input hue control input (or chrominance output) B-Y input signal R-Y input signal R-Y output signal B-Y output signal 4.43 MHz output for TDA8395 loop filter burst phase detector 3.58 MHz crystal connection 4.43 MHz crystal connection supply/start horizontal oscillator horizontal output flyback input/sandcastle output phase 2 loop filter phase 1 loop filter
SOIF EXTAU IFOUT DECDIG GND1 VP GND2 DECFT CVBSINT PEAKIN CVBSEXT CHROMA BRI BOUT GOUT ROUT RGBIN RIN GIN BIN CON SAT HUE BYI RYI RYO BYO XTALOUT DET XTAL1 XTAL2 VSTART HOUT FBI/SCO
V P 10 GND2 11 DEC FT 12 CVBS INT 13
39 PH2LF 38 FBI/SCO 37 HOUT 36 VSTART 35 XTAL2 34 XTAL1 33 DET 32 XTALOUT 31 BYO 30 RYO 29 RYI 28 BYI 27 HUE
Fig.4
Pin configuration for TDA8362.
PH2LF PH1LF
March 1994
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL VFB VRAMP VOUT AFCOUT IFIN1 IFIN2 AGCOUT DECAGC TUNEADJ AUOUT DECDEM DECBG TDA8360 The TDA8360 has the following differences to the pinning: Pin 6: external audio input not connected Pin 15: external CVBS input not connected Pin 16: chrominance and A/V switch input not connected Pin 27: hue control input not connected. TDA8361 The TDA8361 has the following differences to the pinning: Pin 1: only audio de-emphasis Pin 27: only hue control Pin 32: 4.43 MHz output for TDA8395 is not connected. FUNCTIONAL DESCRIPTION Video IF amplifier The IF amplifier contains 3 AC-coupled control stages with a total gain control range of greater than 60 dB. The sensitivity of the circuit is comparable with that of modern IF ICs. PIN 41 42 43 44 45 46 47 48 49 50 51 52 DESCRIPTION vertical feedback input vertical ramp generator vertical output AFC output IF input 1 IF input 2 tuner AGC output AGC decoupling capacitor tuner take-over adjustment audio output decoupling sound demodulator decoupling bandgap supply
TDA8360; TDA8361; TDA8362
To overcome this problem a speed-up circuit has been included which detects whether the AGC detector is activated every frame period. If, during a 3-frame period, no action is detected the speed of the system is increased. When the incoming signal has no peak white information (e.g. test lines in the vertical retrace period) the gain would be video signal dependent. To avoid this effect the circuit also contains a black level AGC detector which is activated when the black level of the video signal exceeds a certain level. The TDA8361 and TDA8362 contain a video identification circuit which is independent of the synchronization circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. In the TDA8360 this circuit is only used for stable OSD at no signal input. In the normal television mode the identification output is connected to the coincidence detector, this applies to all three devices. The identification output voltage is LOW when no transmitter is identified. In this condition the sound demodulator is switched off (mute function). When a transmitter is identified the output voltage is HIGH. The voltage level is dependent on the frequency of the incoming chrominance signal.
The reference carrier for the video demodulator is obtained by means of passive regeneration of the picture carrier. The external reference tuned circuit is the only remaining adjustment of the IC. In the TDA8362 the polarity of the demodulator can be switched so that the circuit is suitable for both positive and negative modulated signals. The AFC circuit is driven with the same reference signal as the video demodulator. To ensure that the video content does not disturb the AFC operation a sample-and-hold circuit is incorporated; the capacitor for this function is internal. The AFC output voltage is 6 V. The AGC detector operates on levels, top sync for negative modulated and top white for positive modulated signals.The AGC detector time constant capacitor is connected externally. This is mainly because of the flexibility of the application. The time constant of the AGC system during positive modulation (TDA8362) is slow, this is to avoid any visible picture variations. This, however, causes the system to react very slowly to sudden changes in the input signal amplitude.
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Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
Sound circuit The sound bandpass and trap filters have to be connected externally. The filtered intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL demodulator. The PLL circuit tunes itself automatically to the incoming signal, consequently, no adjustment is required. The volume is DC controlled. The composite audio output signal has an amplitude of 700 mV RMS at a volume control setting of -6 dB. The de-emphasis capacitor has to be connected externally. The non-controlled audio signal can be obtained from this pin via a buffer stage. The amplitude of this signal is 350 mV RMS. The TDA8361 and TDA8362 external audio input signal must have an amplitude of 350 mV RMS. The audio/video switch is controlled via the chrominance input pin. Synchronization circuit The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed level. The sync pulses are then fed to the slicing stage (separator) which operates at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence detector is used for transmitter identification and to detect whether the line oscillator is synchronized. When the circuit is not synchronized the voltage on the peaking control pin (pin 14) is LOW so that this condition can be detected externally. The first PLL has a very high static steepness, this ensures that the phase of the picture is independent of the line frequency. The line oscillator operates at twice the line frequency.
TDA8360; TDA8361; TDA8362
When the pin is left open-circuit the trap is switched off so that the circuit can also be used for S-VHS applications. The luminance delay line and the delay for the peaking circuit are also realised by means of gyrator circuits. Colour decoder The colour decoder in the various ICs contains an alignment-free crystal oscillator, a colour killer circuit and colour difference demodulators. The 90° phase shift for the reference signal is achieved internally. Because the main differences of the 3 ICs are found in the colour decoder the various types will be discussed. TDA8360 This IC contains only a PAL decoder. Depending on the frequency of the crystals which are connected to the IC the decoder can demodulate all PAL standards. Because the horizontal oscillator is calibrated by using the crystal frequency as a reference the 4.4 MHz crystal must be connected to pin 35 and the 3.5 MHz crystal to pin 34. When only one crystal is connected to the IC the other crystal pin must be connected to the positive supply rail via a 47 k resistor. For applications with two 3.5 MHz crystals both must be connected to pin 34 and the switching between the crystals must be made externally. Switching of the crystals is only allowed directly after the vertical retrace. The circuit will indicate whether a PAL signal has been identified by the colour decoder via the saturation control pin. When two crystals are connected to the IC the output voltage of the video identification circuit indicates the frequency of the incoming chrominance signal.
The oscillator network is internal. Because of the spread of internal components an automatic adjustment circuit has been added to the IC. The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in a free-running frequency which deviates less than 2% from the typical value. The circuit employs a second control loop to generate the drive pulses for the horizontal driver stage. X-ray protection can be realised by switching the pin of the second control loop to the positive supply line. The detection circuit must be connected externally. When the X-ray protection is active the horizontal output voltage is switched to a high level. When the voltage on this pin returns to its normal level the horizontal output is released again. The IC contains a start-up circuit for the horizontal oscillator. When this feature is required a current of 6.5 mA has to be supplied to pin 36. For an application without start-up both supply pins (10 and 36) must be connected to the 8 V supply line. The drive signal for the vertical ramp generator is generated by means of a divider circuit. The RC network for the ramp generator is external. Integrated video filters The circuit contains a chrominance bandpass and trap circuit. The filters are realised by means of gyrator circuits and are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. In the TDA8361 and TDA8362 the chrominance trap is active only when the separate chrominance input pin is connected to ground or to the positive supply voltage and when a colour signal is recognized.
March 1994
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Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
The conditions are: · Signal identified at fosc = 3.6 MHz; VO = 6 V · Signal identified at fosc = 4.4 MHz (or no colour); VO = 8 V. This information can be used to switch the sound bandpass filter and trap filter. TDA8361 This IC contains an automatic PAL/NTSC decoder. The conditions for connecting the reference crystals are the same as for the TDA8360. The decoder can be forced to PAL when the hue control pin is connected to the positive supply voltage via a 5 k or 10 k resistor (approximately). The decoder cannot be forced to the NTSC standard. It is also possible to see if a colour signal is recognized via the saturation pin. TDA8362 In addition to the possibilities of the TDA8361, the TDA8362 can co-operate with the SECAM add-on decoder TDA8395. The communication between the two ICs is achieved via pin 32. The TDA8362 supplies the reference signal (4.43 MHz) for the calibration system of the TDA8395, identification of the colour standard is via the same connection. When a SECAM signal is detected by the TDA8395 the IC will draw a current of 150 µA. When TDA8362 has not identified a colour signal in this condition it will go into the SECAM mode, that means it will switch off the R-Y and B-Y outputs and increase the voltage level on pin 32.
TDA8360; TDA8361; TDA8362
This voltage will switch off the colour-killer in the TDA8395 and switch on the R-Y and B-Y outputs of the TDA8395. Forcing the system to the SECAM standard can be achieved by loading pin 32 with a current of 150 µA. Then the system manager in the TDA8362 will not search for PAL or NTSC signals. Forcing to NTSC is not possible. For PAL/SECAM applications the input signal for the TDA8395 can be obtained from pin 27 (hue control) when this pin is connected to the positive supply rail via the 5 k or 10 k resistor. An external source selector is required by the TDA8395/TDA8362 combination for PAL/SECAM/NTSC applications. RGB output circuit The colour difference signals are matrixed with the luminance signal to obtain the RGB signals. Linear amplifiers have been chosen for the RGB inputs so that the circuit is suitable for incoming signals from the SCART connector. The contrast and brightness controls operate on internal and external signals. The fast blanking pin has a second detection level at 3.5 V. When this level is exceeded the RGB outputs are blanked so that "On-Screen-Display" signals can be applied to the outputs. The output signal has an amplitude of approximately 4 V, black-to-white, with nominal input signals and nominal control settings. The nominal black level is 1.3 V.
March 1994
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Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL VP Tstg Tamb Tsol Tj supply voltage storage temperature operating ambient temperature soldering temperature for 5 s maximum junction temperature (operating) PARAMETER
TDA8360; TDA8361; TDA8362
MIN. - -25 -25 - - 9.0
MAX. V °C °C °C °C +150 +70 260 150
UNIT
THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER from junction to ambient in free air THERMAL RESISTANCE 40 K/W
CHARACTERISTICS VP = 8 V; Tamb = 25 °C; unless otherwise specified. SYMBOL Supplies VP IP IHOSC Ptot IF circuit VISION IF AMPLIFIER INPUTS (PINS 45 AND 46) Vi(rms) input sensitivity (RMS value) note 2 fi = 38.90 MHz fi = 45.75 MHz fi = 58.75 MHz RI CI Gcr Vi(rms) Input resistance (differential) Input capacitance (differential) gain control range maximum input signal (RMS value) note 3 note 3 - - - - - 64 100 70 70 70 2 3 - - 100 100 100 - - - - µV µV µV k pF dB mV supply voltage (pin 10) supply current (pin 10) horizontal oscillator start current (pin 36) total power dissipation note 1 7.2 - 6.5 8.0 80 - 0.7 8.8 - - - V mA mA W PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
including start supply -
March 1994
11
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIDEO AMPLIFIER OUTPUT; NOTE 4 (PIN 7) V7 negative modulation zero signal output level top sync level V7 positive modulation (TDA8362) zero signal output level white level V7 V7 difference in amplitude between negative and positive modulation detection level of black level for positive modulation when no peak white is available in the signal video output impedance internal bias current of NPN emitter follower output transistor maximum source current bandwidth of demodulated output signal gain differential phase differential video non linearity white spot threshold voltage level white spot insertion voltage level noise inverter clamping voltage level noise inverter insertion level intermodulation blue yellow blue yellow S/N signal-to-noise ratio note 9 notes 7 and 10 Vo = 0.92 or 1.1 MHz 60 Vo = 0.92 or 1.1 MHz 56 Vo = 2.66 or 3.3 MHz 60 Vo = 2.66 or 3.3 MHz 60 notes 7 and 11 Vi = 10 mV end of control range V7 V7 residual carrier signal residual 2nd harmonic of carrier signal note 7 note 7 52 52 - - 60 61 1 0.5 - - - - dB dB mV mV 66 62 66 66 - - - - dB dB dB dB -3 dB note 6 notes 6 and 7 note 8 note 5 1.85 4.2 - - 2 4.3 0 3.1 2.15 4.4 15 - V V % V note 5 4.45 1.9 4.6 2 4.75 2.1 V V
ZO Ibias Isource B Gdiff diff NLvid Vth Vins Nclamp Nins mod
- 1 - 6 - - - - - - -
- - - 9 2 1 - 4.8 3.2 1.4 2.6
50 - 5 - 5 5 5 - - - -
mA mA MHz % deg % V V V V
March 1994
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Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IF AND TUNER AGC; NOTE 12
Timing of IF-AGC (C48 = 2.2 µF)
modulated video interference tinc response time for an IF input signal amplitude increase of 52 dB for positive and negative modulation response time for an IF input signal amplitude decrease of 52 dB for negative modulation for positive modulation (TDA8362) Ileak allowed leakage current of the AGC capacitor for negative modulation for positive modulation note 13 - - - 100 0.5 - - 5 - IO(max) = 1 mA 1 - - 0.2 150 - - - - - 2 10 200 µA nA - - 25 100 - - ms ms 30% AM for 1 to 100 mV; 0 to 200 Hz - - - 2 10 - % ms
tdec
Tuner take-over adjustment (pin 49)
V49(rms) V49(rms) Vcr V47 V47(sat) I47 Ileak V47 minimum starting level voltage for tuner take-over (RMS value) maximum starting level voltage for tuner take-over (RMS value) control voltage range 0.5 - 4.5 mV mV V
Tuner control output (pin 47)
maximum tuner AGC output voltage output saturation voltage maximum tuner AGC output swing leakage current RF AGC input signal variation for complete tuner control maximum gain minimum gain; I47 = 2 mA VP + 1 300 - 1 4 V mV mA µA dB
AFC OUTPUT; NOTE 14 (PIN 44) V44 fsl fos VO ZO V1 output voltage swing AFC slope AFC offset output voltage at centre frequency output impedance note 7 - - - - - - 6 33 - 3.5 50 - - - 50 - - VP - 1 V mV/kHz kHz V k
SWITCHING TO POSITIVE MODULATION (TDA8362); NOTE 15 (PIN 1) minimum voltage on pin 1 to switch the video demodulator and AGC to positive modulation input current V
II
-
-
1
mA
March 1994
13
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS - - video identified; colour signal available; fosc = 3.5 MHz -
MIN. -
TYP.
MAX.
UNIT
VIDEO IDENTIFICATION OUTPUT (PIN 4) VO ZO VO output voltage output impedance output voltage video not identified 0.5 - - V k V 25 6
- video identified; colour signal available/unavailable ;fosc = 4.4 MHz td delay time of identification after the AGC has stabilized on a new transmitter maximum load current at pin 4 -
8
-
V
-
10
ms
I4 Sound circuit
-
-
25
µA
DEMODULATOR INPUT; NOTE 16 (PIN 5) V5(rms) f RI CI AMR input limiting for PLL catching range (RMS value) catching range PLL DC input resistance input capacitance AM rejection note 17 note 3 note 3 VI = 50 mV RMS; note 18 - 4.2 100 - 60 1 - - 15 66 2 6.8 - - - mV MHz k pF dB
DE-EMPHASIS (PIN 1) VO(rms) RO V1 V50(rms) RO V50 THD S/Nint S/Next VOLcr OSS V50 output signal amplitude (RMS value) output resistance DC output voltage -6 dB; note 17 note 17 - - - 500 - - note 19 note 7 note 7 see also Fig.5 - - - - - note 20 - 350 15 3 - - - 900 - - 0.5 - - - - 50 mV k V
AUDIO ATTENUATOR OUTPUT (PIN 50) controlled output signal amplitude (RMS value) output resistance DC output voltage total harmonic distortion internal signal-to-noise ratio external signal-to-noise ratio control range suppression of output signal when mute is active DC shift of the output when mute is active 700 250 3.3 - 60 80 80 80 10 mV V % dB dB dB dB mV
March 1994
14
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS - - -
MIN.
TYP.
MAX.
UNIT
EXTERNAL AUDIO INPUT (TDA8361, TDA8362); NOTE 21 (PIN 6) V6(rms) RI GV cr input signal amplitude (RMS value) input resistance voltage gain difference between input maximum volume and output crosstalk between internal and external audio signals 350 25 12 - 700 - - - mV k dB dB
60
CVBS/On-Screen Display and CD inputs INTERNAL AND EXTERNAL CVBS INPUTS (PINS 13 AND 15) V13(p-p) I13 V15(p-p) internal CVBS input voltage (peak-to-peak value) internal CVBS input current external CVBS input voltage; TDA8361, TDA8362 (peak-to-peak value) external CVBS input current; TDA8361, TDA8362 suppression of non-selected CVBS input signal; TDA8361, TDA8362 note 23 note 3 notes 3 and 22 - - - 2 4 1 2.8 - 1.4 V µA V
I15 ISS
- 50
4 -
- -
µA dB
COMBINED CHROMINANCE AND SWITCH INPUT (TDA8361, TDA8362; PIN 16) V16(p-p) V16(p-p) RI CI V16 V16 V16 SSCVBS chrominance input voltage (peak-to-peak value) notes 3 and 24 - 1 - note 3 - - VP - 0.5 3 50 0.3 - 15 - - - 4 - - - - 5 0.5 - 5 - V V k pF V V V dB
input signal amplitude before clipping note 7 occurs (peak-to-peak value) chrominance input resistance chrominance input capacitance DC input voltage to switch the A/V switch to internal mode DC input voltage to switch the A/V switch to external mode DC input voltage for chrominance insertion suppression of non-selected notes 7 and 23 chrominance signal from CVBS input
March 1994
15
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS -
MIN.
TYP.
MAX.
UNIT
RGB INPUTS FOR ON-SCREEN DISPLAY (PINS 22, 23 AND 24) V22,23,24(p-p) input signal amplitude for an output signal of 4V (black-to-white) (peak-to-peak value) input signal amplitude before clipping occurs (peak-to-peak value) difference of black level of internal and external signals at the outputs input currents note 25 0.7 0.8 V
V22,23,24(p-p) Vdiff I22,23,24 VI VI V21(max) td I21 SSint
1 - - no data insertion data insertion data insertion - 0.9 - - - note 23 46
- - 0.1 - - - - 0.2 -
- 100 - 0.4 - 3 20 - -
V mV µA V V V ns mA dB
FAST BLANKING (PIN 21) fast blanking input voltage fast blanking input voltage maximum input pulse delay of data insertion input current suppression of internal RGB signals with data insertion at f = 0 to 5 MHz suppression of external RGB signals with data insertion at f = 0 to 5 MHz input voltage to blank the RGB outputs to facilitate `On-Screen-Display' signals being applied to these outputs delay between the input pulse and the blanking at the output
SSext
note 23
46
-
-
dB
VI
note 26
4
-
-
V
td
note 7
-
30
-
ns
COLOUR DIFFERENCE INPUT SIGNALS (PINS 28 AND 29) V29(p-p) V28(p-p) I28,29 input signal amplitude (R-Y) (peak-to-peak value) input signal amplitude (B-Y) (peak-to-peak value) input current for both inputs - - - 1.05 1.35 0.1 - - 1.0 V V µA
Chrominance filters CHROMINANCE TRAP CIRCUIT ftrap QF SR trap frequency trap quality factor colour subcarrier rejection notes 7 and 27 - - 20 - note 7 - fSC 2 - fSC 3 - - - - - dB MHz
CHROMINANCE BANDPASS CIRCUIT fc QBP centre frequency bandpass quality factor MHz
March 1994
16
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Delay line and peaking circuit Y DELAY LINE td B delay time bandwidth of internal delay line 28, SEE ALSO FIG.6 (PIN 14) at 50% of pulse; note 7 - - - - 160 50 1 7 - - - - ns IRE mA V note 7 note 7 - 8 480 - - - ns MHz
PEAKING CONTROL; NOTE
tW Scth I14 VI
width of preshoot or overshoot peaking signal compression threshold input current when no video input signal present voltage level to switch off peaking
Horizontal and vertical synchronization circuits SYNC VIDEO INPUT (TDA8361, TDA8362; PINS 13 AND 15) V13 SL
VERTICAL SYNC
sync pulse amplitude slicing level
referenced to pin 15; note 3 note 29
50 - 22
300 50 -
- - -
mV % µs
tW
width of the vertical sync pulse without sync instability
note 30
HORIZONTAL OSCILLATOR ffr ffr fosc/VP fosc/T fosc( max) free running frequency spread on free running frequency frequency variation with respect to the supply voltage frequency variation with temperature maximum frequency deviation at the start of the horizontal output VP = 8 V ±10%; note 7 note 44 - - - 15625 - 0.2 1 - - ±2 0.5 - 75 Hz % % Hz/K %
Tamb = 25 °C ±50 °C; - note 7 -
FIRST CONTROL LOOP; NOTE 31 (FILTER CONNECTED TO PIN 40) fHR fCR S/N holding range PLL catching range PLL signal-to-noise ratio of the video input signal at which the time constant is switched hysteresis at the switching point note 7 - ±0.6 - ±0.9 ±0.9 20 ±1.2 - - kHz kHz dB
HYS
-
3
-
dB
March 1994
17
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL i/o tcr tshift i/o V39 II VOL IO(max) VO(max) df I38 VO VO VIcl tW tW td PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS -
MIN.
TYP. - - - - -
MAX.
UNIT µs/µs µs µs µA/µs V µA V mA V % µA V V V µs lines µs
SECOND CONTROL LOOP; NOTE 32 (CAPACITOR CONNECTED TO PIN 39) control sensitivity control range from start of horizontal output to flyback maximum horizontal shift range shift control sensitivity voltage to switch on the X-ray protection input current during protection note 7 note 7 without RL on pin 39 150 12 - 3 - - - - - 50 - 5.3 2.0 3.0 3.5 14 5.4 11 ±2 - 6 - IO = 10 mA - 10 - note 7 - 100 4.8 1.8 2.6 3.3 note 33 - 5.2
tbf
HORIZONTAL OUTPUT (PIN 37) LOW level output voltage maximum allowed output current maximum allowed output voltage duty factor 0.3 - VP - 300 5.8 2.2 3.4 3.7 - 5.6
FLYBACK INPUT/SANDCASTLE OUTPUT (PIN 38) required input current during flyback pulse output voltage during burst key output voltage during blanking clamped input voltage during flyback burst key pulse width vertical blanking pulse width delay of start of burst key to start of sync note 7
VERTICAL SECTION; NOTE 34 ffr flock free running frequency locking range divider value not locked locking range (lines/frame) VERTICAL RAMP GENERATOR (PIN 42) I42 Idis Vsaw(p-p) td input current during scan discharge current during retrace sawtooth amplitude (peak-to-peak value) delay from field-to-field in 50 Hz mode note 7 - - - - - 0.3 1.5 - 2 - 1.8 1.6 µA mA V µs - 45 - 488 50/60 - 625/525 - - 64.5 - 722 Hz Hz
March 1994
18
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL VERTICAL OUTPUT (PIN 43) IO Iint VO(max) VO(min) V41 V41 I41 tp T/V VGL available output current internal bias current of NPN emitter follower maximum available output voltage minimum available output voltage note 7 PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS
MIN. -
TYP. - - -
MAX.
UNIT
1 - 4 - 2.0 - -
mA mA V V
0.2 - - 2.5 1 - 3 - -
0.3
VERTICAL FEEDBACK INPUT (PIN 41) DC input voltage AC input voltage input current internal pre-correction to sawtooth temperature dependency on amplitude vertical guard switching level with respect to the DC feedback level; switching level LOW vertical guard switching level with respect to the DC feedback level; switching level HIGH delay of scan start power on at 60 Hz note 35 T = 40 °C 3.0 - 15 - 1 -1.5 V V µA % % V
- - -
VGH
-
-
+1.5
V
td
-
140
-
ms
Colour demodulation part CHROMINANCE AMPLIFIER ACCcr V THRon HYSoff ACC control range change in amplitude of the output signals over the ACC range threshold colour killer ON hysteresis colour killer OFF strong input signal noisy input signal ACL CIRCUIT chrominance burst ratio at which the ACL starts to operate REFERENCE PART 2.3 - 2.7 note 7 S/N 40 dB - - +3 +1 - - dB dB note 36 26 - -30 - - - - 2 -38 dB dB dB
Phase-locked loop; note 37
fCR catching range phase shift for a ±200 Hz deviation of note 7 the oscillator frequency 300 - - - - 2 Hz deg
March 1994
19
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS - - - - - -
MIN.
TYP.
MAX.
UNIT
Oscillator
TCosc fosc RI RI CI R temperature coefficient of fosc fosc deviation with respect to VP input resistance (pin 34) input resistance (pin 35) input capacitance (pins 34 and 35) required resistance to VP to force the oscillator into one crystal mode note 7 note 7; VP = 8 V ±10% fi = 3.58 MHz; note 4 fi = 4.43 MHz; note 4 note 4 2.0 - 1.5 1 - 47 2.5 250 - - 10 - Hz/K Hz k k pF k
HUE CONTROL AND CHROMINANCE OUTPUT (TDA8361, TDA8362); NOTE 38 (PIN 27) HUEcr HUE HUE/T R hue control range hue variation for ±10% VP hue variation with temperature value of resistor connected to VP to switch the PAL decoder and to obtain a chrominance input signal for the TDA8395 (TDA8362) chrominance output signal to the TDA8395 (peak-to-peak value) see also Fig.7 note 7 Tamb = 0 to +7 °C; note 7 ±45 - - 4.7 ±60 0 0 10 - 5 - 12 deg deg deg k
VO(p-p)
nominal output signal -
330
-
mV
DEMODULATORS V30(p-p) V31(p-p) G (R-Y) output signal amplitude (peak-to-peak value) (B-Y) output signal amplitude (peak-to-peak value) gain ratio of both demodulators G(B-Y)/G(R-Y) spread of signal amplitude ratio PAL/NTSC ZO B V30,31(p-p) output impedance (R-Y)/(B-Y) output bandwidth of demodulators residual carrier output voltage (peak-to-peak value) (R-Y) output (B-Y) output V30,31(p-p) residual carrier output voltage (peak-to-peak value) (R-Y) output (B-Y) output f = 2fosc - - - - 10 10 mV mV -3 dB; note 40 f = fosc - - - - 10 10 mV mV note 7 note 39 note 39 - - 1.6 -1 - - 0.525 0.675 1.78 - 250 650 - - 1.96 +1 - - dB kHz V V
March 1994
20
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL DEMODULATORS V30(p-p) VO/T VO/VP e H/2 ripple at (R-Y) output (peak-to-peak value) change of output signal amplitude with temperature change of output signal amplitude with supply voltage phase error in the demodulated signals PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS - - - -
MIN. -
TYP.
MAX.
UNIT
only burst fed to input note 7 note 7
25 - ±0.1 5
mV %/K dB deg
0.1 - -
COLOUR DIFFERENCE MATRIXES IN CONTROL CIRCUIT G-Y/-(R-Y) G-Y/-(B-Y) -(B-Y) -(R-Y) G-Y NTSC mode; the CD matrix results in nominal hue setting the following signal (1.14/-10°) NTSC mode; the CD matrix results in nominal hue setting the following signal (1.14/100°) NTSC mode; the CD matrix results in the following signal (0.30/235°) nominal hue setting PAL/SECAM mode with TDA8362/TDA8395 -(R-Y) and -(B-Y) not affected - - -0.51 ±10% -0.19 ±25% - -
-1.12UR - 1.12VR -0.20UR + 1.12VR -0.25VR - 0.17UR
REFERENCE SIGNAL OUTPUT FOR TDA8395 (TDA8362; PIN 32) fref V32(p-p) VO VO reference frequency output signal amplitude (peak-to-peak value) output voltage level output voltage level PAL/NTSC identified no PAL/NTSC; SECAM (by TDA8395) identified note 41 - 0.2 - - 4.43 0.25 1.5 5 - 0.3 - - MHz V V V
I32
required current to force TDA8362/TDA8395 combination in SECAM mode
150
-
-
µA
Control part SATURATION CONTROL; NOTE 25 (PIN 26) SATcr SAT/V II Vctr saturation control range saturation level change input current control voltage to switch colour PLL in the free-running mode see also Fig.8 VP = ±10%;note 7 no colour identified note 37 52 - - VP - 1 - 0 1 - - - - - dB % mA V
March 1994
21
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS - -
MIN.
TYP. -
MAX.
UNIT
CONTRAST CONTROL; NOTE 25 (PIN 25) CONcr contrast control range tracking between the three channels over a control range of 10 dB BRIGHTNESS CONTROL (PIN 17) BRIcr V18,19,20(p-p) brightness control range see also Fig.10 - 3.5 ±1 4.0 - 4.5 V see also Fig.9 20 - dB dB 0.7
RGB AMPLIFIERS (PINS 18, 19 AND 20) output signal amplitudes (peak-to-peak value) nominal luminance input signal and nominal contrast; note 25 nominal settings for contrast and saturation control and no luminance signal to the R-Y signal (PAL) note 25 note 42 V
V20(p-p)
output signal amplitudes for the RED channel (peak-to-peak value)
3.8
4.2
4.6
V
V18,19,20 V18,19,20 Vpwl IO ZO Isource
blanking level at the RGB outputs black level at the RGB outputs maximum peak white level available output current output impedance current source of output stage relative spread between the RGB output signals
0.5 1.2 - 5 - 1.8 -
0.6 1.3 6 - 150 2.0 -
0.8 1.4 - - - - 5
V V V mA mA %
S/N
signal-to-noise ratio of output signals note 43 for RGB input for CVBS input note 7 note 7 note 23 - 50 - - 60 56 - - - - 25 25 dB dB mV mV
fres(p-p) fres(p-p)
residual frequency at fosc in the RGB outputs (peak-to-peak value) residual frequency at 2fosc plus higher harmonics in the RGB outputs (peak-to-peak value) difference in black level between the three outputs black level shift with picture content variation of black level with temperature
Vdiff Vbl bl/T
nominal brightness note 7 note 7
- - -2
- 0 -
100 - 0
mV mV mV/K
March 1994
22
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
SYMBOL bl/CON bl/SAT bl PARAMETER
TDA8360; TDA8361; TDA8362
CONDITIONS - -
MIN. - -
TYP.
MAX.
UNIT
RGB AMPLIFIERS (PINS 18, 19 AND 20) variation of black level over contrast range variation of black level over saturation range relative variation in black level between the three channels during variations of supply voltage (±10%) saturation (50 dB) contrast (20 dB) brightness (±0.5 V) Vdiff B differential drift of black level over a temperature range of 40 °C bandwidth of output signals for RGB input CVBS input CVBS input S-VHS input Notes to the "Characteristics" 1. It is possible to start the horizontal oscillator when a current of 5.5 mA is supplied to this pin. In this condition the main part of the IC is not active and this results in the frequency of the oscillator not being controlled at the correct value. Consequently, the oscillator frequency will be higher than normal, the maximum deviation will be 75%. When the start-up function is used the maximum voltage on pin 36 must be limited to 8.8 volts. 2. On set AGC. 3. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 4. Measured at 10 mV RMS top sync input signal. 5. So called projected zero point, i.e. with switched demodulator. 6. Measured in accordance with the test line given in Fig.11. For the differential phase test the peak white setting is reduced to 87%. The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. The phase difference is defined as the difference in degrees between the largest and smallest phase angle. 7. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 8. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.12. 9. Insertion (suppression of the interference pulses) to a level of 2.6 V is active only during a strong input signal. This is because the noise inverter has a negative effect on the sound performance at a weak input signal. 10. The test set-up and input conditions are given in Fig.13. The figures are measured with an input signal of 10 mV RMS. fosc = 3.58 MHz fosc = 4.43 MHz nominal saturation nominal contrast nominal saturation nominal controls note 7 -3 dB 8 - - 8 - 2.8 3.5 - - - - - MHz MHz MHz MHz - - - - - - - - - - 50 25 60 100 10 mV mV mV mV mV nominal saturation; note 7 nominal contrast; note 7 100 50 mV mV
March 1994
23
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
11. Measured with a source impedance of 75 , where: V O (black-to-white) S/N = 20 log -------------------------------------------------------V m ( rms ) ( B = 5 MHz )
TDA8360; TDA8361; TDA8362
12. To obtain a good noise immunity of the AGC circuit the AGC detector is gated during the sync pulse. This gating is switched off during the vertical retrace to avoid disturbances of the signal amplitude due to phase errors of the incoming video signal which are caused by the head-switching of VCRs. 13. When the leakage current of the capacitor exceeds this value it will result in a reduced performance of the AGC (amplitude variation during line or frame) but it will not result in a hang-up situation. 14. The AFC slope is directly related to the Q-factor of the demodulator tuned circuit. The given AFC steepness is obtained with a Q-factor of 60. When a lower steepness is required this can be obtained by connecting an external resistor to the AFC output (the output impedance is 50 k). The AFC off-set is tested with a double sideband input signal and with the reference tuned circuit tuned to minimum AGC voltage (optimum tuning for the demodulator). 15. For positive modulated signals the FM sound demodulator for the sound is not required. This is because the sound signal is amplitude modulated. Therefore the TDA8362 can be switched to positive modulation via the de-emphasis pin (pin 1). When switched to positive modulation the audio switch is set to `external' so that the demodulated audio signal can be supplied to the input. The option between AM sound and SCART audio signals is achieved by means of an external switch. 16. The sound IF input is combined with the AF volume control. The IF signal is internally AC coupled to the limiter amplifier. The volume control voltage must be supplied to this pin via a resistor. 17. VI = 100 mV RMS; FM: 1 kHz, f = ±50 kHz. 18. VI = 50 mV RMS, f = 4.5/5.5 MHz; FM: 70 Hz ±50 kHz deviation AM: 1 kHz at 30% modulation. 19. VI = 100 mV RMS, 5.5 MHz; FM: 1 kHz, ±17.5 kHz deviation; 15 kHz bandwidth; audio attenuator at -6 dB. 20. Audio attenuator at -20 dB; temperature range 10 to 50 °C. 21. In the TDA8361 and TDA8362 the audio and CVBS switches are controlled via the chrominance input pin. Table 1 lists the various possibilities. When the DC voltage has a value between 3 and 5 V the switches are set to the S-VHS position. The chrominance trap is then switched off and separate Y and chrominance signals have to be applied to the inputs (the audio switch is set to external in this condition). The audio switch is also set to external when the IF amplifier is switched to positive modulation (see also note 15). 22. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 23. This parameter is measured at nominal settings of the various control voltages. 24. Burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mV (p-p). 25. Nominal contrast is specified as maximum contrast -3 dB. Nominal saturation as maximum -12 dB. The nominal brightness control voltage is 2.5 V. 26. When the data blanking input pulse exceeds a level of 4 V the RGB outputs are blanked. In this condition it is possible to supply `On-Screen-Display' signals to the outputs. This blanking overrules both the internal and external RGB signals. 27. The -3 dB bandwidth of the circuit can be calculated by means of the following equation: 1 f 3 dB = f osc 1 ------- 2Q
March 1994
24
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
28. The amplitude response curve can be expressed as follows: A(f) = 1 + K1 - cos (180 x f/3.1 MHz)
TDA8360; TDA8361; TDA8362
and is realised with a transversal peaking filter having delay sections of 160 ns each. In the `neutral' setting K = 0 and in the minimum setting K = -0.5. The peaking signal amplifier is linear for 250 ns step input signals up to 50 IRE units. For higher amplitudes the marginal gain is reduced. When the horizontal PLL is not synchronized (no signal present at the video input) the peaking control voltage is pulled down by means of an internal current. This information can be used to detect whether an input signal is available. 29. Slicing level independent of sync pulse amplitude. 30. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 µs. 31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time constant is switched to `slow' when excessive noise is present in the signal (only when the internal video signal is selected, when the video switch is in the external mode the time constant is always `fast'). In the `fast' mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. When no video signal is received the time constant of the first loop is switched to `very slow'. This ensures a stable OSD when the receiver is switched to a channel without transmitter. The output current of the phase detector for the various conditions is shown in Table 2. 32. Picture shift can be obtained by means of a variable external load on the second phase detector. The control range is ±2 µs; the required current for this phase shift is ±6 µA. 33. The vertical blanking pulse in the RGB outputs has a width of 22 or 17.5 lines (50 or 60 Hz system). The width of the vertical sync pulse in the sandcastle pulse is 14 lines. This is to prevent a phase distortion on top of the picture due to a timing modulation of the incoming flyback pulse. 34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 2 search modes of operation: The `large window' mode is switched on when the circuit is not synchronized or, when a non-standard signal is received (the number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz) The `narrow window' mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. 35. This precorrection is intended to compensate for non-linearity of AC coupled vertical output stages. The value given indicates the amplitude of the correction waveform with respect to the sawtooth amplitude. 36. At a chrominance input voltage (related to CVBS2) of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)) the dynamic range of the ACC is +6 and -20 dB.
March 1994
25
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
TDA8360; TDA8361; TDA8362
37. All frequency variations are referenced to 3.58/4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520. If the spurious response of the 4.43 MHz crystal is lower than -3 dB with respect to the fundamental frequency for a damping resistance of 1 k, oscillation at the fundamental frequency is guaranteed. The spurious response of the 3.58 MHz crystal must be lower than -3 dB with respect to the fundamental frequency for a damping resistance of 1.5 k. The catching and detuning range are measured for nominal crystal parameters. These are: a) load resonance frequency f0 (CL = 20 pF) = 4.433619 or 3.579545 MHz b) motional capacitance CM = 20.6 fF (4.43 MHz crystal) or (3.58 MHz crystal) c) parallel capacitance C0 = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal). The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. The free-running frequency of the oscillator can be checked by pulling the saturation control pin to the positive supply rail. In that condition the colour killer is not active so that the frequency off-set is visible on the screen. When two crystals are connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator continuously switching between the two frequencies. 38. In the TDA8362 the hue control pin has a double function. When the control voltage has a value of 0 to 5 V (normal control range) the hue can be controlled when NTSC signals are decoded. When this voltage is increased to a value greater than 5.5 V the decoder is forced to the PAL standard. When this pin is connected to the positive supply line via a 10 k resistor the selected CVBS signal, of the CVBS switch, is available. This signal can be applied to the SECAM decoder TDA8395. The phase shift of the hue control can be measured at the colour difference outputs (pins 30 and 31). 39. The -(R-Y) and -(B-Y) signals are demodulated with the 90° phase difference of the reference carrier and a gain ratio -(B-Y)/-(R-Y) = 1.78. The matrixing to the required signals is achieved in the control part. 40. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter. The bandwidth of the demodulator low-pass filter is approximately 1 MHz. 41. The reference signal for the TDA8395 is available only when the crystal oscillator is operating at a frequency of 4.43 MHz. When a SECAM signal is identified this signal is only available during the vertical retrace period thus avoiding crosstalk with the incoming SECAM signal during scan. 42. When one of the three output signals exceeds this level the gain of the amplifiers is reduced. This is achieved by a reduction of contrast and thus avoids clipping of the output signals. The discharge current at pin 25 is 0.2 mA. When the black level exceeds a value of 2 V the maximum peak-to-peak value of the video output signal will be less than 4 V (p-p); this is due to the operation of the peak-white limiter. 43. The signal-to-noise ratio is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). During the measurement the peaking control voltage is set to nominal. 44. The typical free running frequency is dependent on the crystal which is used for calibration. With 4.4 MHz the typical free running frequency is 15625, with 3.58 MHz the typical free running frequency is 15734. Calibration during start-up is always carried out with a 4.4 MHz crystal if no forced mode is used.
March 1994
26
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
Table 1 Audio and CVBS switch selection. LEVEL (pin 16) DC 0.5 V 3 DC 5 V DC 7.5 V INTERNAL CVBS ON OFF OFF EXTERNAL CVBS/Y OFF ON (Y) ON (CVBS)
TDA8360; TDA8361; TDA8362
CHROMINANCE OFF ON OFF
CHROMINANCE TRAP ON OFF ON
AUDIO internal external external
Table 2 Output current of phase detector. CURRENT 1 DURING Weak signal and synchronized Strong signal and synchronized Not synchronized No video identification SCAN (µA) 30 180 180 6 VERTICAL RETRACE (µA) 30 270 270 6 GATED YES/NO YES (5.7 µs) NO NO NO
QUALITY SPECIFICATION Quality level in accordance with UZW B0/FQ-0601. SYMBOL ESD PARAMETER protection circuit specification (note 1) RANGE A 2000 100 1500 Note 1. All pins are protected against ESD by means of internal clamping diodes. RANGE B 200 200 0 V pF UNIT
March 1994
27
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
TDA8360; TDA8361; TDA8362
MBC208
MBC207 - 1
0 (dB) 20
50 (%) 30
40
10
60
10
80
30
100
0
1
2
3
4
(V)
5
50
0
1
2
3
4
(V)
5
Fig.5 Volume control curve.
Fig.6 Peaking control curve.
MBC206 - 1
60 (deg) 40 300 (%) 20 250
MBC204
200 0 150 20 100 40
50
60
0
1
2
3
4
(V)
5
0
0
1
2
3
4
(V)
5
Fig.7 Hue control curve
Fig.8 Saturation control curve.
March 1994
28
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
TDA8360; TDA8361; TDA8362
MBC205
100 (%) 80 (V) 60 0 40 1.0
MBC209
20 1.0 0 0 1 2 3 4 5 0 1 2 3 4 (V) 5
(V)
Fig.9 Contrast control curve.
Fig.10 Brightness control curve.
MBC212
16 %
100% 92%
30% for negative modulation 100% = 10% rest carrier
Fig.11 Video output signal.
March 1994
29
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
TDA8360; TDA8361; TDA8362
andbook, full pagewidth
MBC211
100% 86% 72% 58% 44% 30% 10 12 22 26 32 36 40 44 48 52 56 60 64 µs
Fig.12 Test signal waveform.
handbook, full pagewidth
3.2 dB 10 dB 13.2 dB 30 dB 13.2 dB 30 dB
SC CC BLUE
PC
SC CC YELLOW
PC
MBC213
PC
SC
ATTENUATOR
TEST CIRCUIT
SPECTRUM ANALYZER
CC
gain setting adjusted for blue
MBC210
Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier. All amplitudes with respect to top sync level. V O at 3.58 or 4.4 MHz Value at 0.92 or 1.1 MHz = 20 log ----------------------------------------------------------- + 3.6 dB V O at 0.92 or 1.1 MHz V O at 3.58 or 4.4 MHz Value at 2.66 or 3.3 MHz = 20 log ----------------------------------------------------------V O at 2.66 or 3.3 MHz
Fig.13 Test set-up intermodulation.
March 1994
30
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
PACKAGE OUTLINE
TDA8360; TDA8361; TDA8362
handbook, full pagewidth
seating plane
47.92 47.02 4.57 5.08 max max
15.80 15.24
3.2 2.8
0.51 min 1.73 max 1.778 (25x) 0.53 max 0.18 M 0.32 max 15.24 1.3 max 17.15 15.90
MSA267
52
27
14.1 13.7
1
26
Dimensions in mm.
Fig.14 52-lead shrink dual in-line; plastic (SOT247AG).
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
REPAIRING SOLDERED JOINTS Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 °C, it must not be in contact for more than 10 s; if between 300 and 400 °C, for not more than 5 s.
March 1994
31
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8360; TDA8361; TDA8362
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
March 1994
32
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
NOTES
TDA8360; TDA8361; TDA8362
March 1994
33
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
NOTES
TDA8360; TDA8361; TDA8362
March 1994
34
Philips Semiconductors
Objective specification
Integrated PAL and PAL/NTSC TV processors
NOTES
TDA8360; TDA8361; TDA8362
March 1994
35
Philips Semiconductors a worldwide company
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Philips Semiconductors