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VER : F3B
VM8G Block Diagram Intel Discrete GFX
A A
FAN & THERMAL POWER
Penryn EMC1423-1-AIZL-TR
PG 36 REGULATOR CPU VR
POWER (478 Micro-FCPGA) +1.5V_RUN/+1.05V_VCCP PG 42 PG 44
CLOCK REGULATOR REGULATOR
SLG8SP513V +1.8V_SUS /+0.9V_DDR_VTT +3.3V_ALW/+5V_SUS/+15V_ALW
BATT (QFN-64)
PG 3,4
AC/BATT CHARGER PG 41 PG 17 PG 43 PG 45
CONNECTOR 800/1066 MHz
RUN POWER SW
PG 47 +3.3V_SUS/+5V_SUS
+5V/+3.3V/+1.8V PG 46 LVDS Panel Connector
PCIEx16
Cantiga ATI M92-S2 LP (WXGA) PG 25
B
DDR2 x 4 PCI EXPRESS GFX VGA B
CRT CONN.
DDR2-SODIMM*2 667/800 MHZ DDR II 1299 uFCBGA (512M 64bits) 631 uFCBGA 23mm*23mm PG 26
PG 22
PG 15,16 PG 18,19,20,21,22,23,24
PG 5,6,7,8,9,10 RTL8111DL RJ45/Magnetics
GLAN PG 39
PG 39
DMI interface
SATA-ODD SATA PCIE
PG 33 PCIE MINI-CARD
WLAN
PG 31
SATA-HDD SATA PCIE
PG 33 ICH9-M
PCIE
Bluetooth USB 2.0 676 BGA
C USB2.0 EXPRESS-CARD34 C
PG 31 PG 28
USB2.0
IHDA USB conn x 2 PG 32
PG 11,12,13,14
USB conn x 2
Board to board PG 38
LPC
USB2.0
AUDIO/AMP Panel Connector
MODEM (AMOM) (To CCD) PG 25
CX20583-10z
CX20548-11Z
PCIE 3-in-1 Card Reader Card Reader CONN.
PG 37 Board to board KBC
ITE8502 R5U230(1394a+Media)
18X8 1394a CONN
Keyboard
Audio PG 29 Board to board PG 38
Audio SPK RJ-11conn PG 34
D
Jacks x2 D
conn 2Wx1 SPI PS/2
PG 37 PG 38
PG 37 USER QUANTA
FLASH
2M bytes
Touchpad INTERFACE
Title
COMPUTER
PG 35 Schematic Block Diagram
PG 30 PG 34 Size Document Number Rev
VM8G 1B
Date: Saturday, June 06, 2009 Sheet 1 of 53
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Table of Contents Power States
CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE PAGE DESCRIPTION ACTIVE IN
SIGNAL
1 Schematic Block Diagram
2 Front Page +PWR_SRC 10V~+19V 4,25,30,39,41,42,43,44,45,49,50 MAIN POWER S0~S5
3-4 Penryn
+RTC_CELL +3.0V~+3.3V 11,14,29,30 RTC S0~S5
5-10 Cantiga
A 11-14 ICH9M +3.3V_ALW +3.3V 3,13,29,30,35,39,40,41,43,45,46,47 8051 POWER ALWON S0~S5 A
15-16 DDRII SO-DIMM(200P)
+5V_ALW2 +5V 42,43,45,46,47,49 LCD/CHARGE POWER ALWON S0~S5
17 Clock Generator
18-24 M92-S2 +15V_ALW +15V 25,45,46 LARGE POWER +5V_ALW S0~S5
25 LCD Conn.
+3.3V_LAN +3.3V 39 LAN POWER AUX_ON
26 CRT Conn
27 BLANK PAGE +5V_SUS +5V 14,32,35,44,45,46,49,50 SLP_S5# CTRLD POWER SUS_ON
28 Express Card
+3.3V_SUS +3.3V 3,11,12,13,14,19,25,28,35,42,44,46,49 SLP_S5# CTRLD POWER 3.3V_SUS_ON
29 SIO (ITE8512)
30 FLASH/RTC +1.8V_SUS +1.8V 6,8,9,15,42,43,46,49 SODIMM POWER DDR_ON
31 Mini Card / BT
+0.9V_DDR_VTT +0.9V 16,43,46 SODIMM POWER 0.9V_DDR_VTT_ON
32 USB
33 SATA Conn +5V_RUN +5V 14,20,25,26,33,34,35,36,37,46,50 SLP_S3# CTRLD POWER RUN_ON
34 TP / KEYBOARD 3,6,8,9,11,12,13,14,15,17,19,25,26,27,28,29,
+3.3V_RUN +3.3V 31,33,35,36,37,39,46,50 SLP_S3# CTRLD POWER 3.3V_RUN_ON
35 SWITCH /LED
B 36 FAN & Thermal +1.5V_RUN +1.5V 4,9,14,28,31,42,46,50 CALISTOGA/ICH8 POWER 1.5V_RUN_ON B
37 Audio CODEC(CX20583-10z)/Phone Jack
+1.05V_VCCP +1.05V 3,4,5,6,8,9,11,14,42,50 CPU/CALISTOGA/ICH8 POWER 1.05V_RUN_ON
38 Module Board
39 LAN / TRANSFORM +VCC_CORE +0.7V~+1.77V 4,44 CPU CORE POWER IMVP_VR_ON
40 BLANK PAGE LCDVCC_TST_EN
+LCDVCC +3.3V 25 LCD Power & ENVDD
41 Charger (MAX8731A)
42 1.05VCCP / 1.5VRUJN +5V_MOD +5V 33 Module Power MODC_EN#
43 DDR2_1.8VSUS, 0.9V
+5V_HDD +5V 33 HDD Power HDDC_EN#
44 CPU MAX17410 (2phase)
45 MAX17020 (+5.5V,+3,3V) +PBATT +10V~+17V MAIN BATTERY CHG_PBATT
46 RUN Power Switch
+SBATT +10V~+17V SECOND BATTERY CHG_SBATT
47 DCIN,Batt
48 PAD& SCREW +1.1V_GFX_PCIE +1.1V 20 GFX PCIE POWER GFX_RUN_ON
49 VGA GFX CORE
+VCC_GFX_CORE +0.9~+1.1 20,23,49 GFX CORE POWER GFX_RUN_ON
50 EMI CAP
C C
51 SMBUS BLOCK
52 Power Block Dianram GND PLANE PAGE DESCRIPTION
GND ALL
D D
QUANTA
Title
COMPUTER
Index & Power Status
Size Document Number Rev
VM8G 1B
Date: Tuesday, June 02, 2009 Sheet 2 of 53
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_A#[3..16] U13A H_D#[0..63] U13B H_D#[0..63]
[5] H_A#[3..16] [5] H_D#[0..63] H_D#[0..63] [5]
H_A#3 J4 H1 H_D#0 E22 Y22 H_D#32
A[3]# ADS# H_ADS# [5] D[0]# D[32]#
H_A#4 L5 E2 H_D#1 F24 AB24 H_D#33
A[4]# BNR# H_BNR# [5] D[1]# D[33]#
ADDR GROUP 0
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# [5] D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# [5] F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# [5] D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# [5] D[6]# D[38]#
DATA GRP 0
DATA GRP 2
H_A#10 N3 H_D#7 E23 U23 H_D#39
A[10]# H_BR0# [5] D[7]# D[39]#
H_A#11 P5 F1 H_D#8 K24 Y25 H_D#40
H_A#12 A[11]# BR0# R22 56 H_D#9 D[8]# D[40]# H_D#41
P2 A[12]# G24 D[9]# D[41]# W22
CONTROL
H_A#13 L2 D20 H_IERR# 1 2 +1.05V_VCCP H_D#10 J24 Y23 H_D#42
A
H_A#14 A[13]# IERR# H_D#11 D[10]# D[42]# H_D#43 A
P4 A[14]# INIT# B3 H_INIT# [11] J23 D[11]# D[43]# W24
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# [5] F26 D[13]# D[45]# AA23
M1 Reserve from EMI H_D#14 K22 AA24 H_D#46
[5] H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[14]# D[46]#
C1 R58 1 2 0 603 H_RESET# H_D#15 H23 AB25 H_D#47
[5] H_REQ#[0..4] RESET# H_RESET# [5] D[15]# D[47]#
H_REQ#0 K3 F3 J26 Y26
REQ[0]# RS[0]# H_RS#0 [5] [5] H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 [5]
H_REQ#1 H2 F4 H26 AA26
REQ[1]# RS[1]# H_RS#1 [5] [5] H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 [5]
H_REQ#2 K2 G3 H25 U22
REQ[2]# RS[2]# H_RS#2 [5] [5] H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 [5]
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# [5] H_D#[0..63] H_D#[0..63]
H_REQ#4 L1
H_A#[17..35] REQ[4]# [5] H_D#[0..63] H_D#[0..63] [5]
G6 H_D#16 N22 AE24 H_D#48
[5] H_A#[17..35] HIT# H_HIT# [5] D[16]# D[48]#
H_A#17 Y2 E4 H_D#17 K25 AD24 H_D#49
A[17]# HITM# H_HITM# [5] D[17]# D[49]#
H_A#18 U5 H_D#18 P26 AA21 H_D#50
A[18]# D[18]# D[50]#
ADDR GROUP 1
H_A#19 R3 AD4 ITP_BPM#0 H_D#19 R23 AB22 H_D#51
A[19]# BPM[0]# PAD T31 D[19]# D[51]#
H_A#20 W6 AD3 ITP_BPM#1 Layout Note: H_D#20 L23 AB21 H_D#52
A[20]# BPM[1]# PAD T34 D[20]# D[52]#
XDP/ITP SIGNALS
H_A#21 U4 AD1 ITP_BPM#2 Place voltage H_D#21 M24 AC26 H_D#53
A[21]# BPM[2]# PAD T98 D[21]# D[53]#
DATA GRP 1
DATA GRP 3
H_A#22 Y5 AC4 ITP_BPM#3 H_D#22 L22 AD20 H_D#54
A[22]# BPM[3]# PAD T29 divider within D[22]# D[54]#
H_A#23 U1 AC2 ITP_BPM#4 H_D#23 M23 AE22 H_D#55
A[23]# PRDY# PAD T99 D[23]# D[55]#
H_A#24 R4 A[24]# PREQ# AC1 ITP_BPM#5 0.5" of GTLREF H_D#24 P25 D[24]# D[56]# AF23 H_D#56
H_A#25 T5 AC5 ITP_TCK pin H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK ITP_TDI H_D#26 D[25]# D[57]# H_D#58
T3 A[26]# TDI AA6 P22 D[26]# D[58]# AE21
H_A#27 W2 AB3 ITP_TDO H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO ITP_TMS +1.05V_VCCP H_D#28 D[27]# D[59]# H_D#60
W5 A[28]# TMS AB5 R24 D[28]# D[60]# AC22
H_A#29 Y4 AB6 ITP_TRST# H_D#29 L25 AD23 H_D#61
H_A#30 A[29]# TRST# ITP_DBRESET# H_D#30 D[29]# D[61]# H_D#62
U2 A[30]# DBR# C20 PAD T2 T25 D[30]# D[62]# AF22
2
H_A#31 V4 H_D#31 N25 AC23 H_D#63
H_A#32 A[31]# R266 D[31]# D[63]#
W3 A[32]# [5] H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 [5]
H_A#33 AA4 THERMAL R13 1 2 56 +1.05V_VCCP 1K/F M26 AF24
A[33]# [5] H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 [5]
H_A#34 AB2 N24 AC20
A[34]# [5] H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 [5]
B H_A#35 AA3 D21 H_PROCHOT# B
PAD T1
1
A[35]# PROCHOT# H_THERMDA V_CPU_GTLREF AD26 COMP0
[5] H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 GTLREF COMP[0] R26 Note:
B25 H_THERMDC R15 2 1 *1K/F_NC CPU_TEST1 C23 MISC COMP[1] U26 COMP1 H_DPRTSTP need to daisy chain
THERMDC TEST1
1
A6 R14 2 1 *1K/F_NC CPU_TEST2 D25 AA1 COMP2
[11] H_A20M# A20M# TEST2 COMP[2] from ICH9 to IMVP6 to CPU.
ICH
A5 C7 R265 PAD T87 CPU_TEST3 C24 Y1 COMP3
[11] H_FERR# FERR# THERMTRIP# H_THERMTRIP# [6,11] TEST3 COMP[3]
C4 2K/F PAD T85 CPU_TEST4 AF26
[11] H_IGNNE# IGNNE# TEST4
PAD T97 CPU_TEST5 AF1 E5
TEST5 DPRSTP# H_DPRSTP# [6,11,44]
D5 H CLK PAD T86 CPU_TEST6 A26 B5
[11] H_STPCLK# H_DPSLP# [11]
2
STPCLK# PAD T33 CPU_TEST7 TEST6 DPSLP#
[11] H_INTR C6 LINT0 C3 TEST7 DPWR# D24 H_DPWR# [5]
[11] H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK [17] [6,17] CPU_MCH_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD [11]
[11] H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# [17] [6,17] CPU_MCH_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# [5]
[6,17] CPU_MCH_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# [44]
Quard Core Only
F6 D2 Penryn Ball-out Rev 1a
TDI_1/RSV RSVD[06] PAD T32
D3 TDO_2/RSV
N5 COMP0
BMP_1#[0]/RSV COMP1
M4 BMP_1#[1]/RSV
B2 COMP2 FSB BCLK BSEL2 BSEL1 BSEL0
BMP_1#[2]/RSV COMP3
AE8 BMP_1#[3]/VSS
D8 DCLKPH_1/VSS
533 133 0 0 1
F8 ACLKPH_1/VSS
2
2
2
2
D22 GTLREF_2/RSV 667 166 0 1 1
T2 R66 R65 R262 R261
THRMDA_1/RSV 54.9/F 27.4/F 54.9/F 27.4/F
V3 THRMDC_1/RSV 800 200 0 1 0
AA8 HFPLL_1/VSS
AC8 1066 266 0 0 0
1
1
1
1
SPARE_1[4]/VSS
AA7 BR1#/VCC
C C
Penryn Ball-out Rev 1a Comp0,2 connect with Zo=27.4ohm,
Comp1,3 connect with Zo=55ohm,
make those traces length shorter than 0.5".
Populate ITP700Flex for bringup Trace Comp0,2 should be 18-Mil Wide.
Trace Comp1,3 should be 5-Mil Wide.
Place under CPU 10/20mils
REM_DIODE1_P
+3.3V_RUN
ITP_BPM#5 R61 1 2 56 +1.05V_VCCP U14
3
1
C505 1 10 SMBCLK1
VDD SCL SMBCLK1 [17,25,29]
ITP_TDO R63 2 *56_NC Q37 2200P
1
MMST3904-7-F