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CONTENTS
1. 2. 2.1 2.2 2.3 2.4 2.5 3. 4. 5. 5.1 5.2 6 6.1 6.2 7. 8. 9. 10. 11. 11.1 11.2 12. 13. 14. 15. 15.1 15.2 15.3 15.4 16. 16.1 16.2 16.3 17. 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 18. 19. 20. 20.1 20.2 CHANGE HISTORY .................................................................................................................... 4 GENERAL DESCRIPTION .......................................................................................................... 4 STI5508 ...................................................................................................................................... 4 M2 .............................................................................................................................................. 5 DRIVE INTERFACES .................................................................................................................. 5 FRONT PANEL ........................................................................................................................... 5 REAR PANEL ............................................................................................................................. 6 GPIO, IRQ, AND CHIP SELECT ASSIGNMENTS ........................................................................ 6 JUMPER CONFIGURATION ........................................................................................................ 7 AUDIO OUTPUT .......................................................................................................................... 8 AUDIO DACS .............................................................................................................................. 8 AUDIO MUTE .............................................................................................................................. 8 VIDEO INTERFACE .................................................................................................................... 8 SCART INTERFACE ................................................................................................................... 9 DIGITAL VIDEO INTERFACE ....................................................................................................... 9 MPEG DECODER SDRAM MEMORY ........................................................................................ 9 PROCESSOR SDRAM MEMORY .............................................................................................. 9 FLASH MEMORY ....................................................................................................................... 10 SERIAL EEPROM MEMORY ..................................................................................................... 10 TMM DRIVE INTERFACE ............................................................................................................ 10 CONNECTION INFORMATION .................................................................................................... 10 TMM DRIVE TRAY MOTOR CONTROL AND PUSH AND STALL SENSE CIRCUITRY................. 11 ATAPI DRIVE INTERFACE AND EPLD ........................................................................................ 11 AUDIO SAMPLING RATE AND EXTERNAL PLL COMPONENT CONFIGURATION ..................... 11 UART SERIAL PORT .................................................................................................................. 11 FRONT PANEL ........................................................................................................................... 12 FRONT PANEL MICRO ............................................................................................................... 12 VFD CONTROLLER .................................................................................................................... 12 MICROPHONE INPUTS .............................................................................................................. 12 HEADPHONE OUTPUTS ............................................................................................................ 12 MISCELLANEOUS FUNCTIONS ................................................................................................. 12 POWER DOWN .......................................................................................................................... 12 RESET CIRCUITRY .................................................................................................................... 13 VOLTAGE REGULATORS ........................................................................................................... 13 CONNECTORS ........................................................................................................................... 13 ATAPI DRIVE STANDARD CONNECTOR .................................................................................... 13 TMM DRIVE CONNECTORS ....................................................................................................... 14 STI5508 JTAG INTERFACE ......................................................................................................... 15 RS232 SERIAL PORT ................................................................................................................. 16 DIGITAL YUV OUTPUT HEADER ................................................................................................ 16 ANALOG VIDEO INPUT HEADER .............................................................................................. 16 SCART CONNECTORS .............................................................................................................. 16 POWER CONNECTOR ............................................................................................................... 17 SCHEMATICS ............................................................................................................................. 17 BILL OF MATERIALS .................................................................................................................. 17 BOARD LAYOUT ........................................................................................................................ 17 TOP SIDE ASSEMBLY DRAWING ............................................................................................. 17 BOTTOM SIDE ASSEMBLY DRAWING ...................................................................................... 17

1 CHANGE HISTORY

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1. CHANGE HISTORY Revision Rev 1.0 Rev 1.1 Date 7/23/2000 8/23/2000 Author Jim Loughin Jim Loughin Comments Initial Release Updated to match final design

2. GENERAL DESCRIPTION Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the document. 2.1 STI5508 The STi5508 provides a highly integrated back-end solution for DVD applications. A host CPU handles both the general application (the user interface, and the DVD, CD-DA, VCD, SVCD navigation) and the drivers of the different embedded peripheral (audio/video, karaoke, sub-picture decoders, OSD, PAL/NTSC encoder...). Because of its memory savings, increased number of internal peripherals, improved development platform and reference design, theSTi5508 offers a costeffective solution to DVD applications, with rapid time-to-market. These functions include: Integrated 32-bit host CPU @ 60MHz - 2 Kbytes of instruction cache, 2 Kbytes of data cache, and 4Kbytes of SRAM configurable as data cache. Audio decoder - 5.1 channel Dolby Digital� /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs - IEC60958 IEC61937 digital output - DTS� digital out 5.1 channel - SRS�/TruSurround� - MP3 decoding Karaoke processor - Echo, pitch shift, microphone inputs, voice cancellation and multiple other effects Video decoder - Supports MPEG-2 MP@ML - Fully programmable zoom-in and zoom-out - PAL to NTSC and NTSC to PAL conversion DVD and SVCD subpicture decoder High performance on-screen display - to 8 bits per pixel OSD options - Anti-flicker, anti-flutter and anti-aliasing filters PAL/NTSC/SECAM encoder - RGB, CVBS, Y/C and YUV outputs with 10-bit DACs - Macrovision� 7.01/6.1 compatible Shared SDRAM memory interface - Supports one or two 16Mbit, or one 64Mbit 125 MHZ SDRAMs Programmable CPU memory interface for SDRAM, ROM, peripherals... Front-end interface - DVD, VCD, SVCD and CD-DA compatible - Serial, parallel and ATAPI interfaces - Hardware sector filtering - Integrated CSS decryption and track buffer Integrated peripherals - UARTS, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timers - Modem support - 38 bits of programmable I/O Please refer to the STi5508 Data Sheets: STi5508 DVD HOST PROCESSOR WITH ENHANCED AUDIO FEATURES and STi5508 REGISTER MANUAL for more detailed information. 2.2 MEMORY The STi5508 includes all of the interface signals to connect to industry standard SDRAM, DRAM, ROM, and I2C memory devices. The system includes one or two SDRAM components. The MPEG decoder unit interfaces to a single 4M x 16bit SDRAM over the SMI bus. The general purpose processor can share the decoder SDRAM or can access an optional SDRAM installed on the EMI bus. This EMI SDRAM can be either a 1Mx16 or 4Mx16 chip. The optional EMI SDRAM can be installed if the system requires higher performance of requires more RAM than is standard system (due to complex trick modes, advanced GUI, etc). The standard production Ravisent CineMasterCE software will execute without EMI SDRAM installed, however EMI SDRAM is required to perform debugging and prototyping. A single 1Mx16 FLASH ROM device is support on the EMI bus. There is also a small I�C serial EEPROM (from 1Kbit to 256Kbit) for storage of user player settings, software configuration information, title specific information, or other purposes.
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2.3 DRIVE INTERFACES The system supports either a standard ATAPI drive interface or the SGS Thomson TVM502 drive (simply called TMM). The TMM drive is supplied with either a three connector interface or a single FFC cable connection. The design supports either connection method. The TMM three connector interface utilizes separate connectors for power, data, and drive tray motor control. Circuitry to control the TMM drive tray is located on the decoder board when this TMM drive version is used. The interface to the ATAPI drive is included within the STi5508. The ATAPI data bus is buffered so that the ATAPI cable does not interfere with signal quality. An ATAPI drive is connected via the standard 34 pin dual row PC style IDE header. An IDE power connector is also supported for convenience. 2.4 FRONT PANEL The front panel is included in the reference design and is based around an inexpensive Futaba VFD and a common NEC front panel controller chip, (uPD16311). The STi5508 controls the uPD16311 using several control signals, (clock, data, chip select). The infra-red remote control signal is passed directly to the STi5508 for decoding. A more advanced front panel is possible with the addition of a front panel microcontroller. A Microchip PIC can be used to control the 16311, receive the infra-red remote control decoding, and system power down. Communication between the STi5508 and the front panel PIC is accomplished over an I�C interface. The front panel connector also supports two microphone inputs and a stereo headphone output. 2.5 REAR PANEL A typical rear panel is included in the reference design. This rear panel supports: - Six channel and two channel simultaneous audio outputs - Optical and coax S/PDIF outputs are supported - Composite, S-Video, and RBG/YUV outputs - Dual SCART provides SCART passthrough when DVD output is not supplied - External video DENC Connections The six video signals used to provide CVBS, S-Video, and RGB/YUV are generated by the STi5508s internal video DAC. The video signals are be buffered by external circuitry. The STi5508 can generate either RGB or YUV outputs on three of the pins by configuring internal STi5508 registers. Six channel audio output by the STi5508 in the form of three I�S (or similar) data streams. An addition, an I�S stream is generated by the STi5508 to support simultaneous two-channel output. The S/PDIF serial stream is also generated by the STi5508 output by the rear panel. A six-channel audio DAC, a stereo DAC, or both can be installed. 3 GPIO, IRQ, AND CHIP SELECT ASSIGNMENTS
PIO Port Bit Port 0 Bit 0 Port 0 Bit 1 Port 0 Bit 2 Port 0 Bit 3 Port 0 Bit 4 Port 0 Bit 5 Port 0 Bit 6 Port 0 Bit 7 Port 1 Bit 0 Port 1 Bit 1 Port 1 Bit 2 Port 1 Bit 3 Port 1 Bit 4 Port 1 Bit 5 Port 1 Bit 6 Port 1 Bit 7 Port 2 Bit 0 Port 2 Bit 1 Port 2 Bit 2 Port 2 Bit 3 Port 2 Bit 4 Port 2 Bit 5 Port 2 Bit 6 Pin # 186 187 188 189 190 191 192 193 194 195 196 197 200 201 202 203 204 205 206 207 208 1 2 STi5508 Alternate Function SC0_DATA #ATAPI_RD #ATAPI_WR SC0_CLK SC0_RST SC0_CMD_VCC SC0_DATA_DIR SC0_DETECT SSC0_DATA SSC0_CLK PARA_DVALID/SC_EXT_CLK TXD2 RXD2 PARA_SYNC/TXD1 TRIGIN TRIGOUT SC1_DATA PARA_REQ/RXD1 PARA_STR SC1_CLK SC1_RST SC1_CMD_VCC DAC_DATA/SC1_DATA_DIR CineMaster CE Function #SOFT_RESET #ATAPI_RD #ATAPI_WR DAC_CCLK (Audio DAC control) DAC_CCLK (Audio DAC control) #DAC_CS0 (Audio DAC control) #DAC_CS1 (Audio DAC control) Unused (Test Point 39) SDA (I2C) SCL (I2C) Unused (Test Point 35) TXD (Serial Port) RXD (Serial Port) SR0 (for PLL1700) TRIGIN (JTAG) TRIGOUT (JTAG) FPCLK (Front Panel) FS0 (for PLL1700) FS1 (for PLL1700) RTS (Serial Port) CTS (Serial Port) FPDATA (Front Panel) DAC_DATA (Stereo Aud�o)

Port 2 Bit 7

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SC1_DETECT

FPSTRB (Front Panel)

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Port 3 Bit 0 Port 3 Bit 1 Port 3 Bit 2 Port 3 Bit 3 Port 3 Bit 4 Port 3 Bit 5 Port 3 Bit 6 Port 3 Bit 7 Port 4 Bit 0 Port 4 Bit 1 Port 4 Bit 2 Port 4 Bit 3 Port 4 Bit 4 Port 4 Bit 5 Port 4 Bit 6 Port 4 Bit 7

6 7 8 9 10 11 12 13 39 40 41 42 43 44 45 46

PARA_DATA0 PARA_DATA1 PARA_DATA2 PARA_DATA3 PARA_DATA4 PARA_DATA5 PARA_DATA6/COMP1 PARA_DATA7/COMP2 YUV0 YUV1 YUV2 YUV3 YUV4 YUV5 YUV6 YUV7

OPEN (TMM Tray Control) CLOSE (TMM Tray Control) Unused (Test Point 36) Front Panel IR Unused (Test Point 37) Unused (Test Point 38) #SENSE (TMM Tray Control) #PUSH (TMM Tray Control) YUV0 (External Video DENC) YUV1 YUV2 YUV3 YUV4 YUV5 YUV6 YUV7

* Front Panel uses the 16311 controller. In the CineMaster design, FPDIN and FPDOUT are connected together as FPDATA. Pin Name #CE1 #CE2 #CE3 #IRQ0 #IRQ1 #IRQ2 Pin # 134 133 132 127 126 125 STi5508 Pin Function Programmable Chip Enable 1 Programmable Chip Enable 2 Programmable Chip Enable 3 Interrupt 1 Interrupt 2 Interrupt 3 CineMaster CE Function ATAPI Buffer Chip Enable Unused FLASH Memory Chip Select Front Panel Interrupt Front End Interrupt (ATAPI/TMM) Unused

Table 1 GPIO, IRQ, and Chip Select Assignments 4. JUMPER CONFIGURATION Jumper JP1 Function Power Down Boot From Link Installed +3.3V, +5V and +12V are disconnected from the STi5508 and associated circuitry using a FET switch forces STi5508 to boot from JTAG interface only Not Installed Uninstalled all components are powered Not Installed STi5508 will attempt to boot from FLASH, but will also boot from JTAG interface

JP3

* Note: There is no JP2

Table 2 Jumper Configuration

5. AUDIO OUTPUT The STi5508 supports both a six channel analog output and a stereo output configuration. Both of these output configurations are available simultaneously (eight analog outputs total). In a system configuration with six analog outputs, the front left and right channels can be configured to provide the stereo outputs, Dolby Surround, and SRS TruSurround, or the left and right front channels for a 5.1 channel surround system. The STi5508 also provides a stereo output channel that can be used in combination with the 5.1 outputs. An example of this configuration is a DVD player with these stereo outputs connected to the TV and the six channel outputs connected to the surround sound amplifier unit. In this setup, the consumer can use the TV speakers or the surround speaker without changing any wires. The stereo output can be configured separately from the six-channel left and right outputs, so, for example, the stereo output can be configured for Dolby ProLogic. The Sti5508 also provides digital output in S/PDIF format. The evaluation board supports both optical and coaxial S/PDIF outputs. 5.1 AUDIO DACs The STi5508 supports several variations of an I�S type bus, varying the order of the data bits (leading or no leading zero bit, left or right alignment within frame, and MSB or LSB first) is possible using the Sti5508 internal configuration registers. The I�S format uses four stereo data lines and three clock lines. The I�S data and clock lines can be connected directly to one or more audio DAC to generate analog audio output.
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The evaluation board uses a six-channel DAC and also a two-channel DAC. The six-channel DAC is connected to the three STI5508 data signals for six-channel output and the two-channel DAC is connected to the STi5508 optional stereo output. The board can be configured with either the six- or two-channel DAC, or both. When the two-channel DAC is not used, the left and right front audio can be connected to the stereo audio output connectors by installing zero ohm resistors R364 and R365. The six-channel DAC is an AKM AK4356. The two-channel DAC is an AK4394 also made by AKM. Both of these DACs support up to 192Khz sampling rate. A less expensive 96kHz two-channel DAC with the same pin-out can be placed instead of the AK4394. Four STi5508 PIO pins are used to configure the audio DACs. The outputs of the DACs are differential, not single ended so a slightly more expensive buffering circuit is required. The buffer circuits use NJR NJM5532 opamps to perform the low-pass filtering and the buffering. 5.2 AUDIO MUTE The audio DACs contain an internal mute circuit and can be enabled by the STi5508 PIO pins. The evaluation board may output a small pop when the system is powered on and off, but no audible pops should be heard during operation or when entering or leaving standby mode. 6. VIDEO INTERFACE The STi5508 integrates a PAL/NTSC encoder. It converts the digital MPEG/Sub Picture/OSD stream into a standard analog baseband PAL/NTSC signals. Six analog video outputs provide CVBS, S-Video (Y/C), and RGB/YUV formats. The three RGB signals can be configured via an internal STi5508 register setting to output either RGB or YUV video signals. The encoder handles interlaced and non-interlaced mode. It can perform Closed Captions, CGMS or Teletext encoding and allows Macrovision 7.01/6.1 copy protection. The encoder supports both master and slave modes for synchronization. The six video signals are routed to the back panel where they are low-pass filtered and buffered. The six active video buffer circuits on the decoder board are identical and use a video speed MAX4018 opamp made by Maxim. The buffered CVBS video is available on a RCA (cinch) style jack, S-Video on a mini-DIN, RGB/YUV on a triple RCA jack, and all six signals (and stereo audio) are available on a SCART connector. Note:The STi5508 is not capable of placing the video synch information in the green signal as required by some RGB monitors. The synch information must be obtained from the CVBS output and connected to the external sync input of an RGB monitor. Note:When the STi5508 is configured to output YUV signals, the RGB pins of the SCART connector will also output YUV. 6.1 SCART INTERFACE The Ravisent evaluation board contains a SCART controller chip from ST Microelectronics, the STv6412. This controller chip allows SCART daisy-chaining the SCART output from another device can be connected to the DVD player SCART input and passed through when the DVD player is in standby. All SCART functions are controlled by the 6412 chip, which is in turn controlled by the STi5508 over the I�C bus. Please see the STv6412 AUDIO/VIDEO SWITCH MATRIX data sheet for more detailed information. 6.2 DIGITAL VIDEO INTERFACE An external video DENC can be connected to the STi5508. The digital output and analog input headers are provided on the board, J20 and J19 respectively. The video encoder is controlled via I2C through the header. Also supplied on the header are +3.3V, +5V, ground, and +5V and 5V analog supplies. The output of the external DENC is then fed into the video filter-buffers on board. The values of the discrete components in the filter-buffers should be changed to match the characteristics of the external DENC. 7. MPEG DECODER SDRAM MEMORY The STi5508 includes glueless interfaces to SDRAM memory for the MPEG decoder. The STi5508 supports one or two 1Mx16bit chips or a 4Mx16bit SDRAM chip. However, the Ravisent evaluation board supports only a 64Mbit chip. The device used is a 4M x 16 bit, 125MHz, 3.3V, 54 pin TSOP II, Micron Technology MCT48LC4M16A2TG-7 or equivalent. 8. PROCESSOR SDRAM MEMORY The STi5508 supports DRAM or SDRAM on its processor bus without any glue logic required. The Ravisent evaluation board supports only SDRAM - either a 1Mx16bit or a 4Mx16bit SDRAM. The STi5508 processor can be configured to share the decoder memory. This will reduce performance slightly, but will reduce the cost of the system, as processor SDRAM is no longer required. It is expected that a typical DVD player will not need any processor SDRAM and this chips will only be installed for test and debug purposes. Dual PCB footprints were used to accommodate the differences in packaging between 16M and 64M SDRAMS. U5/1 is the 16Mbit footprint and U5/2 is the 64Mbit footprint. The same 64Mbit SDRAM used for decoder memory can be used for processor SDRAM.

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9. FLASH MEMORY The decoder board supports a single 1Mx16bit FLASH memory device. The device is a 1M x 16, 90ns, bottom boot block, 3.3V, 48 pin TSOP II, SGS Thomson M29F160BB-90N1 or equivalent. Both 3.3V and 5V FLASH devices can be installed. Our current FLASH loading software supports several FLASH chips from different manufacturers. To support new chips, the programming algorithm will have to be adapted, but this is a rather simple adaptation. Note: Intel and Micron FLASH require that pins 13 and 14 are tied to the positive power supply to allow programming in circuit. To support these device families, install zero ohm (0R0) resistors in locations R79 and R80. Note: Install a zero ohm resistor in location R350 to support +5V FLASH. Install zero ohms in R352 to support +3.3V FLASH. Never install both R350 and R352 at the same time as this will short the 3.3 and 5V supplies together. The default is +3.3V. Note: Some FLASH devices use pin 15 for address pin A19, while most others use pin 9. To support a chip that uses pin 15, install R81. 10. SERIAL EEPROM MEMORY An I�C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup, etc.) and software configuration information (i.e. remote control type). Industry standard EEPROM range in size from 1kbit to 256kbit and share the same IC footprint and pinout. The default device is 2kbit, 256k x 8, SOIC8 SGS Thomson ST24C02M1 or equivalent. See the section on Reset Circuitry for a less costly EEPROM solution. 11. TMM DRIVE INTERFACE The STi5508 will directly supports a Thomson TVM502 drive (or a similar drive built around the ST chip drive set) without any external glue logic. The newer TVM drives include the disc tray motor control circuitry, but the older drives do not. Tray motor control circuitry is included on the evaluation board to support these older drives. 11.1 CONNECTION INFORMATION The newer TMM drive uses a 19 pin FFC connector while the older drives use two PicoFlex ribbon connectors and a two pin tray motor connector. Both connector systems are supported on the evaluation board. The drive interface, with the exception of the tray motor circuitry, is contained entirely in the STi5508. The older TMM drive connects to the evaluation board in three places: J5 Drive tray motor terminals J6 Power cable connector J7 Data cable connector The newer TMM drive connects to the evaluation board with a single connector: J8 FFC19 connector The connectors selected by Thomson for the data and power cables are in the PicoFlex product line manufactured by Molex and Lumberg. The FFC connector is available from many suppliers including Molex. See Bill of Material for part numbers. 11.2 TMM DRIVE TRAY MOTOR CONTROL AND PUSH AND STALL SENSE CIRCUITRY There is circuitry on the decoder board to power the TMM drive tray and to monitor its activity. When the tray is being opened or closed and the tray has reached the end of its travel or is being jammed, the motor will stall and draw a high current. Circuitry monitors the level of current used by the motor and will toggle a PIO pin of the STi5508 when the motor has stalled, (schematic net name: #SENSE). The STi5508 will then remove power to the motor. Also, if the tray is open and the user pushes the tray to close it, the motor will generate voltage. Circuitry will sense this voltage and toggle another PIO pin, (schematic net name: #PUSH). The STi5508 will then close the tray. The sensitivity of the push sense can be adjusted by changing the value of R114 in relation to R117. When the tray is motionless, the voltage across the motor is zero. When the tray is pushed the voltages at either side of the motor begin to diverge. These two voltages are fed into a comparator to create the trigger signal. This is an improved circuit from the Ravisent STi5505 evaluation boards and this new circuit is not sensitive to temperature or component tolerances. Note: To disable the push sense circuit, remove R109 and R112. R106 and R107 should already be installed. 12. ATAPI DRIVE INTERFACE AND EPLD The STi5508 includes a glueless ATAPI interface on-chip. While this interface limits performance of the system, it is a lower cost solution than providing external logic to interface the drive to the STi5508 front-end interface. Standard ATAPI DVD drives are supported through the ATAPI EPLD interface. The drive connects to the decoder board through a standard 40 pin header, The header is a 2 row by x 20 pins, 0.1 pin spacing, and has 0.025 square pins. Note: The decoder board supports the standard ATAPI electrical connections, but the software protocol within the drive is not always supported according to ATAPI specifications. Custom software may need to be developed and tested to support ATAPI drives from different manufacturers.
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13 AUDIO SAMPLING RATE AND EXTERNAL PLL COMPONENT CONFIGURATION The decoder board has optional PLLs, which can be installed to provide the audio clock for the system. The initial version of the STi5505 was not able to provide an audio clock for 96kHz support and an external PLL was used to support this. This was fixed in the STi5505 later chip revisions and therefore no problems are expected in the STi5508. However, in case a problem arises, the PLL circuit can be installed to provide a high quality clock particularly important in S/PDIF applications. In the default configuration, a small buffer chip is installed to buffer the audio clock between the STi5508 and the audio DACs. 14 UART SERIAL PORT The evaluation board provides an RS232 connection to the STi5508. A standard DB9 connector ribbon cable can be connected to the 10 pin header provided, (J9). The RS232 buffer can also be bypassed and the 3.3V signals can be accessed on the header. ASC2 is the serial port used to this connection. 15. FRONT PANEL 15.1 FRONT PANEL MICRO A Microchip PIC can be installed in the system to control the front panel VFD, perform IR remote control decoding and power down functions, and read the position on two POTs with its internal ADC. When the front panel micro is installed, the entire decoder board circuit can be powered down in standby mode because the PIC will decode the IR signals. 15.2 VFD CONTROLLER The VFD controller is a NEC uPD16311. This controller is not a processor, but does include a simple state machine which scans the VFD and reads the front panel button matrix. The 16311 also includes RAM so it can store the current state of all the VFD icons and segments. Therefore, the 16311 need only be accessed when the VFD status changes and when the button status is read. The STI5508 can control this chip directly using PIO pins or can allow the front panel PIC to control the VFD. 15.3 MICROPHONE INPUTS The board has two � phono-jacks for microphone input. The microphone circuits consist of microphone pre-amps, a signal buffers, and a stereo ADC. The microphone pre-amp, SSM2165, conditions the signal for better performance. The stereo ADC is a Crystal CS5331 and connects directly to the STi5508 digital audio input via I�S. Adjusting the value POT1 and POT2 can vary the compression characteristics of the microphone signal. See the SSM2165 data sheet for a graph of the compression characteristics and POT settings. When the correct POT setting is found, the pots can be replaced with fixed resistors, R382 and R383. 15.4 HEADPHONE OUTPUTS The left and right audio is amplified and output through a stereo � phono-jack. The audio is from the two-channel output, not the let and right channel of the six-channel, (the left and right six-channel audio can be connected to the left and right two-channel output when the stereo DAC is not installed). A dual logarithmic POT is used to adjust the volume of the audio before amplification, POT5. The connections for left and right channels at the headphone jack can be swapped by changing the resistor stuffing options, R376-379 . 16 MISCELLANEOUS FUNCTIONS 16.1 POWER DOWN Two dual FET ICs can be installed on the decoder board to enable a power down feature. Power down is activated by connecting a switch across JP1, shorting the two pins together pulling pin 2 to +5V. The front panel microcontroller can also control the power down status by driving FPPWD high. When in power down state, power can be removed from all of the circuitry except the front panel micro, which must remain power to decode remote control signaling and scanning the front panel buttons. If the front panel micro is not used, then the STi5508 cannot be powered down. The board can be configured in several ways to accomplish a power down goal. The net VCC_PIC is always powered. VCC can either be switched (by installing R3) or always powered (by installing R1). VCC3 can either be switched (by installing R5)or always powered (by installing R2). VCC-S, VCC3-S, +12V-S, and +8V-S are switched. There are four LEDs used to indicate power state and they can be connected on either side of the FET switch. The dual FET is a Fairchild NDS8934 and is located at Q1 and Q2. Note: If the power down feature is enabled FPPWD must be driven by the front panel micro or some other source. 16.2 RESET CIRCUITRY Three different chips are supported to provide the power-on-reset and pushbutton reset function: Analog Device ADM707 (or equivalent), Telcom Semiconductor TC1270, or Xicor X1242. The TC1270 is a lower cost alternative to the ADM707. The Xicor device also includes 2kbits of Serial EEPROM storage and can be used to replace both the reset and SEEPROM devices to reduce cost. All three devices support and pushbutton reset switch.

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16.3 VOLTAGE REGULATORS There are two +5V linear regulators to generate +5V for the analog circuitry from +12V. A smaller DPAK surface mount device can be used in most circumstances, but in applications were more than 150mA are required, a TO-220 throughhole package can be used. The STi5508 requires 2.5V to operate. This voltage is generated from +5V. Negative 5V is required by the audio buffer circuitry and this is generated in one of three ways. If 12V is supplied by the power supply, it is regulated to 5V with a linear regulator. If no 12V is supplied, a DC-DC can be installed in U51 to generate either 12V or 5V. The use of a switching regulator to generate the negative voltage may introduce noise into that voltage, so better audio performance may be produced by generating 12V with the DC-DC converter and then regulating this to 5V with a linear regulator. 17 CONNECTORS 17.1 ATAPI DRIVE STANDARD CONNECTOR Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 ATAPI Drive Interface J23 Description Pin #RESET 2 DATA7 4 DATA6 6 DATA5 8 DATA4 10 DATA3 12 DATA2 14 DATA1 16 DATA0 18 GND 20 DMARQ 22 #IOW 24 #IOR 26 IOCHRDY 28 #DMACK 30 INTRQ 32 ADDR1 34 ADDR0 36 #CS0 38 40 Table 3 ATAPI Drive Interface J23 TMM Tray Connector J5 Pin Description 1 +12V 2 GND 3 GND 4 +5V Table 4 ATAPI Power Connector J4 TMM Tray Connector J5 Pin Description 1 OPEN 2 CLOSE Table 5 TMM Tray Connector J5 TMM Power Connector J6 Pin Description 1 +5V (filtered) 2 +5V 3 GND 4 GND (filtered) 5 GND 6 +8V 7 GND 8 +12V 9 GND 10 +3.3V Table 6 TMM Power Connector J6
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Description GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 GND GND GND GND GND HIO16 #PDIAG ADDR2 #CS1 GND

17.2 TMM DRIVE CONNECTORS

TMM Data Connector J7 Pin Description 2 GND 3 SYNC 4 FLAG 5 DATA 6 BCLK 7 GND 8 #FE RESET 9 FE I NT 10 SCL 11 SDA 12 GND Table 7 TMM Data Connector J7 Pin 1 2 3 4 5 6 7 8 9 10 Description GND SYNC FLAG DATA BCLK GND #FRESET FEINT SCL TMM FFC19 Connector J8 Pin 11 12 13 14 15 16 17 18 19 Description SDA GND GND +3.3V +5V GND GND (filtered) +12V +8V or +12V

Table 8 TMM FFC19 Connector J8 17.3 STI5508 JTAG INTERFACE Pin 1 3 5 7 9 11 13 15 17 19 JTAG Programming Interface J2 Description Pin Description 2 GND PIO3_7 4 GND PIO3_6 6 GND 8 GND TMS 10 GND TCK 12 GND TDI 14 GND TDO 16 GND #JTAG_RESET 18 GND #TRST 20 GND Table 9 JTAG Programming Interface J2 17.4 RS232 SERIAL PORT Pin 1 3 5 7 9 RS232 Serial Port Header J9 Description Pin 2 TXD 4 RXD 6 8 GND 10 Table 10 RS232 Serial Port Header J9 Description CTS RTS -

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17.5 DIGITAL YUV OUTPUT HEADER Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 Digital YUV Output Header J20 Description Pin YUV0 2 YUV1 4 YUV2 6 YUV3 8 YUV4 10 YUV5 12 YUV6 14 YUV7 16 PIXCLK 18 20 SCL 22 SDA 24 GND 26 Table 11 Digital YUV Output Header J20 17.6 ANALOG VIDEO INPUT HEADER Pin 1 3 5 7 9 11 17.7 SCART CONNECTORS Pin 1 3 5 7 9 11 13 15 17 19 21 17.8 POWER CONNECTOR Pin 1 2 3 4 5 6 71 81
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Description GND GND GND VSYNC HSYNC GND GND GND +5V or +3.3V +5V (analog) -5V (analog)

Analog Video Input Header J19 Description Pin Description RED 2 GND GREEN 4 GND BLUE 6 GND CHROMA 8 GND LUMA 10 GND CVBS 12 GND Table 12 Analog Video Input Header J19 SCART Connectors J10 Description Pin RIGHT AUDIO OUT 2 LEFT AUDIO OUT 4 GND 6 BLUE 8 GND 10 GREEN 12 GND 14 RED (CHROMA) 16 GND 18 CVBS OUT (LUMA) 20 GND (shield) Table 13 SCART Connectors J10 Power Connector J1 Description +5 V +3.3 V +3.3 V GND GND +12 V GND -12 V

Description RIGHT AUDIO IN GND LEFT AUDIO IN SWITCH GND BLANK GND CVBS IN

Table 14 Power Connector J1 Connection to these two terminals is not required unless the board uses 12V. In a system without 12V, a six pin header can be installed into pins one (1) through six (6) leaving pins seven (7) and eight (8) unpopulated. 18 SCHEMATICS 19 BILL OF MATERIALS 20 BOARD LAYOUT 20.1 TOP SIDE ASSEMBLY DRAWING 20.2 BOTTOM SIDE ASSEMBLY DRAWING
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