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Slide Module
receiver
Key
Pad Cristal
Camera 32.768
Module KHz
26MHz
MT6129
(RF Transceiver)
External
Memory
Nand Flash Camera 32.768Khz VAPC
Interface Interface OSC
Interface AMPS/GSM
VAFC
GSM TX
SYSCLK
TX I/Q
TX DCS/PCS (PAM) DCS TX
RX I/Q
RX GSM RX
(Baseband Processor) VAPC
DCS RX
B2PSI
PCS RX ESHS-
AuxADC M090SF
Supply Voltages
LB_TX
(GSM TX
HeadSet HB_TX Enable)
Main Mic (DCS/PCS
Mic
HeadSet USB UART TX Enable)
KEYPAD
Receiver
(Power Management IC)
Bottom SIM
Connector
Charger
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Baseband section
This document provides a description of the baseband section of the ESL808. Most design decisions
are explained, but no detailed calculations are included. Total chip solutions(MT6219, MT6305,
MT6129) except for RF Power Amplifier(RF3146) are from Media Tek, Taiwan.
I. MT6219 ( GSM/GPRS Baseband Processor )
Figure 1. Block Diagram of MT6219
Figure 1 details the block diagram of MT6219. Based on dual-processor architecture, the major
processor of MT6219 is ARM7EJ-S, which mainly runs high-level GSM/GPRS protocol software as
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well as multi-media applications. With the other one is a digital signal processor corresponding for
handling the low-level MODEM as well as advanced audio functions. Except for some mixed-signal
circuitries, the other building blocks in MT6219 are connected to either the microcontroller or the
digital signal processor.
Figure 2. Typical Application of MT6219
1. Micro-Controller Unit Subsystem
ARM7EJ-S, plays the role of the major bus master controlling the whole subsystem. Essentially, it
communicates with all the other on-chip modules by way of system buses : AHB Bus and APB Bus.
All bus transactions originate from bus masters, while slaves can only respond requests from bus
masters. Prior to a data transfer can be established, bus master must ask for bus ownership. This is
accomplished by request-grant handshaking protocol between masters and arbiters.
Two levels of bus hierarchy are designed to provide alternatives for different performance
requirements, i.e. AHB Bus and APB Bus for system back bone and peripheral buses, respectively. To
have high performance and proper efficiency, the AHB Bus provides 32-bit data path with multiplex
scheme for bus interconnections.
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Only memory addressing method is used in MT6219 based system. All components are mapped onto
MCU 32-bit address space. A Memory Management Unit is employed to have a central decode scheme.
It generates certain selection signals for each memory-addressed modules on AHB Bus.
In order to off-load the processor core, a DMA Controller is designated to act as a master and share the
bus resources on AHB Bus to do fast data movement between modules. This controller comprises
thirteen DMA channels.
A 512KByte SRAM is provided for acting as system memory for high-speed data access. For factory
programming purpose, a Boot ROM module is used. These two modules use the same Internal
Memory Controller to connect to AHB Bus.
External Memory Interface supports both 8-bit and 16-bit devices. Since AHB Bus is 32-bit wide, all
the data transfer will be converted into several 8-bit or 16-bit cycles depending on the data width of
target device. This interface is specific to both synchronous and asynchronous components, like Flash,
SRAM and parallel LCD. This interface supports also page and burst mode type of Flash.
1.1 Processor Core
The Micro-Controller Unit Subsystem in MT6219 is built up with a 32-bit RISC core, ARM7EJ-S.
The memory interface of ARM7EJ-S is totally compliant to AMBA based bus system. Basically, it can
be connected to AHB Bus directly.
1.2 Memory Management
The processor core of MT6219 supports only memory addressing method for instruction fetch and data
access. It manages a 32-bit address space that has addressing capability up to 4GB. System RAM,
System ROM, Registers, MCU Peripherals and external components are all mapped onto such 32-bit
address space.
1.3 Bus System
Two levels of bus hierarchy are employed in constructing the Micro-Controller Unit Subsystem of
MT6219. AHB Bus and APB Bus serve for system backbone and peripheral buses, while an APB
bridge connects these two buses. Both AHB and APB Buses operate at the same clock rate as
processor core.
1.4 Direct Memory Access
A generic DMA Controller is placed on Layer2 AHB Bus to support fast data transfers, and also to
off-load the processor. With this controller, specific devices on AHB or APB buses can benefit greatly
from quickly completing data movement from or to memory module, i.e. Internal System RAM or
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External SRAM. Such Generic DMA Controller can also be used to connect any two devices other
than memory module as long as they can be addressed in memory space.
1.5 Interrupt Controller
Figure 2 outlines the major functionality of the MCU Interrupt Controller. The interrupt controller
processes all interrupt sources coming from external lines and internal MCU peripherals. Since
ARM7EJ-S core supports two levels of interrupt latency, this controller will generate two request
signals : FIQ for fast, low latency interrupt request and IRQ for more general interrupts with lower
priority.
One and only one of the interrupt sources can be assigned to FIQ Controller and have the highest
priority in requesting timing critical service. All the others should share the same IRQ signal by
connecting them to IRQ Controller. The IRQ Controller manages up 32 interrupt lines of IRQ0 to
IRQ31 with fixed priority in descending order.
Figure 3. Block Diagram of the Interrupt Controller
1.6 Internal Memory Controller
System RAM
MT6219 provides four 64KByte size of on-chip memory modules acting as System RAM for data
access with zero latency. Such module is composed of four high speed synchronous SRAMs with
AHB Slave Interface connected to system backbone AHB Bus. The synchronous SRAM operates at
the same clock as AHB Bus and is organized as 32-bit wide with 4 byte-write signals capable for byte
operations.
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System ROM
The System ROM is primarily used to store software program for Factory Programming. However,
due to it's advantageous zero latency performance, some of timing critical codes are also placed in this
area. This module is composed of high-speed diffusion ROM with AHB Slave Interface connected to
system backbone AHB Bus.
1.7 External Memory Interface
MT6219 incorporates a powerful and flexible memory controller, External Memory Interface, to
connect with a variety of memory components. This controller provides generic access schemes to
asynchronous/synchronous type of memory devices, such as Flash Memory and SRAM. It can
simultaneously support up to 8 memory banks with max size of 64MB each.
Refer to Figure 2. Typical Application of MT6219.
2. Microcontroller Peripherals
MCU Peripherals are devices that are under control of the Microcontroller. Most of them are attached
to the APB of the MCU subsystem, thus shall serve as APB slaves. Each MCU peripheral has to be
accessed as a memory-mapped I/O device, i.e., the MCU or the DMA bus master read or write specific
peripheral by issuing memory-addressed transactions. Refer to Figure2. Typical Application of
MT6219.
2.1 Pulse-Width Modulation Outputs
Two generic pulse-width modulators are implemented to generate pulse sequences with programmable
frequency and duty cycle for LCD backlight. The duration of the PWM output signal is Low as long as
the internal counter value is greater than or equals to the threshold value and the waveform is shown in
Figure3.
Figure 4. PWM waveform
PWM1 and PWM2 are devoted to LCM Backlight dimming function and enabling camera flash.
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2.2 Alerter
The output of Alerter has two sources : one is the enhanced pwm output signal, which is implemented
embedded in Alerter module; the other is PDM signal from DSP domain directly. The enhanced pwm
with three operation modes is implemented to generate a signal with programmable frequency and tone
volume. However the output of Alerter in ESL808 is dedicated to the enabling signal of vibrator.
2.3 SIM Interface
The MT6219 contains a dedicated smart card interface to allow the MCU access to the SIM card. It
can operate via 5 terminals, using SIMVCC, SIMSEL, SIMRST, SIMCLK and SIMDATA.
Figure 5. SIM Interface Block Diagram
The SIMVCC is used to control the external voltage supply to the SIM card and SIMSEL determines
the regulated smart card supply voltage. SIMRST is used as the SIM card reset signal. Besides,
SIMDATA and SIMCLK are used for data exchange purpose.
2.4 Keypad Scanner
The keypad can be divided into two parts : one is the keypad interface including 7columns and 6
rows ; the other is the key detection block which provides key pressed, key released and de-bounce
mechanism. Each time key pressed or key released, i.e. something different in the 7*6 matrix, the key
detection block will sense it, and it will start to recognize if it's a key pressed or key released event.
Whenever the key status changes and is stable, a KEYPAD IRQ will be issued. The MCU can then
read the key pressed directly in registers. And this keypad can detect one or two key-pressed
simultaneously with any combination.
2.5 General Purpose Inputs/Outputs
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Figure 6. GPIO Block Diagram
MT-6219 offers 48 general-purpose I/O pins and 3 general-purpose output pins. By setting the control
registers, MCU software can control the direction, the output value and read the input values on these
pins. Besides, these GPIOs and GPOs are multiplexed with other functionalities to reduce the pin
count.
2.6 UART
The MT6219 houses three UARTs. The UARTs provide full duplex serial communication channels
between the MT6219 and external devices. However, 1st UART ports (URXD1, UTXD1) are only
available in ESL808.
2.7 Real Time Clock
The Real Time Clock module provides time and data information. It works on the 32.768KHz
oscillator (OSC60) with independent power supply. When the MS is powered off, a dedicated
regulator is used to supply the RTC block. If the main battery is not present, the backup supply such as
a small mercury cell battery or a large capacitor is used. In addition to provide timing data, alarm
interrupt is generated and it can be used to power up the baseband core through the BBWAKEUP pin.
Also, regulator interrupts corresponding to the seconds, minutes, hours and days can be generated
whenever the time counter value reaches a maximum.
2.8 Auxiliary ADC Unit
The auxiliary ADC unit is used to monitor the status of battery and charger, identify the plugged
peripheral, and perform temperature measurement.
ADC0 and ADC1 : current sensing
ADC2 : battery temperature
ADC3 : charging voltage
ADC5 : detecting ear microphone.
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2.9 Irda Framer
Irda Framer functional block can be divided into twp parts : The transmitting part and the receiving
part. In the transmitter, It will perform BOFs addition, byte stuffing, the addition of 16-bits FCS and
EOF appendence. In the receiving part, it will execute BOFs removal, ESC character removal, CRC
checking and EOF detection. In addition, the framer will pwerform 3/16 modulation and
demodulation to connect to the IR transceiver. The transmitter and receiver all need DMA channel.
Figure 7. Irda Framer Functional Block
3. Microcontroller Coprocessors
Microcontroller Coprocessors are designed to run computing-intensive processes in place of MCU.
Those coprocessors intend to offer a solution special for timing critical GSM/GPRS Modem processes
that require fast response and massive data movement. Controls to the coprocessors are all through
memory access by way of APB Bus.
4. Multi-Media Subsystem
MT6219 is specially designed to support multi-media terminals. It integrates several hardware
based accelerators such as advanced LCD display controller, hardware JPEG encoder/decoder,
hardware Image Resizer and MPEG4 video CODEC. In addition, MT6219 also incorporates
NAND Flash, USB 1.1 Device and SD/MMC/MS pro controllers for Mass data transfers and
storages.
4.1 LCD Interface
A specific LCD controller is implemented to allow MCU to access external LCD module by dedicated
Parallel Interface(NLD00:NLD07) and to improve data throughput for color LCD applications. LCM
is 1.8 inch, 260K colors TFT and 176x220 resolutions.
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Figure 8. LCD Interface Block Diagram
4.2 JPEG Decoder
To boost JPEG image processing performance, a hardware block is preferred to aid software and deal
with JPEG file as much as possible. As a result, JPEG Decoder is designed to decode all baseline and
progressive JPEG images with all YUV sampling frequencies combinations.
4.3 JPEG Encoder
The Hardware JPEG Encoder implements the baseline mode of Standard ISO/IEC 10918-1. It
supports YUV422 format for color pictures and greyscale format. For hardware reduction, it uses
stardard DC and AC Juffman tables for both the luminance and chrominance components. To adjust
the picure compression ratio and picture quality, there are 4 levels of quantization that can be
programmed. After initialization by software, the hardware JPEG encoder can generate the entire
compressed file.
4.4 Image Resizer
This Block provides image resizing capability. It receives image data from a block-based image
source such as JPEG decoder in format of YUV color space, or a pixel-based image source such as
camera in format of RGB or YUV and performs image resizing. The first pass is coarse resizing pass
and it can shrink the image by a factor of 1, 1/4, 1/16, 1/64. The second pass is fine resizing pass and it
can shrink and enlarge the image in fractional ratio. Refer to the Figrue9 Image resizer block diagram.
The maximum isze of a pixel based source image is only 2047x2047.
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Figure 9. Image Resizer Block Diagram
4.5 NAND Flash Interface
MT6219 provides 8-bit NAND flash data and 7 interface Signals(NRNB, NCLE, /WP,NALE, /NCE,
/NEW, /NRE). The MCP of ESL808 is 128Mbit(Nor Flash)x32MBit(SRAM)+512Mbit(NAND Flash).
Nand Flash interface bus are assigned to LCM data for speed up and high throughput.
4.6 USB Device Controller
MT6219 provides a USB function interface that is in compliance with Universal Serial Bus
Specification Rev 1.1. The USB device controller supports only full-speed(12Mbps) operation. The
cellular phone can make use of this widely available USB interfaces to transmit/receive data with USB
host, typically PC.
The USB device uses cable-powered feature for the transceiver but only drains little current. An
external resistor(nominally 1.5kohm) is required to be placed across Vusb and DP Signal. Two
additional external serial resistors mignt be needed to be placed on the output of DP and DM signals to
make the output impedance equivalent to 28~44ohm. Also, USB cable can be used to Charger for 5V
input.
4.7 SD Memory Card Controller
The controller fully supports the SD Memory Card bus protocol as defined in SD Memory Card
Specification Part1 Physical Layer Specification version1.0. But ESL808 is not interfaced Mini SD
card but T-Flash Memory Card. Interface Signals are same.
The Detection is controlled by INS pin status. When Card is nothing, The INS is high logically. And
When Card inserted, The INS is low.
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Figure 10. SD Card Interface Pin Map
5. Audio Front-End
The audio front-end essentially comprises voice and audio data paths. The whole voice band data paths
are complied with GSM03.50 specification. Furthermore, Mono hands-free audio or external FM radio
playback path are provided. The stereo audio path facilitates audio quality playback, external FM radio,
and voice playback through headset.
Figure 11. Audio Front-End Block Diagram
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Figure 12 shows the block diagram of digital circuits of the audio front-end. The APB register block is
an APB peripheral to get settings from the MCU. The DSP audio port block interfaces with the DSP
for control and data communications. Besides, there is a Digital Audio Interface(DAI) block to
communicate with the System Simulator for FTA or external Bluetooth module for particular
applications. The digital filter block performs filter operations for voice band and audio band signal
processing.
Figure 12. The block diagram of the digital circuits for Audio Front-End
Stereo sound are implemented by LM4890 IC(Mono audio amplifier).
ESL808 used 2 in 1 speaker. The AU_Out0_N/_P lines are for Voice Audio. AU_MOUTL was
connected to the Speaker via LM4890 for Ring Tone and Melody(Midi and MP3)
6. Radio Interface Control
This Chapter details the MT6219 Interface control with Radio part of a GSM Terminal. Providing a
Comprehensive control scheme, The MT6219 radio interface consists of Baseband Serial
Interface(BSI), Baseband Parallel Interface(BPI), Automatic Power Control(APC) and Automatic
Frequency Control(AFC) together with APC_DAC and AFC_DAC.
6.1 Baseband Serial Interface
The Baseband Serial Interface is used to control the external radio components. It utilizes a 3-wire
serial bus to transfer data to RF circuitry for PLL frequency change, reception gain setting, and other
radio control purposes. In this unit, BSI data registers are double-buffered in the same way as the
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TDMA event registers. The user writes data into the write buffer and the data is transferred from the
write buffer to the active buffer when TDMA_EVTVAL signal from the TDMA Timer is pulsed.
The Unit supports 2 external components. There are four output pins. BSI_CLK is the output Clock,
BSI_DATA is the serial data port, and BSI_CS0 and BSI_CS1 are the select pins for the 2 components.
BSI_CS1 is multiplexed with other function.
Figure 13. Block diagram of BSI unit.
6.2 Baseband Parallel Interface
The Baseband Parallel Interface features a 10-pin output bus used for timing-critical control of the
external circuits. These pins are typically used to control front-end components at the specified time
along the GSM time-base, such as transmit-enable(PA_EN), band switching(BANDSW_DCS), TR-
switch(LB_TX, HB_TX), etc.
Figure 14. Block diagram of BPI Interface
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6.3 Automatic Power Control (APC) Unit
Automatic Power Control unit is used to control the Power Amplifier module. Through APC unit, we
can set the proper transmit power level of the handset and to ensure that the burst power ramping
requirements are met. In one TDMA frame, up to 7 TDMA events can be enabled to support multi-slot
transmission. In practice, 5 banks of ramp profiles are used in one frame to make up 4 consecutive
transmission slots.
The shape and magnitude of the ramp profiles are configurable to fit ramp-up, intermediate ramp, and
ramp-down profiles. Each bank of the ramp profile consists of 16 8-bit unsigned values, which is
adjustable for different conditions.
The entries from one bank of the ramp profile are partitioned into two parts, with 8 values in each part.
In normal operation, the entries in the left half part are multiplied by a 10-bit left scaling factor, and
the entries in the right half part are multiplied by a 10-bit right scaling factor. Those values are then
truncated to form 16 10-bit intermediate values. Finally the intermediate ramp profile are linearly
interpolated into 32 10-bit values and sequentially used to update to the D/A converter. The block
diagram of the APC unit is shown in Figure 15.
Figure 15. Block diagram of APC unit
The APC Analog Signal is inputted to Power Amplifier Module through Low Pass filter (R842,C841)
6.4 Automatic Frequency Control (AFC) Unit
Automatic Frequency Control unit provides the direct control of the oscillator for frequency offset and
Doppler shift compensation. The Block diagram is depicted in Figure 16. It utilizes a 13-bit D/A
converter to achieve high-resolution control. The AFC is always inputted to VCTCXO to gemerated
13Mhz. The Aanlog voltage is about 1.5V and AFC_DAC is about 4200 decimally.
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Figure 16. Block diagram of the AFC Controller
7. Baseband Front End
Figure 17. Block Diagram of Baseband Front-End
Baseband Front End is a modem interface between Tx/Rx mixed-signal modules and digital signal
processor. We can divide this block into two parts. The first is the uplink(transmitting) path, which
converts bit-stream from DSP into digital in-phase and quadrature signals for TX mixed-signal module.
The second part is the downlink(receiving) path, which receives digital in-phase and quadrature
signals from RX mixed-signal module, performs FIR filtering and then sends results to DSP. The
uplink path is mainly composed of GMSK Modulator and uplink parts of Baseband Serial Ports, and
the downlink path is mainly composed of RX digital FIR filter and downlink parts of Baseband Serial
Ports. Baseband Serial Ports is a serial interface used to communicate with DSP. In addition, there is a
set of control registers in Baseband Front End that is intended for control of Tx/Rx mixed-signal
modules, inclusive of calibration of DC offset and gain mismatch of downlink analog-to-digital
converters as well as uplink.
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7.1 Baseband Serial Ports
Baseband Front End communicates with DSP through the sub block of Baseband Serial Ports.
Baseband Serial Ports interfaces with DSP in serial manner. It implies that DSP must be configured
carefully in order to have Baseband Serial Ports cooperate with DSP core correctly.
7.2 Downlink Path ( RX Path)
On downlink path, the subblock between RX mixed-signal module and Baseband Serial Ports is RX
Path. It mainly consists of a digital FIR filter, two sets of multiplexing paths for loopback modes,
interface for RX mixed-signal module and interface for Baseband Serial Ports.
Figure 18. Block diagram of Downlink Path
7.3 Uplink Path ( TX Path )
The purpose of the uplink path inside Baseband Front End is to sink TX symbols, one bit for each
symbol, from DSP, then perform GMSK modulation on them, then perform offset cancellation on I/Q
digital signals out of GMSK modulator, and finally control TX mixed-signal module to make D/A
conversion on I/Q signals out of GMSK Modulator with offset cancellation. Accordingly, the uplink
path is composed of uplink parts of Baseband Serial Ports, GSM Encryptor, GMSK Modulator and
Offset Cancellation.
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Figure 19. Block Diagram of Uplink Path
8. Timing Generator
Timing is the most critical issue in GSM/GPRS applications. The TDMA timer provides a simple
interface for the MCU to program all the timing-related events for receive event control, transmit event
control and the timing adjustment.
In pause mode, the 13MHz reference clock may be switched off temporarily for the purpose of power
saving and the synchronization to the base-station is maintained by using a low power 32.768KHz
crystal oscillator. The 32.768KHz oscillator is not accurate and therefore it should be calibrated prior
to entering pause mode.
Figure 20. The Block Diagram of TDMA Timer.
Figure 21. The Block Diagram of Slow Clocking unit.
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9. Power, Clocks and Reset
9
9
9
9
Figure 22. Major Phone Power States and Operation Modes for MT6219 based terminal
This Chapter descripbes about the power,clock and reset management functions provided by MT6219.
Together with Power Management IC, MT6219 offers both fine and coarse resolutions of power
control by way of software programming. With this efficient method, the developer can turn on
selective resources accordingly in order to achieve optimized power consumption. The Operating
modes of MT6219 as well as main power states provided by the PMIC are shown in Figure 22.
9.1 Baseband to PMIC Serial Interface
MT6219 use 3 wires B2PSI interface connected to PMIC, this bi-directional serial bus interface allows
baseband to write command to and read from PMIC. The bus protocol utilizes a 16bits proprietary
format. B2PSICK is the serial bus clock and is driven by the master. B2PSIDAT is the serial data;
master or slave can drive it. B2PSICS is the bus selection signal. Once the B2PSICS goes low,
Baseband starts to transfer the 4 register bits followed by a read/write bit, then wait for 3 clocks for
PMIN B2PSI state machine to decode the Operation for the next succeeding 8 data bits. The State
machine should count for 16 clocks to complete the data transfer.
9.2 Clocks
There are two major time bases in the MT6219. For the faster one is the 13MHz clock origination from
an off-chip temperature-compensated voltage controlled oscillator that can be 26MHz. This signal is
the input from the SYSCLK pad then is converted to the square-wave signal. The other time base is the
32.768KHz clock generated by an on-chip oscillator connected to an external crystal.
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Figure 23. Clock distributions in the MT6219
9.2.1 32.768Khz Time Base
The 32.768Khz clock is always running. It's mainly used as the time base of the Real Time
Clock(RTC) module, which maintains time and date with counters. In low power mode, the
13Mhz time base is turned off, so the 32.768Khz clock shall be employed to update the critical
TDMA timer and Watchdog timer. This Time base is also used to clock the keypad Scanner
logic. The C161,C162 must be tuned with Oscillator.
9.2.2 13Mhz Time Base
Two 1/2-dividers, one for MCU Clock and the other for DSP Clock, exist to allow usage of
eigher 26 or 13Mhz TXVCXO as clock input. There phase-locked loops(MPLL, DPLL and
UPLL) are used to generate three primary clocks.
MPLL : Provides the MCU System Clock.
DPLL : Provides the DSP System Clock. DPLL can be programmed to provide 1x to 6x
output of the 13Mhz reference.
UPLL : Provides the USB System Clock.
9.3 Reset Management
Figure 17 shows reset scheme used in MT6219. There are three kinds of resets in the MT6219, i.e.,
hardware reset, watchdog reset, and software resets.
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Figure 24. Reset Scheme used in MT6219
9.3.1 Hardware Reset
This Reset is inputted through the SYSRST# pin frim PMIC(MT6305 Pin 24). The SYSRST# shall be
driven to low during power-on. The Hardware reset has a grlbal effect on the chip. It initializes all
digital and analog circuits except the RTC. Refer to the listed below.
- All Anlog Circuits are turned off
- All PLLs are turned off and bypassed. The 13Mhz system clock is the default time base.
- Special Trap statue in GPIO.
9.3.2 Watchdog Reset
A Watchdog reset is generated when the Watchdog timer expires as the MCU software failed to re-
program the timer counter in time. Hardware blocks that are affected by the watchdog reset are :
- MCU Subsystem
- DSP Subsystem
- External Component (By software program)
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9.3.3 Software Reset
These are local reset signals that initialize specific hardware. For example, The MCU or DSP software
may write to software reset trigger registers to reset hardware modules to their initial states, when
hardware failures are detected. The following Modules hae software resets
- DSP Core
- DSP Coprocessors.
II. MT6305 ( GSM Power Management System)
The MT6305 is a power management system chip optimized for GSM handsets, especially those based
on the MTK system solution. It contains seven LDOs, one to power each of the critical GSM sub-
blocks. Sophisticated controls are available for power-up during battery charging, keypad interface,
and RTC alarm. The interface Features are listed below.
- Handles all GSM baseband Power management
- 2.8V to 5.5V input range
- Charger input up to 15V
- Seven LDOs Optimized for specific GSM Subsystems
- High Operation Efficiency and Low Stand-by Current
- Li-Ion and NiMH battery Charge function
- SIM Card interface
- Three Open-Drain Output Switches to Control the LED, Alerter and vibrator
- Thermal Overload Protection
- Under Voltage Lock-Out Protecton
- Over Voltage Protecton
- Power on Reset And start up Timer
1. Low Dropout Regulator and Reference
The MT6305 integrates seven LDOs that are optimized for their given functions by balancing
quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise.
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Figure 25. Functional Block Diagram of MT6305
2. Digital Core LDO (Vcore)The digital core LDO is a regulator that could source 100mA
with 1.2V output voltage with Pin3(DANODE) GND. If Pin2 is not GND, The output Voltage
is 1.8V. It supplies the baseband circuitry in the handset. The LDO is optimized for very low
quiescent current.
3. Digital IO LDO (DVDD)
The digital IO LDO is a regulator that could source 100mA with 2.8V output voltage. It supplies the
baseband circuitry in the handset.
4. Analog LDO (AVDD)
The analog LDO is a regulator that could source 150mA with 2.8V output voltage. It supplies the
analog sections of the baseband chipsets. The LDO is optimized for low frequency ripple rejection in
order to reject the ripple coming from the RF Power Amplifier burst frequency at 217Hz. The
Decoupling Capacitor C156 must be higher than X5R type.
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5. TCXO LDO ( Vtcxo)
The TCXO LDO is a regulator that could source 20mA with 2.8V output voltage. It supplies the
temperature compensated crystal oscillator, which needs its own ultra low noise supply and very good
ripple rejection ratio. The Decoupling Capacitor C156 must be higher than X5R type.
6. RTC LDO ( Vrtc)
The RTC LDO is a regulator that could source 200uA with 1.2V output voltage with Pin3 GND. If
Pin3 is not GND, The Output Voltage is 1.5V. It charges up a capacitor-type backup coin cell to run
the real-time clock module. The LDO features the reverse current protection.
7. Memory LDO ( Vmem)
The memory LDO is a regulator that could source 150mA with 1.8V or 2.8V output voltage selection
based on the supply specs of memory chips. It supplies the memory circuitry in the handset.
8. SIM LDO (Vsim)
The SIM LDO is a regulator that could source 20mA with 1.8V or 3.0V output voltage selection based
on the supply specs of subscriber identity modules card. The LDO is controlled independently of the
others LDO.
9. SIM card interface
It provides level shifting needs for low voltage GSM controller to communicate with either 1.8V or 3V
SIM cards. In ESL808, 3V SIM card is applied. All SIM cards contain a clock input, a reset input, and
a bi-directional data input/output. The clock and reset inputs to SIM cards are level shifted from the
supply of digital IO of baseband chipset to the SIM supply.
Figure 26. Status of Mobile Handset and LDOs.
10. Vibrator , Alerter, LED switches
Three built-in open-drain output switches drive the vibrator motor(Pin38), alerter beeper(Pin39) and
LEDs(Pin41) in the handset. Each switch is controlled by baseband chipset with enable pins. The
switch of LED can sink 150mA to drive up to 10 LEDs simultaneously for backlight. The switch of
vibrator can sink 250mA for a vibrator motor. The switch of alerter can sink 300mA to drive the
beeper. And all the open-drain output switches are high impedance when disable. LED pin is
dedicated to 7-colored indicator LED(In ESL808, dedicated to Slide Key BackLight LED),
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ALERTER pin is dedicated to Main KEY BackLight LED, VIBRATOR pin is dedicated to Vibrator
Motor.
11. Battery Charger
BATUSE pin can set MT6305 to fit the battery type. When BATUSE is set low, Li-ion battery is used.
MT6305 charges the battery in three phases : pre-charging, constant current mode charging, and
constant voltage mode charging. The circuitry of MT6305 combines with a PMOS transistor, diode,
current-sense resistor externally to form a simple and low cost linear charger. MT6305 is available
pulsed top-off charging algorithm by the CHRCNTL pin control from baseband chipset.
Figure 27. Charger and Voltage Detection
Figure 28. Li-Ion Battery Charging Profile.
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IV. S71PL129JB0BAW9U0 (Pseudo SRAM + Nor Flash
Memory) and K9K1208U0C Nand EEPROM)
1. S71PL129JB0BAW9U0
The S71PL129JB0BAW9U0 is a mixed multi-chip package containing a 32Mbit pseudo static RAM
and a 128Mbit Flash memory. The /BYTE inputs can be used to select the optimal memory
configuration. The power supply for the S71PL129JB0BAW9U0 can range from 2.7V to 3.3V. The
S71PL129JB0BAW9U0 can perform simultaneous read/write operations on its flash memory and is
available in a 107-pin BGA package making it suitable for a variety of applications. The Boot block
architecture for flash memory is a bottom boot block. The MCP has two CE# signal for Flash.
These CE# are controlled EA23 address Pin.
Figure 29. MCP Block diagram
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2. K9K1208U0C (Nand Flash EEPROM)
The K9K1208U0C,offered in 64Mx8Bit or 32Mx16bit, is 512mbit with spare 16MBit capacity. The
device is offered 2.7 ~ 3.3v VCC. Its NAND cell provides the most cost-effective solution for the
solid state mass storage market. A Program operation can be performaned in typical 200uS on the
528byte or 264word page and en erase operaton can be performaed in typical 2ms on a 16kbyte or 8K
word block. Data in the page can be read out at 60ns cycle time per byte. The I/O pins serve as the
ports for address and data input/output as well as command input. The R/B(Pin A6) must be pulled up.
Figure 30. Block Diagram
Figure 31. Array Organization
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RF section
I. MT6129 (RF Transceiver IC)
MT6129 includes LNAs, two RF quadrature mixers, an integrated channel filter, programmable gain
amplifiers(PGA), an IQ demodulator for the receiver, a precision IQ modulator with offset PLL for the
transmitter, two internal TX VCOs, a VCXO, on-chip regulators, and a fully programmable sigma-
delta fractional-N synthesizer with an on-chip RF VCO.
Figure 32. MT6129 Functional block diagram
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- Recommended Operating Range
Item Symbol Min Typ Max Unit
Power Supply Voltage(VBAT) VBAT 3.1 3.6 3.6 V
Power Supply Voltage(VCCD) VCCD 2.5 2.8 3.1 V
Operating Ambient Temperature Topr -20 25 75 C
1. Receiver
The receiver section of MT6120 includes Quad-band low noise amplifiers(LNAs), RF quadrature
mixers, an on-chip channel filter, Programmable Gain Amplifiers(PGAs), quadrature second mixers,
and a final low-pass filter. The very low-IF MT6129 uses image-rejection mixers and filters to
eliminate interference. With accurate RF quadrature signal generation and mixer matching techniques,
the image rejection of the MT6129 can reach 35dB for all bands. Compared to a direct conversion
receiver(DCR), MT6129's very low-IF architecture improves the blocking rejection, AM suppression,
as well as the adjacent channel interference performance.
The ESL808 was designed for Tri-Band(GSM900, DCS1800, PCS1900)
- Receiver Input Frequency
Mode Min Max Unit
GSM850 869 894 Mhz
GSM900 925 960 Mhz
DCS 1805 1880 Mhz
PCS 1930 1990 Mhz
2. Transmitter
The MT6120 transmitter section consists of two on-chip TX VCOs, buffer amplifiers, a down-
converting mixer, a quadrature modulator, an analog phase detector and a digital phase frequency
detector, each with a charge pump output and on chip loop filter. The dividers and loop filters are used
to achieve the desired IF frequency from the down-conversion mixer and quadrature modulator. For a
given transmission channel, the transmitter will select one of the two different TX reference dividing
numbers. These built-in components, along with an internal voltage controlled oscillator and a loop
filter, implement a translation loop modulator. The TX VCO output is fed to the power amplifier. A
control loop, implemented externally, is used to control the PA's output power level.
- Transceiver Output Frequency
Mode Min Max Unit
GSM850 824 849 Mhz
GSM900 880 915 Mhz
DCS 1710 1785 Mhz
PCS 1850 1910 Mhz
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3. TX VCO
Two power VCOs are integrated with OPLL to form a complete transmitter circuit. The TX VCO
output power is typically 9dBm with +/-2.5dB variation in EGSM bands and +8dBm output power
with +/-2dB variation in DCS1800/PCS1900 bands over extreme Temperature conditions.
The PAM(RF3146) Input range is Typically 3dBm. So 5dB Attenuator is added Between MT6129 and
RF3146. Tx VCO Trequency Range is same with Trasnsceiver Frequency Range.
4. Frequency Synthesizer
The MT6120 includes a frequency synthesizer with a fully integrated RF VCO to generate RX and TX
local oscillator frequencies. The PLL locks the RF VCO to a precision reference frequency at 26MHz.
To reduce the acquisition time or to enable fast settling time for multi-slot data services such as GPRS,
a digital loop along with a fast-acquisition system are implemented in the synthesizer. After the
calibration, a fast-acquisition system is utilized for a period of time to facilitate fast locking.
The frequency ranges of the synthesizer for RX mode are
RX mode GSM850 1737Mhz ~ 1788Mhz
E-GSM900 1850Mhz ~ 1920Mhz
DCS1800 1805Mhz ~ 1880Mhz
PCS1900 1930Mhz ~1990Mhz
The Calculate LO Freqnecy Fvco from RX Channel Frequency Fch is following.
Fvco = 2*Fch-200K for GSM850 and E-GSM900
Fvco = Fch-100K for DCS1800 and PCS1900.
The frequency ranges of the synthesizer for TX mode are
TX mode GSM850 1813Mhz ~ 1868Mhz
E-GSM900 1936Mhz ~ 2059Mhz
DCS1800 1881Mhz ~ 2008Mhz
PCS1900 2035Mhz ~2149Mhz
The Calculate LO Freqnecy Fvco from TX Channel Frequency Fch is following.
(set the divider ratio D1 of TX reference divider = 11)
Fvco = 2*D1*Fch/(D1-1) for GSM850 and E-GSM900
Fvco = D1*Fch/(D1-1) for DCS1800 and PCS1900.
The MT6129 uses a digital calibration technique to reduce the PLL settling time Once the RF
synthesizer is programmed through a 3-wire serial interface, the calibration loop is activated. The main
function of the calibration loop is to preset the RF VCO to the vicinity of the desired frequency
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quickly and correctly, thus aiding the PLL to settle faster. On the other hand, since a large portion of
initial frequency error is dealt with by the integrated calibration loop, the overall locking time can be
drastically reduced, irrespective of the desired frequency.
5. Voltage Control Crystal Oscillator(VCXO)
VCXO consists of an amplifier, a buffer, and a programmable capacitor array. The VCXO provides the
MT6129 with a selectable reference frequency of either 13MHz or 26MHz. When VCXOFRQ pin is
high, Output Frequency is 26Mhz. When VCXOFRQ pin is low, Output Frequency is 13Mhz.
VCXOFRQ is High in ESL808. The Amplifier is designed to be in series resonance with a standard
26Mhz crysatal. The Crystal is connected from the Input pin XAL of Amplifier to ground through a
series load capacitance. The buffer provides a typical 600mVpp voltage swing. As an alternative, the
reference frequency can ve provided by an external 26Mhz VCTCXO module. When Pin VCXOCXR
is tied to the VCCVCXO supply, the XTAL pin will accept an external signal. Furthermode, the
VCXO control pin can be tied to VCCVCXO to prevent the current leakage during the sleep mode
operation.
6. Regulator
The MT6129 internal regulators provide low noise, stable, temperature and process independent
supply voltages to critical blocks in the transceiver. An internal P-channel MOSFET pass transistor is
used to achieve a low dropout voltage of less than 150mV in all regulators.
II. RF3146 ( GSM850,EGSM,DCS and PCS Power
Amplifier Module)
Figure 33. RF3146 Block Diagram
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The RF3146 is a high-power, high-efficiency power amplifier module with integrated power control of
RFMD. The device is a self-contained 7mm*7mm*0.9mm lead frame module with 50ohm input and
output terminals. The power control function is also incorporated, eliminating the need for directional
couplers, detector diodes, power control ASICs and other power control circuitry(See figure 34) ; this
allows the module to be driven directly from the DAC output. The device is designed for use as the
final RF amplifier in EGSM900 and DCS handsets. On-board power control provides over 50dB of
control range with an analog voltage input. The RF3146 has Max +35dBm GSM output power and
Max +33dBm DCS output power at 3.5V.
Figure 34. The Shaded area are eliminated on RF3146.
Figure 35. Diagram of the power control
Figure 36. Diagram of the Power control
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Most power control systems in GSM sense either forward power or collector/drain current. The
RF3146 does not use a power detector A high-speed control loop is incorporated to regulated the
collector voltage of the amplifier while the stage are held at a constant bias. The Vramp signal is
multiplied by a factor of 2.65 and the collector voltage for the second and third stages are regulated to
the multiplied Vramp voltage. The basic circuit is shown in Figure 24.
III. ESHS-M090SF (Antenna Switch Module
for Tri- Band with SAW Filter)
ESHS-M090SF is an Antenna Switch Module for GSM900,DCS1800 and PCS1900 of Hitachi
Metals with Three SAW Modules. Control Pins (VC1, VC2) are connected to LB_TX, HB_TX
(signals from baseband processor). The Control Pins Operating range is 2.4V 2.8V.
Figure 37. The Evaluation board and control logic of ESHS-M090SF
The GSM900 and DCS1800/PCS1900 input port matching impedances are 50 ohm.
The GSM900, DCS1800 and PCS1900(Balance) output port matching impedance are 150ohm.
ESL808 TECHNICAL MANUAL