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PAMS Technical Documentation Schematics / Layouts RL7 v.10 TME-3
Block diagram v.RB5.0 ed.76
0 RXIINP
2 RXQINP
4 TXIOUTP
5 TXIOUTN
6 TXQOUTP
7 TXQOUTN
9 VREFRF01
8 VREFRF02
RF
RF
SYS 2 AFC AFC RXQINP
schematic 0 TXC TXC
TXQOUTP RXIINP
TXQOUTN
TXIOUTP
RFAUXCONV_O(2:0) TXIOUTN
RFCLK_I
RFCONV_O(9:0) 0 RFBUSCLK RFBUSCLK
1 RFBUSDA RFBUSDA
GENIO_O(31:0) 2 RFBUSEN1 RFCLKGND_I
RFBUSEN1
RFAUX_O(1:0) LPRFCLK_I
VREFRF01
RFICCNTRL_O(2:0)
VREFRF02
RFCLKGND_I
TXC TXP
5
RFCLK_I RESET
6
6
HGR_TEMP HGR_TEMP
SLOWAD_O(6:0)
RESET
PUSL_O(2:0)
LPRFCLK_I
Issue 1 04/2002 Nokia Corporation Page A-1
PAMS Technical Documentation Schematics / Layouts RL7 v.10 TME-3
Block Diagram System v.RB5.0 ed.128
CONN
ACCDIF(2:0)
KEYB(10:0)
GENIO(31:0)
DSP_MCUTEST(2:0)
AUDIO(4:0)
SLOWAD(6:0)
Components: 100-149
RF_BB
Gsm
SLOWAD(6:0) SLOWAD_O(6:0) SLOWAD_O(6:0)
RFCONV(9:0) RFCONV_O(9:0) RFCONV_O(9:0)
RFAUXCONV(2:0) RFAUXCONV_O(2:0) RFAUXCONV_O(2:0)
LPRFCLK LPRFCLK_I LPRFCLK_I
RFCLK RFCLK_I RFCLK_I
RFCLKGND RFCLKGND_I RFCLKGND_I
RFAUX(1:0) RFAUX_O(1:0) RFAUX_O(1:0)
GENIO(31:0) GENIO_O(31:0) GENIO_O(31:0)
PUSL(2:0) PUSL_O(2:0) PUSL_O(2:0)
POWER UPP RFICCNTRL(2:0) RFICCNTRL_O(2:0) RFICCNTRL_O(2:0)
high_density_2.0 basic8m
LCDUI(2:0) RFCLK Components: 400-419
RFCLKGND
PWRONX RFCONV(9:0) KEYB(10:0)
MEMORY
RFAUXCONV(2:0) GENIO(31:0) amd64mbit
RFCONVDA(5:0)
RFCONVDA(5:0)
RFICCNTRL(2:0)
AUDIO(4:0)
RFCONVCTRL(2:0) RFCONVCTRL(2:0)
MEMADDA(23:0)
GENIO(31:0)
AUDIODATA(1:0) AUDIODATA(1:0)
SLOWAD(6:0) MEMADDA(23:0)
AUDUEMCTRL(3:0) AUDUEMCTRL(3:0) MEMCONT(9:0) MEMCONT(9:0)
IACCDIF(5:0) IACCDIF(5:0) JTAG_EMULATION(6:0)
PUSL_E(2:0) PUSL(2:0) DSP_MCUTEST(2:0)
ACCDIF(2:0)
Components: 300-319
GENIO(31:0)
Components: 320-349
Components: 200-249
R&D
use
Issue 1 04/2002 Nokia Corporation Page A-2
PAMS Technical Documentation Schematics / Layouts RL7 v.10 TME-3
Schematic diagram RF-BB v.RB5.0 ed.20
RFCONV/RFCONV_O: 0: RXIINP
1: RXIINN
0 0 2: RXQINP
1 1 3: RXQINN
2 2 4: TXIOUTP
3 3 5: TXIOUTN
4 4 6: TXQOUTP
5 5 7: TXQOUTN
6 6 8: VREFRF02
7 7 9: VREFRF01
8 8
9 9
R400
RFCONV(9:0) RFCONV_O(9:0)
R401 Neg. inputs of RxI and RxQ
10k
are connected to VRef2
10k
C400 C401
100p 100p
13 GND GND 13
5 5
6 6
7 7
8 8 GENIO/GENIO_O
9 9
10 10
11 11
12 12
GENIO(31:0) GENIO_O(31:0)
RFAUXCONV/RFAUXCONV_O 0: TXC
0 0 1: TXPWRDET
1 1 2: AFC
2 2
RFAUXCONV(2:0) RFAUXCONV_O(2:0)
RFICCNTRL/RFICCNTR_O 0: RFBUSCLK
0 0 1: RFBUSDA
1 1 2: RFBUSEN1
2 2
RFICCNTRL(2:0) RFICCNTRL_O(2:0)
0 0
1 1
2 2
PUSL(2:0) PUSL_O(2:0)
SLOWAD/SLOWAD_O 5: VCXOTEMP
6: PATEMP
5 5
6 6
SLOWAD(6:0) SLOWAD_O(6:0)
RFAUX(1:0) Last references:
R403
LPRFCLK C403
LPRFCLK_I
RFCLK RFCLK_I
R403 C403
100R 100p
RFCLKGND RFCLKGND_I
GND
RFAUX_O(1:0)
Issue 1 04/2002 Nokia Corporation Page A-3
PAMS Technical Documentation Schematics / Layouts RL7 v.10 TME-3
Schematic Diagram UPP v.RB5.0 ed.26
D300
UPP8M_V1.1_UBGA144 PUSL(2:0)
A11 TESTMODE PURX K2 0
JTAG_EMULATION(6:0)
VBAT SLEEPX L1 1
0 GND C4 JTCLK SLEEPCLK H3 2
1 A2 JTRST
J300
2 A3 JTDI EARDATA E2 0
GND 3 C3 JTMS MICDATA F2 1
2 STIRXD 4 B3 JTDO
0 STITXD 5 B2 EMU0 UEMINT J2
AUDIODATA(1:0)
1 STISCLK 6 A1 EMU1 CBUSCLK G1
VBATT CBUSDA G2 0
0 B4 GENTEST0 CBUSENX F3 1
1 B5 GENTEST1 2
GND 31
2 C5 GENTEST2 GENIO31 D1 SIMIODa 3
GENIO30 C2 SIMIOCtrl 30
0 B11 GENIO0 GENIO29 D2 SIMIOClk 29
DSP_MCUTEST(2:0) AUDUEMCTRL(3:0)
1 A12 GENIO1 GENIO26 B1
2 A13 GENIO2
3 B12 GENIO3 IRTX H2 0
IRRX G3 1
A4 VDDDSP1 2 26
GENIO(31:0)
C1 VDDDSP2 MBUSTX E3 3
E1 VDDDSP3 MBUSRX D3 4
D5 VSSDSP1 5
VCORE VCORE D4 VSSDSP2 FBUSTX F1
F4 VSSDSP3 FBUSRX E4
IACCDIF(5:0)
K1 VDDMCU DBUSCLK K3 0
J4 VSSMCU DBUSDA L3 1
VCORE C300 DBUSEN1X J3 2
100n J1 VDDCORE1
N8 VDDCORE2
GND J13 N3 0
C301 VDDPDRAM1 RFCONVCLK RFCONVCTRL(2:0)
100n A9 VDDPDRAM2 GENIO18 K4 1
GND C302 H4 VSSCORE1 2 18
100n K7 L4 3 16
VSSCORE2 RXID
VIO H10 VSSPDRAM1 GENIO16 M4 4
GND D8 N4 5
VSSPDRAM2 RXQD
GND GENIO17 K5
RFCONVDA(5:0)
N10 VDDIO1 TXID M2 17
H1 VDDIO2 GENIO14 N1 14
A6 VDDIO3 TXQD N2 15
F13 M3 27p
C303 VDDIO4 GENIO15
100n K9 VSSIO1 AUXDA L2 C304
GND G4 VSSIO2
D7 VSSIO3 GENIO13 E12 13
GND
G10 VSSIO4 GENIO5 D11 5
C305 GENIO6 D12 6
MEMADDA(23:0) GND
100n N5 VDDA GENIO7 E10 7
GND GENIO8 E11 8
RFICCNTRL(2:0)
0 N7 0 GENIO9 D13 9
1 M8 1 GENIO10 F10 10
2 L10 2 GENIO11 F11 11
3 L11 3 GENIO12 E13 12
4 M12 4
5 N13 5 RFBUSCLK G11 0
6 L13 6 RFBUSDA F12 1
7 J11 7 RFBUSEN1X G13 2
8 GENIO25 G12
9 M7 8
10 M9 9 RFCLK M5
11 M10 L5 RFCLK
10 VSSA
12 M11 11
13 K11 D6 RFCLKGND
12 GENIO28
14 L12 13 GENIO4 A7
15 K13 14 LCDCAMCLK C6
J12 15 LCDCAMTXDA B6 0
GENIO27 A5 1
16 H11 16 LCDCSX C7 2
17 L8 17
18 L9 18 GENIO19 B13
LCDUI(2:0)
19 K8 19 GENIO20 C11 25
20 K12 20 GENIO21 C12 28
21 H12 21 GENIO22 C13 4
22 K6 22 27
23 19
9 K10 FLSRSTX P00 D9 0 20
P01 A10 1 21
0 N9 EXTWRX P02 B10 2 22
1 L7 EXTRDX P03 C10 3
P04 D10 4
2 L6 FLS2CSX
3 M6 FLSBAAX P10 A8 5
4 N11 FLSPS P11 B8 6
5 M13 FLSAVDX P12 C8 7
6 N12 FLSCLK P13 B9 8
7 N6 FLSCSX P14 C9 9
8 H13 FLSRDY P15 B7 10
23 M1 GENIO23 KEYB(10:0)
24 J10 GENIO24
MEMCONT(9:0)
Last references:
C305
X300
D300
Issue 1 04/2002 Nokia Corporation Page A-4
PAMS Technical Documentation Schematics / Layouts RL7 v.10 TME-3
Schematic Diagram UEM v. RB5.0 ed. 77
VBAT
PWRONX
VBATT1
GND
not_assembled
V201
RN1302 C245 D200 C200 C201
R207
10k
2u2 UEM_V4.4_WDOGS_ENABLED 1u0 10n
2x10k
M9 VCHARIN1 VCHAROUT1 N10
VFLASH1 V200 R1 VBATT6 VBATT3 VBATT2 VBATT1 P9 VCHARIN2 VCHAROUT2 P10
GND L6 L9
RN1302 R2 VCHARINK VCHAROUTK
GND GND
2x10k
D5 TESTMODE VBATREGS M10
R1 GNDREGS L10
GND GND P8
R2 VBATBB1
N9 M7 GND
VBATBB2 PWMO
N11 VBATBB3 PWM1C P4
N14 VBATBB4 CHDISX M5
GND A1
B200 VBATBB5
N8 GND
32.768kHz VANA
P7 M8 VANA
PWRONX VFLASH1
P11 VFLASH1 C202
VFLASH2
P1 M13 VFLASH2 1u0
OSCIN VCORE
P2 B1 VCORE C203 C204
VBACK OSCOUT VIO
VIO 1u0 1u0 GND
C205 C206 C207 C208
10p 10p P3 VBACK GNDFLASH1 L5 1u0 1u0
N3 GND GND
C209 C210 VRTC VSIM
GND VANA GND
100n 1u0 M4 OSCCAP VDAAUD2 N2
1u0 VANA GND
C212 100n EARP M2 C211 X200
K4 M1 100n GND 0
C213 1u0 VDAAUD1 EARN
GND GND GND GND GND N1 1
XEAR
GND H2 3 VSIM GND 4
AUDIO(4:0) C214 MICBCAP 2
GND H1 N6 2 RST VPP 5
MICB1 HEADINT
2 3 4 J2 L1 1 SIMCLK DATA 6
MIC1P HF
E100
J1 MIC1N HFCM L2 C215 SK51002-001
VSAAUD2 L3 100n
GND