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5 4 3 2 1
VER : 1A
BOM P/N Description
ZRL BLOCK DIAGRAM
31ZRLMB0000 ZRL MB ASSY(UMA,HR,DC)W/O CPU CHARGER
31ZRLMB0010 ZRL MB(UMA,HR,DC,SURGE)W/O CPU ISL88731 P27
D D
3/5V SYS PWR
RT8223M P28
intel
CPU CORE PWR
ISL95835 P29
DDR SYSTEM MEMORY
SandyBridge CPU +1.05V_VTT +1.8V
RT8238A P30 HPA00835RTER P33
DC 35W PCI-E
X16
DDR3 +1.5_SUS discharger
RT8207A P31 P33
DDR III - SODIMM 0 Dual Channel DDR III rPGA 988
(37.5mm X 37.5mm)
1066 MHz
DDR III - SODIMM 1 +VCCSA Thermal protect
RT8241DZ P32 P33
C P14, 15 FDI CLK DMI C
P4~P7 5GT/s
FDI interface X4 DMI interface
2.7GT/s 5GT/s
SATA0
HDD (SATA) FDI CLK DMI INT_CRT
P20 CRT
intel
iGFX Interfaces
P16
SATA Gen3
SATA1
ODD (SATA) SATA Gen2 INT_LVDS
P20 LVDS P16
USB 2.0
USB 2.0 * 3 INT_HDMI
CougarPoint 0.7 PCI-E HDMI
USB1,3,9 P24 USB P17
B
Bluetooth B
HDA PCI-Express Gen2 PCIE-6
USB4 P24
mBGA 989 5GT/s MINI CARD
(25mm X 25mm) USB-13
WLAN
CCD (Camera) P19
Azalia Note:
USB8 P16 HM65 not support USB 6 & 7
RTC HM65 not support SATA 2 & 3
P8~P13 X'TAL
X'TAL P9 PCIE-1
Card Reader 25MHz ATHEROS AR8158
32.768KHz
SPI LPC
RJ45
USB12 P23
10/100 LAN P18 P18
X'TAL
25MHz
Audio CODEC Dual SPI ROM WPCE791/FLASH
REALTEK ALC271X
4MB x1 (Basic ME+Braidwood) NPCE971
P21 P9 P26
A A
Quanta Computer Inc.
HP Jack MIC Jack SPK DMIC SPI ROM Touch Pad Keyboard Fan Driver PROJECT : ZRL
Size Document Number Rev
P22 P22 P21 P21 P26 P25 P25
(DA Type) P25 1A
Block Diagram
Date: Tuesday, June 21, 2011 Sheet 1 of 34
5 4 3 2 1
1 2 3 4 5 6 7 8
ZRL power tree
+5VPCU +5VPCU
MDV1660 3A
+5V_S5
RT8223M
A
PU4 A
MDV1660 +5V 2.5A
VIN
+3VPCU +3VPCU
AO3404 0.21A
+3V_S5
MDV1660 +3V 3.65A
ADAPTER Smart HPA00835RTER
+1.8V 1.75A
Charger
PU7
ISL88731C
BATTERY PU2
B B
+1.5V_SUS +1.5V_SUS 13A
AO3404 +1.5V 0.38A
RT8207L
PU9 0.75A
+0.75V_DDR_VTT
+SMDDR_VREF 0.38A
VIN
RT8238A 14A
+1.05V_S5
PU8
Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
RT8241DZ +VCCSA 6A
C VIN +10V~+19V MAIN POWER ALWAYS ALWAYS C
PU6
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
ISL95835HRTZ-T +VCC_GFX 33A
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
PU5
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5
+5V_S5 +5V USB POWER S5_ON S0-S5
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0 +VCC_CORE 53A
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
D D
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
Quanta Computer Inc.
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable PROJECT : ZRL
Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
Date: Tuesday, June 21, 2011 Sheet 2 of 34
1 2 3 4 5 6 7 8
5 4 3 2 1
03
D D
+3V_S5 +3V_S5
+3V_GPU +3V_GPU
+3V_GPU
2.2K 2.2K
N12P-GE
2.2K 2.2K
SMB_ME0_CLK
G
D S I2CS_SCL
NMOS
SMB_ME0_DAT
G
D S I2CS_SDA
NMOS
+3V_S5 +3V_S5 +3VPCU +3VPCU
+3V_S5
C C
intel 2.2K 2.2K 6.8K 6.8K
G
SMB_ME1_CLK S NMOS D MBCLK EC
G
ITE 8518
SMB_ME1_DAT S D MBDATA
CougarPoint 0.7 NMOS
mBGA 989
+3V_S5 +3V_S5 +3V +3V
(25mm X
25mm) +3V_S5
Slave ADDRESS :A0H Slave ADDRESS :A4H
DDR3 DIMM-0-STD VREF DQ0 DDR3 DIMM-1-STD VREF DQ1
B (5.2H) M2 Solution (9.2H) M2 Solution B
2.2K 2.2K 4.7K 4.7K
G
SMB_PCH_CLK D S SMB_RUN_CLK
NMOS
G
SMB_PCH_DAT D S SMB_RUN_DAT
NMOS
A A
Quanta Computer Inc.
PROJECT :ZRL
Size Document Number Rev
1A
SMBus Address
Date: Tuesday, June 21, 2011 Sheet 3 of 34
5 4 3 2 1
5 4 3 2 1
Sandy Bridge Processor (DMI,PEG,FDI)
U17A
Sandy Bridge Processor (CLK,MISC,JTAG)
U17B
04
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
[8] DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22
[8] DMI_TXN1 B25 A28 CLK_CPU_BCLKP [10]
MISC
CLOCKS
DMI_RX#[1] BCLK
[8] DMI_TXN2 A25 DMI_RX#[2] [9] H_SNB_IVB# C26 PROC_SELECT# BCLK# A27 CLK_CPU_BCLKN [10]
D B24 K33 D
[8] DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
PEG_RX#[1] M35
B28 L34 SKTOCC# AN34
[8] DMI_TXP0 DMI_RX[0] PEG_RX#[2] TP75 SKTOCC#
[8] DMI_TXP1 B26 DMI_RX[1] PEG_RX#[3] J35 DPLL_REF_CLK A16 CLK_DPLL_SSCLKP [10]
DMI
[8] DMI_TXP2 A24 DMI_RX[2] PEG_RX#[4] J32 DPLL_REF_CLK# A15 CLK_DPLL_SSCLKN [10]
[8] DMI_TXP3 B23 DMI_RX[3] PEG_RX#[5] H34
PEG_RX#[6] H31
G21 G33 TP_CATERR# AL33
[8] DMI_RXN0 DMI_TX#[0] PEG_RX#[7] TP76 CATERR#
[8] DMI_RXN1 E22 DMI_TX#[1] PEG_RX#[8] G30
[8] DMI_RXN2 F21 F35
THERMAL
DMI_TX#[2] PEG_RX#[9]
[8] DMI_RXN3 D21 DMI_TX#[3] PEG_RX#[10] E34
PEG_RX#[11] E32 [11,26] EC_PECI AN33 PECI SM_DRAMRST# R8 CPU_DRAMRST# [5]
[8] DMI_RXP0 G22 D33
DDR3
MISC
DMI_TX[0] PEG_RX#[12]
[8] DMI_RXP1 D22 DMI_TX[1] PEG_RX#[13] D31
PCI EXPRESS* - GRAPHICS
[8] DMI_RXP2 F20 DMI_TX[2] PEG_RX#[14] B33
C21 C32 [26,29] H_PROCHOT# R23 56_4 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R138 140/F_4
[8] DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP_1 R369 25.5/F_4
SM_RCOMP[1] SM_RCOMP_2 R383 200/F_4
PEG_RX[0] J33 SM_RCOMP[2] A4
PEG_RX[1] L35
K34 [11] PM_THRMTRIP# PM_THRMTRIP# AN32
PEG_RX[2] THERMTRIP#
[8] FDI_TXN0 A21 FDI0_TX#[0] PEG_RX[3] H35
[8] FDI_TXN1 H19 FDI0_TX#[1] PEG_RX[4] H32
[8] FDI_TXN2 E19 FDI0_TX#[2] PEG_RX[5] G34
Intel(R) FDI
[8] FDI_TXN3 F18 FDI0_TX#[3] PEG_RX[6] G31
B21 F33 AP29 XDP_PRDY# TP78
[8] FDI_TXN4 FDI1_TX#[0] PEG_RX[7] PRDY#
C20 F30 AP27 XDP_PREQ#
[8] FDI_TXN5 FDI1_TX#[1] PEG_RX[8] PREQ#
[8] FDI_TXN6 D18 FDI1_TX#[2] PEG_RX[9] E35
E17 E33 AR26 XDP_TCLK
[8] FDI_TXN7
PWR MANAGEMENT
FDI1_TX#[3] PEG_RX[10] TCK
JTAG & BPM
F32 AR27 XDP_TMS
PEG_RX[11] TMS XDP_TRST#
PEG_RX[12] D34 [8] PM_SYNC AM34 PM_SYNC TRST# AP30
C [8] FDI_TXP0 A22 FDI0_TX[0] PEG_RX[13] E31 C
G19 C33 R13 10K_4 AR28 XDP_TDI
[8] FDI_TXP1 FDI0_TX[1] PEG_RX[14] TDI
E20 B32 C17 0.1U/10V_4 AP26 XDP_TDO
[8] FDI_TXP2 FDI0_TX[2] PEG_RX[15] TDO
[8] FDI_TXP3 G18 FDI0_TX[3] [11] H_PWRGOOD AP33 UNCOREPWRGOOD
[8] FDI_TXP4 B20 FDI1_TX[0] PEG_TX#[0] M29
[8] FDI_TXP5 C19 FDI1_TX[1] PEG_TX#[1] M32
[8] FDI_TXP6 D19 FDI1_TX[2] PEG_TX#[2] M31 DBR# AL35 XDP_DBRST# XDP_DBRST# [8]
F17 L32 PM_DRAM_PWRGD_R V8
[8] FDI_TXP7 FDI1_TX[3] PEG_TX#[3] SM_DRAMPWROK
PEG_TX#[4] L29
[8] FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 BPM#[0] AT28
[8] FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 +1.05V_VTT R295 75_4
BPM#[1] AR29
PEG_TX#[7] J30 BPM#[2] AR30
H20 J28 CPU_PLTRST# R296 43_4 CPU_PLTRST#_R AR33 AT30
[8] FDI_INT FDI_INT PEG_TX#[8] RESET# BPM#[3]
PEG_TX#[9] H29 BPM#[4] AP32
[8] FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#[10] G27 BPM#[5] AR31
[8] FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 BPM#[6] AT31
PEG_TX#[12] F27 BPM#[7] AR32
PEG_TX#[13] D28
PEG_TX#[14] F26
PEG_TX#[15] E25
A18 eDP_COMPIO
eDP_COMP A17 M28 CPU-989P-rPGA
INT_eDP_HPD_Q eDP_ICOMPO PEG_TX[0]
B16 eDP_HPD PEG_TX[1] M33
M30 +3V_S5
PEG_TX[2]
PEG_TX[3] L31
C15 eDP_AUX PEG_TX[4] L28
D15 K30 +3V_S5
eDP_AUX# PEG_TX[5]
eDP
K27 +1.5V_CPU
PEG_TX[6] C453
PEG_TX[7] J29
C17 J27 0.1U/10V_4
eDP_TX[0] PEG_TX[8]
B F16 eDP_TX[1] PEG_TX[9] H28 B
C16 G28 C374
eDP_TX[2] PEG_TX[10] R393 U14 0.1U/10V_4
G15 eDP_TX[3] PEG_TX[11] E28
5
F28 U22 200/F_4 1 5
PEG_TX[12] NC VCC
C18 eDP_TX#[0] PEG_TX[13] D27 [8,26] SYS_PWROK 2
E16 E26 4 PM_DRAM_PWRGD_Q R392 130/F_4 PM_DRAM_PWRGD_R [10,18,19,23,26] PLTRST# 2
eDP_TX#[1] PEG_TX[14] IN
D16 eDP_TX#[2] PEG_TX[15] D25 [8] PM_DRAM_PWRGD 1
F15 3 4 CPU_PLTRST#
eDP_TX#[3] 74AHC1G09 GND OUT
3
R391 *39_4 3 1 74LVC1G07GW
CPU-989P-rPGA
Q21 *2N7002D
2
MAINON_ON_G [6,33]
DP & PEG Compensation Processor pull-up(CPU) +1.05V_VTT +1.05V_VTT
eDP Hot-plug
3
+1.05V_VTT +1.05V_VTT +1.05V_VTT
2 Q18
[8,29] IMVP_PWRGD
HPD disable R294
H_PROCHOT# R17 62_4 FDV301N 10K_4
R322 24.9/F_4 eDP_COMP R62 24.9/F_4 PEG_COMP XDP_TDO R47 51_4
A XDP_TMS R309 51_4 A
1
eDP_COMPIO and ICOMPO signals should PEG_ICOMPI and RCOMPO signals should XDP_TDI R306 51_4 INT_eDP_HPD_Q
XDP_PREQ# R44 *51_4
be shorted near balls and routed with be routed within 500 mils