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Magpie
VC0918
Magpie TM
Mobile Phone Audio Processor ------ MIDI
Hardware Design Application
Notes
Version: 1.42
Preliminary
Vimicro Subject to change without notice 1
July 8th, 2004
Magpie
1. SYSTEM BLOCK DIAGRAM .....................................................................................................4
2. ELECTRICAL CHARACTERISTICS........................................................................................5
2.1. ABSOLUTE MAXIMUM RANGE ...................................................................................................5
2.2. DC CHARACTERISTICS .............................................................................................................5
2.3. DIGITAL AC CHARACTERISTICS ................................................................................................6
2.4. ANALOG CHARACTERISTICS .....................................................................................................6
2.4.1. PLL AC CHARACTERISTICS ..................................................................................................6
2.4.2. POWER REGULATOR CHARACTERISTICS ...............................................................................6
2.4.3. AUDIO DAC CHARACTERISTICS ...........................................................................................6
2.4.4. DAC AC CHARACTERISTICS ................................................................................................7
2.4.5. SPEAKER POWER AMPLIFIER ................................................................................................7
3. INPUT CLOCK..............................................................................................................................9
4. HOST INTERFACE ......................................................................................................................9
4.1. 12-WIRE PARALLEL HOST INTERFACE ........................................................................................9
4.2. 4-WIRE SERIAL HOST INTERFACE .............................................................................................14
4.3. 3-WIRE SERIAL HOST INTERFACE .............................................................................................16
4.4. POWER SWITCH DESIGN ..........................................................................................................18
5. SYSTEM RESET SCHEME .......................................................................................................18
5.1. EFFECTS OF VARIOUS RESETS ........................................................................................................19
6. WORKING MODES....................................................................................................................20
6.1. OPERATION FLOW OF MODE SWITCH .......................................................................................20
6.1.1. The clock start/stop sequence ........................................................................................20
a) Clock start sequence in PLL working ....................................................................................20
b) Clock stop sequence in PLL working.....................................................................................20
c) Clock start sequence in PLL bypass mode.............................................................................21
d) Clock stop sequence in PLL bypass mode..............................................................................21
6.1.2. Power Down to StandBy mode ......................................................................................21
6.1.3. Standby mode to Idle mode............................................................................................21
6.1.4. Idle mode to Normal mode ............................................................................................22
6.1.5. Normal mode to Idle mode ............................................................................................22
6.1.6. Idle mode to Standby mode............................................................................................23
6.2. PIN DIR UNDER STANDBY MODE .............................................................................................23
6.3. WORKING STATUS OF EACH MODULE IN DIFFERENT MODE ......................................................24
6.4. POWER CONSUMPTION ...........................................................................................................24
7. SOUND VOLUME IMPROVEMENT SCHEME.....................................................................25
8. AIR CHAMBER DESIGN METHOD .......................................................................................25
9. OTHERS.......................................................................................................................................26
9.1 I2S INTERFACE........................................................................................................................26
Vimicro Subject to change without notice 2
July 8th, 2004
Magpie
9.2 PAD CONTROL REGISTERS .......................................................................................................26
10. PCB LAYOUT NOTES: ..........................................................................................................28
Vimicro Subject to change without notice 3
July 8th, 2004
Vimicro
July 8th, 2004
Stereo
Headphone
Mono
Headphon
MIC
e
VC0918 have one mono speaker output.
Voice
ADC
Voice
DAC
HOR HOL
1. System Block Diagram
Timer
CLK VC0918 Mono
VC0918 have one auxiliary analog input to speak Amplifier.
PLL clock Earphone
Wavetable
Subject to change without notice
LO
Synthesizer DAC
VC0918 have one stereo headphone output, external PA is needed.
40channel 16bit
SYS CON Fs=48KHz
HOST LI
Sequencer
I/F
ADPCM
/
PCM
Engine AUXI
BaseBand
Speaker
Volume
LED
SO1
Hand-free
Vibrator
Speaker
I2S IN I2S OUT SO2
VREF
4
Magpie
FM Tuner / MP3 Decoder
Magpie
VC0918 have one I2S digital audio input interface
VC0918 have one I2S output interface
2. Electrical Characteristics
All power supply pins should be by-passed with two capacitors, 10