Text preview for : compal_la-7912p_r0.4_schematics.pdf part of acer compal la-7912p r0.4 schematics acer Notebook Ноутбук Acer Aspire V3-571 compal_la-7912p_r0.4_schematics.pdf



Back to : compal_la-7912p_r0.4_sche | Home

A B C D E




Compal Confidential
Model Name :Q5WV1/Q5WS1
Compal Project Name :
1 1

File Name : LA-7912P




Compal Confidential
2 2




Q5WV1 M/B Schematics Document
Intel Sandy/Ivy Bridge Processor with DDRIII + Panther Point PCH
Nvidia N13P GS/GL


3
2011-12-24 3




REV:0.2




ZZZ2 1G@ ZZZ3 2G@
MB PCB
4 4
Part Number Description
DA60000SV00 PCB 0N4 LA-7912P REV0 M/B
X76344BOL01 X76344BOL02


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A7912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019ID
Date: Friday, January 06, 2012 Sheet 1 of 60
A B C D E
A B C D E




Fan Control
page 42




1 1




100MHz PCI-E 2.0x16 5GT/s PER LANE
PEG(DIS) Intel Memory BUS(DDRIII)
Nvidia 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
N13P GS/GL Sandy/Ivy Bridge BANK 0, 1, 2, 3 page 11,12
1.5V DDRIII 1066/1333
Processor
page22~30

eDP rPGA989
page31
page 4~10

FDI x8 DMI x4 USB 2.0 conn x2 Bluetooth CMOS Camera
Conn
USB port 0,1 on USB port 13 USB port 10
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz USB/B page 38 page 38 page 31
page 33 page 32 page 31 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2
LVDS(UMA/OPTIMUS)
Intel
CRT(UMA/OPTIMUS) HD Audio 3.3V 24MHz

TMDS(UMA/OPTIMUS) Panther Point-M
PCH
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz HDA Codec
989pin BGA ALC271X/281X
port 5 port 3 port 1 SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz SPI page 41
page 13~21

USB 3.0 conn x1 LAN(GbE) & port 1 port 0
MINI Card x1 port 2
Fresco FL1009 WLAN Card Reader SATA HDD
with USB3.0 Conn. USB port 11 page 37 BCM57785
page 35,36
Conn. page 34 SPI ROM x1 Int. Speaker Phone Jack x 2
page 45 port 2
page 13
page 41 page 41
MSATA(WWAN) SATA CDROM
Card Reader RJ45 USB port 8 page 34
3 Conn. page 34 LPC BUS 3

Conn. page 35,36 page 36
33MHz


ENE KB930/KB9012
page 39

RTC CKT.
page 13
Touch Pad Int.KBD
page 40 page 40

Power On/Off CKT. Sub-board
page 40
LS-7911P
USB 2.0/B 2Port BIOS ROM
USB Port0,1
page 39 page 40
DC/DC Interface CKT.
4
page 43,44 4


LS-7912P
Power Circuit DC/DC PWR/B
page 41
page 46~59 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A7912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019ID
Date: Friday, January 06, 2012 Sheet 2 of 60
A B C D E
A B C D E




Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VTT +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW +3VALW always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW_EC +3VALW always to KBC ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON*
+5VS +5VALW to +5VS switched power rail ON OFF OFF
BOARD ID Table BTO Option Table
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
+RTCVCC RTC power ON ON ON
BTO Item BOM Structure
Board ID PCB Revision
UMA Only UMAO@
0
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Dis with OPTIMUS DIS@
1
Blue Tooth BT@
EC SM Bus1 address EC SM Bus2 address 2
Internal USB 3.0 PUSB@
3 0.1
Device Address Device Address
eDP eDP@
4 0.2
Smart Battery 0001 011X b
VRAM X76@
5 0.3
Connector CONN@
6 0.4
Unpop @
PCH SM Bus address 7
N13P-GS GS@
Device Address
N13P-GL GL@
3 Win8 Win8@ 3
Clock Generator (9LVS3199AKLFT, 1101 0010b Audio ALC271X 271X@
RTM890N-631-VB-GRT) USB Port Table
DDR DIMM0 1001 000Xb
Audio ALC281X 281X@
3 External
USB 2.0 USB 1.1 Port PCH HM65 HM65@
DDR DIMM2 1001 010Xb USB Port
PCH HM76 HM76@
0 USB3.0 colay USB2.0 Conn
UHCI0
BT & USB30 & USB20 Config 1 USB/B (Right Side)
OPTMIUS SKU:DIS@ N13P-GL:GL@ N13P-GS:GS@ N13P-GF108_ES4:GF108@ 2 USB/B (Right Side)
UHCI1
BT SKU:BT@ 3
EHCI1
internal USB SKU: PUSB@ DIS USB30 SKU:DUSB@ 4
UHCI2
eDP SKU: EDP@ 5
LVDS SKU: LVDS@ 6
UHCI3
EC 930 SKU: 930@ EC 9012 SKU: 9012@ 7
PCH HM65: HM65@ PCH HM76: HM76@ 8 Mini Card 1(WLAN)
UHCI4
Win8: WIN8@ 9
10 Camera
EHCI2 UHCI5
11 BlueTooth
4 4
12
UHCI6
13


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A7912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019ID
Date: Friday, January 06, 2012 Sheet 3 of 60
A B C D E
5 4 3 2 1




D +1.05VS_VTT D
PEG_ICOMPI and PEG_RCOMPO signals should be
shorted and routed,




1
R517
max length = 500 mils,trace width=4mils
24.9_0402_1% PEG_ICOMPO signals should be routed with - max
JCPU1A
length = 500 mils,trace width=12mils




2
PEG_ICOMPI J22 PEG_COMP spacing =15mils
PEG_ICOMPO J21
<15> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
<15> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<15> DMI_CRX_PTX_N2 A25 DMI_RX#[2]
<15> DMI_CRX_PTX_N3 B24 K33 PEG_GTX_C_HRX_N15 C46 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N15
DMI_RX#[3] PEG_RX#[0] PEG_GTX_C_HRX_N14 C49 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N14
PEG_RX#[1] M35 1 2
<15> DMI_CRX_PTX_P0 B28 L34 PEG_GTX_C_HRX_N13 C51 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N13
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N12 C53 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N12
<15> DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 1 2
<15> DMI_CRX_PTX_P2 A24 J32 PEG_GTX_C_HRX_N11 C60 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N11




DMI
DMI_RX[2] PEG_RX#[4] PEG_GTX_HRX_N[0..15] <22>
<15> DMI_CRX_PTX_P3 B23 H34 PEG_GTX_C_HRX_N10 C71 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N10
DMI_RX[3] PEG_RX#[5] PEG_GTX_HRX_P[0..15] <22>
H31 PEG_GTX_C_HRX_N9 C75 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8 C82 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N8
<15> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 1 2 PEG_HTX_C_GRX_N[0..15] <22>
E22 G30 PEG_GTX_C_HRX_N7 C92 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N7
<15> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PEG_HTX_C_GRX_P[0..15] <22>
F21 F35 PEG_GTX_C_HRX_N6 C93 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N6
<15> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_GTX_C_HRX_N5 C102 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N5
<15> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
E32 PEG_GTX_C_HRX_N4 C111 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N4
PEG_RX#[11] PEG_GTX_C_HRX_N3 C113 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N3
<15> DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33 1 2
D22 D31 PEG_GTX_C_HRX_N2 C125 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N2
<15> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
F20 B33 PEG_GTX_C_HRX_N1 C129 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N1




PCI EXPRESS* - GRAPHICS
<15> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
C21 C32 PEG_GTX_C_HRX_N0 C144 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N0
<15> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PEG_GTX_C_HRX_P15 C47 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14 C50 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P14
PEG_RX[1] L35 1 2
C PEG_GTX_C_HRX_P13 C52 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P13 C
PEG_RX[2] K34 1 2
A21 H35 PEG_GTX_C_HRX_P12 C56 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P12
<15> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
H19 H32 PEG_GTX_C_HRX_P11 C66 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P11
<15> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PEG_GTX_C_HRX_P10 C68 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P10
<15> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_GTX_C_HRX_P9 C81 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P9
<15> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]




Intel(R) FDI
B21 F33 PEG_GTX_C_HRX_P8 C86 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P8
<15> FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PEG_GTX_C_HRX_P7 C89 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P7
<15> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PEG_GTX_C_HRX_P6 C100 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P6
<15> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_GTX_C_HRX_P5 C105 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P5
<15> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PEG_GTX_C_HRX_P4 C106 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P4
PEG_RX[11] PEG_GTX_C_HRX_P3 C117 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P3
PEG_RX[12] D34 1 2
A22 E31 PEG_GTX_C_HRX_P2 C119 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P2
<15> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_GTX_C_HRX_P1 C135 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P1
<15> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
E20 B32 PEG_GTX_C_HRX_P0 C138 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P0
<15> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
<15> FDI_CTX_PRX_P3 G18 FDI0_TX[3]
B20 M29 PEG_HTX_GRX_N15 C516 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N15
<15> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PEG_HTX_GRX_N14 C520 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N14
<15> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PEG_HTX_GRX_N13 C529 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N13
<15> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_HTX_GRX_N12 C534 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N12
<15> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PEG_HTX_GRX_N11 C538 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N11
+1.05VS_VTT PEG_TX#[4] PEG_HTX_GRX_N10 C540 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N10
eDP_COMPIO and ICOMPO signals should <15> FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
<15> FDI_FSYNC1 J17 K28 PEG_HTX_GRX_N9 C542 1 2 GSGL@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N9
be shorted near balls, FDI1_FSYNC PEG_TX#[6]
J30 PEG_HTX_GRX_N8 C544 1 2 GSGL@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N8
PEG_TX#[7] PEG_HTX_GRX_N7 C546 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N7
Trace Width for EDP_COMPIO=4mils, <15> FDI_INT H20 FDI_INT PEG_TX#[8] J28 1 2
H29 PEG_HTX_GRX_N6 C548 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N6
EDP_ICOMPO=12mils, PEG_TX#[9]
1




<15> FDI_LSYNC0 J19 G27 PEG_HTX_GRX_N5 C550 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N5
FDI0_LSYNC PEG_TX#[10]
and both length less than 500 mils... R145 <15> FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 PEG_HTX_GRX_N4 C552 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N4
24.9_0402_1% F27 PEG_HTX_GRX_N3 C554 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N3
should not be left floating PEG_TX#[12]
D28 PEG_HTX_GRX_N2 C556 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N2
PEG_TX#[13]
,even if disable eDP function... F26 PEG_HTX_GRX_N1 C558 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N1
2




PEG_TX#[14] PEG_HTX_GRX_N0 C560 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N0
PEG_TX#[15] E25 1 2
EDP_COMP A18
B eDP_COMPIO PEG_HTX_GRX_P15 C515 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P15 B
A17 eDP_ICOMPO PEG_TX[0] M28 1 2
EDP_HPD# B16 M33 PEG_HTX_GRX_P14 C528 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P14
eDP_HPD# PEG_TX[1] PEG_HTX_GRX_P13 C533 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P13
PEG_TX[2] M30 1 2
L31 PEG_HTX_GRX_P12 C536 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P12
PEG_TX[3] PEG_HTX_GRX_P11 C539 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P11
<31> EDP_AUXP C15 eDP_AUX PEG_TX[4] L28 1 2
PEG_HTX_GRX_P10 C541 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P10
Add eDP circuit <31> EDP_AUXN D15 eDP_AUX# PEG_TX[5] K30
K27 PEG_HTX_GRX_P9 C543
1