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5 4 3 2 1




VER : 1A
BOM P/N
31ZK6MB0000
41ZK6CS0000
51ZK6SS0000
31ZK6MB0010
Description

uma / mxm
00 / 10
ZK6 MB Block Diagram
41ZK6CS0010
51ZK6SS0010


D
LM95245 D

PENRYN Thermal Sensor P3
479 uFCPGA
Fan Driver
P29 CH7318
FSB P3,4 PCIE
BOM Option Table HDMI Level Shifter
Reference Description P19
FSB(800/1066MHZ)
I@ INT VGA SLG8SP513VTR X'TAL HDMI Con.
E@ EXT VGA 14.318MHz P19




DDR SYSTEM MEMORY
CLOCK GENERATOR FSB
SP@ SPECIAL FOR EXT/INT VGA
P2




Graphics Interfaces
* DNI EXT_HDMI
CANTIGA PCI-E x16 EXT_CRT CRT Con.




P18,P19
MXM 3




SWITCH CIRCUIT
Dual Channel DDR III NB P18
DDRIII-SODIMM1 P5,P6,P7,P8, P9,P10,P11
800/1066 MHZ P17
EXT_LVDS
DDRIII-SODIMM2
P16
INT_CRT
DMI USB-11
LVDS/CCD/MIC
INT_LVDS
Con.
Int. MIC P18
C C
DMI(x4)
SATA - HDD
P23
SATA 0 & SATA 4 DMI
THERMAL
SATA PROTECTION P36
SATA - ODD SATA 1 PCIE-2 & PCIE-4
PCI-E MINI CARD
P23
WLAN/ TV 2.5V/ 1.5V PWR
USB-2 & USB-3
TI SN75LVCP412 P22 DISCHARGER P37
USB/eSATA Maxim 4951 SATA 5
P28 USB-1
Re-driver P28
ISL6251
CCD USB-6 PCIE-6 AR8131 CHARGER P31
P18 Intel ICH9M RJ45
GIGA LAN P20
SB P21 ISL6237
USB-0 & USB-10 USB 2.0 (Port0~9) P12, 13, 14, 15 3/5V SYS PWR P32
USB Port x2 USB X'TAL
P28 25MHz
ISL6262A
CPU CORE PWR P33
B USB/B Con. USB-4 & USB-7 X'TAL RTS5159 B
32.768KHz USB Cardreader Con.
P28 Cardreader RT8202
4 IN 1
FFC cable Controller P26 P26 +1.05V P34
USB-5
Bluetooth Con. BATTERY RTC
P21 IHDA
ISL6263A
P12 +1.05V_AXG P35
LPC
Azalia cable
USB-9
MDC Con. RJ11
WIRE CONN.
Finger Printer P24
P29
TPS5116
LPC DDR PWR P36


Int. MIC
X'TAL
WPC775LDG ALC888S-VC
32.768KHz EC P30
AUDIO CODEC P24
MIC MIC JACK
P24
POWER TREE
P38



Power CIR MMB Board Touch Pad AN12947A MAX9737 LINE IN P25
A A
Board Con. Con. Board Con.
AUDIO AMP SUB AMP
P27 P30 P27 P29 P25 P25



K/B Con. W25X16VSS1G EM-6781-T3 HP/SPDIF Speaker SUBWOOFER
SPI FLASH HALL SENSOR P25 P25 P25 Quanta Computer Inc.
P29 P30 P18 PROJECT : ZK6
Size Document Number Rev
1A
Block Diagram
Date: Friday, April 24, 2009 Sheet 1 of 42
5 4 3 2 1
5 4 3 2 1



Clock Generator
L13
+3V +3V_CLK
BKP1608HS181-T/1.5A/180ohm_0603
U12
C513 C244 C259 C249 C231 C227 C223 4 55
VDD_REF NC
9 VDD_PCI
10u/6.3V_6 .1u/10V_4 *.1u/10V_4 .1u/10V_4 *.1u/10V_4 .1u/10V_4 .1u/10V_4 16 7 CGCLK_SMB
VDD_48 SCLK CGDAT_SMB
23 VDD_PLL3 SDA 6
D D
46 VDD_SRC
L16 62 45 PM_STPPCI# <14>
+1V05_CLK VDD_CPU SRC5/PCI_STOP#
+1.05V SRC5#/CPU_STOP# 44 PM_STPCPU# <14>
BKP1608HS181-T/1.5A/180ohm_0603
C254 C252 C253 C258 C260 C251 C245 61 CLK_CPU_BCLK_RRP2 1 2 shortpad
CPU0 CLK_CPU_BCLK <3>
19 60 CLK_CPU_BCLK#_R 3 4
VDD_IO CPU0# CLK_CPU_BCLK# <3>
10u/6.3V_6 .1u/10V_4 .1u/10V_4 .1u/10V_4 *.1u/10V_4 .1u/10V_4 .1u/10V_4 27 VDD_PLL3_IO CLK_MCH_BCLK_R
RP3 C3A to D3A
33 VDD_SRC_IO_1 CPU1 58 1 2 shortpad CLK_MCH_BCLK <5>
43 57 CLK_MCH_BCLK#_R 3 4
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# <5>
52 VDD_SRC_IO_3
56 VDD_CPU_IO SRC8/ITP 54 CLK_PCIE_MINI1 <22>
SRC8#/ITP# 53 CLK_PCIE_MINI1# <22> WLAN card
<6> CLK_MCH_OE# R117 475/F_4 CLK_MCH_OE#_R 8 41
PCI0/CR#_A SRC10 CLK_PCIE_TV <22>
SRC10# 42 CLK_PCIE_TV# <22> TV card
<14> SATACLKREQ# R120 475/F_4 SATACLKREQ#_R 10 PCI1/CR#_B
SRC11/CR#_H 40 CLK_MXM <17>
R119 33_4 PCLK_DEBUG_R 11 39 MXM card
<22> PCLK_DEBUG PCI2 SRC11#/CR#_G CLK_MXM# <17>
C226 *10p/50V_4
R125 33_4 PCLK_591_R 12 37
<30> PCLK_591 PCI3 SRC9 CLK_PCIE_ICH <13>
C225 *10p/50V_4 38 DMI
SRC9# CLK_PCIE_ICH# <13>
PCLK_PCM_R 13 PCI4/SEL_LCDCLK# WLAN_CLKREQ#_R R144 475/F_4
SRC7/CR#_F 51 WLAN_CLKREQ# <22>
R124 33_4 PCLK_ICH_R 14 50 LAN_CLKREQ#_R R146 LAN@475/F_4 LAN_CLKREQ# <20>
C <13> PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E C
C222 *10p/50V_4
CPU_BSEL0 R137 2.2K_4 FSA 17 48 R146 , 8131L/475 ohm , 8121/floating
USB_48/FSA SRC6 CLK_PCIE_LAN <20>
R141 33_4 47 LAN
<14> CLKUSB_48 SRC6# CLK_PCIE_LAN# <20>
R140 *22_4 CPU_BSEL1 64
<28> CLK_Card48 C238 30p/50V_4 FSB/TEST/MODE
SRC4 34 CLK_PCIE_SATA <12>
SRC2 Register5/Bit7 = 1, Register5/Bit6 = 1 B2A to C3A For EMI FSC 5 35 SATA
A1A to B2A REF0/FSC/TESTSEL SRC4# CLK_PCIE_SATA# <12>
SRC4 Register5/Bit5 = 1, Register5/Bit4 = 1 CPU_BSEL2 R128 10K_4 CG_XIN 3 31
R122 33_4 CG_XOUT XTAL_IN SRC3/CR#_C
<14> 14M_ICH 2 XTAL_OUT SRC3#/CR#_D 32
SRC8 Register3/Bit3 = 0, Register6/Bit6 = 1 C229 *30p/50V_4
For EMI 65 28
Register6/Bit7 = 1, Register3/Bit3 = 0 VSS_BODY SRC2/SATA CLK_PCIE_3GPLL <6>
SRC6 15 VSS_PCI SRC2#/SATA# 29 CLK_PCIE_3GPLL# <6>
18 VSS_48
22 VSS_IO LCDCLK/27M 24 CLK_DREFSSCLK <6>
C220 33p/50V_4 CG_XIN 26 25 Display PLLB
VSS_PLL3 LCDCLK#/27M_SS CLK_DREFSSCLK# <6>
CG_XOUT 59 VSS_CPU
30 VSS_SRC1 SRC0/DOT96 20 CLK_DREFCLK <6>
Y2 36 21 Display PLLA
VSS_SRC2 SRC0#/DOT96# CLK_DREFCLK# <6>
14.318MHz 49 VSS_SRC3
1 VSS_REF CKPWRGD/PWRDWN# 63 CK_PWRGD <14>
C234 33p/50V_4
SLG8SP513VTR

B B




CPU Clock select
Clock Generator Strap table
CPU_BSEL0 R409 0_4
<3> CPU_BSEL0 MCH_BSEL0 <6>
+3V
CPU_BSEL1 R136 0_4
<3> CPU_BSEL1 MCH_BSEL1 <6>
CPU_BSEL2 R121 0_4 Pin 13 : For Pin 20/21 and 24/25 selection
<3> CPU_BSEL2 MCH_BSEL2 <6> 0 = LCDCLK & DOT96 for internal graphic (Setting)
PCLK_PCM_R R130 10K_4
Q8 R106 R105 1 = 27M & 27M_SS &SRC_0 for external graphic
FSC FSB FSA Frequency RHU002N06
2




10K_4 10K_4 Pin 14 : For Pin 53/54 (CPU_ITP or SRC_8) selection
PCLK_ICH_R R123 10K_4 0 = SRC_8 (Setting)
0 0 0 266Mhz 1 = CPU_ITP
3 1 CGDAT_SMB
<14,16,20,22> PDAT_SMB
0 0 1 133Mhz
0 1 1 166Mhz
A +3V A
0 1 0 200Mhz
Q9 C3A to D3A
1 1 0 400Mhz RHU002N06
Quanta Computer Inc.
2




1 1 1 Reserved
3 1 CGCLK_SMB
1 0 1 100Mhz
<14,16,20,22> PCLK_SMB PROJECT : ZK6
Size Document Number Rev
1 0 0 333Mhz 1A
CLOCK GENERATOR
Date: Friday, April 24, 2009 Sheet 2 of 42
5 4 3 2 1
5 4 3 2 1




<5> H_A#[3..16]
U25A
H_A#3 J4 H1
A[3]# ADS# H_ADS# <5>




ADDR GROUP_0
H_A#4 L5 E2 H_D#[0..15] U25B H_D#[32..47]
A[4]# BNR# H_BNR# <5> <5> H_D#[0..15] H_D#[32..47] <5>
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# <5> D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# <5> E26 D[2]# D[34]# V24




DATA GRP 0
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
H_DRDY# <5>




DATA GRP 2
H_A#9 A[8]# DRDY# H_D#4 D[3]# D[35]# H_D#36
J1 A[9]# DBSY# E1 H_DBSY# <5> F23 D[4]# D[36]# V23
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 H_BREQ# <5> E25 D[6]# D[38]# U25
H_A#12 P2 H_D#7 E23 U23 H_D#39
D A[12]# D[7]# D[39]# D




CONTROL
H_A#13 L2 D20 H_IERR# R97 56_4 +1.05V H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
P4 A[14]# INIT# B3 H_INIT# <12> G24 D[9]# D[41]# W22
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# <5> J23 D[11]# D[43]# W24
M1 H_D#12 H22 W25 H_D#44
<5> H_ADSTB#0 ADSTB[0]# D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
<5> H_REQ#[0..4] RESET# H_CPURST# <5> D[13]# D[45]#
H_REQ#0 K3 F3 H_D#14 K22 AA24 H_D#46
REQ[0]# RS[0]# H_RS#0 <5> D[14]# D[46]#
H_REQ#1 H2 F4 H_D#15 H23 AB25 H_D#47
REQ[1]# RS[1]# H_RS#1 <5> D[15]# D[47]#
H_REQ#2 K2 G3 J26 Y26
REQ[2]# RS[2]# H_RS#2 <5> <5> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <5>
H_REQ#3 J3 G2 H26 AA26
REQ[3]# TRDY# H_TRDY# <5> <5> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <5>
H_REQ#4 L1 H25 U22
REQ[4]#