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5 4 3 2 1
%/ &PSGO (MEKVEQ
D
AMD CLOCK GENERATOR D
CPU VCORE DDR2-800MHz Dual Channel DDR2
REV.F SO-DIMM X 2
PAGE 16
Up to 2GB DDRII
PAGE 9 10
LED&SW&TOUCHPAD
LVDS & INV PAGE 5 6 7 8 PAGE 50
H.T 800 MHz
PAGE 22
1600MT/s
MINI-PCIE FAN + SENSOR
CRT PCIE *1
PAGE 21
TV Card
PAGE 23
ATI PCIE *16 ATI PCIE *1
PAGE 40
TV OUT PCIE *1 DISCHARGE CIRCUIT
PAGE 23
M76-M RS690M PCIE *1 PAGE 52
JMB360
DVI e-SATA
PAGE 11 12 13 14
PAGE 49 SYSTEM PWR
PAGE 24
ALINK
C
4LANE MINI PCIE
C
CIR
WLAN BAT & CHARGER
PAGE 37
PAGE 26
SUPER I/O
SIR
ITEIT8712F_IX LPC
PAGE 37
33MHz USB NEW CARD
PAGE 37 ATI USB PAGE 27
Azalia
SB600
EC IT8511E PCI 33MHz
KEYPAD
MATRIX CardBus 1394
PAGE 29 PAGE 17 18 19 20 R5C833 PAGE 39
PAGE 28 29
PAGE 38 MMC/SD
INSTANT KEY USB 4 in 1
Memory
CARD READER
PAGE 50 Stick/MS PRO
PAGE 39
USB 2.0 XD
B LED B
CON X5
PAGE 50 MDC Conn SATA HDD PAGE 36
ISA (RJ11) PCI LAN
ROM (8MB) PAGE 34 PAGE 35
PAGE 29
PAGE 25
Bluetooth
Azalia Codec USB
AMPLIFIER HDD
ALC 660 PAGE 36
PAGE 31
PAGE 30 PAGE 35
Camera
SPEAKER or ODD
MIC AND LINE IN DSP SPDIF USB
PHONE JACK
PAGE 35 PAGE 22
PAGE 31 PAGE 32 PAGE 33 PAGE 31
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Block Diagram 20
Date: 14 2007 Sheet 1 of 69
5 4 3 2 1
P01.BALOCK DIAGRAM PCI DEVICES IRQ TABLE GPIO
P02.TABLE OF CONTENTS
P03.POWER BUDGET DEVICE IDSEL# REQ/GNT# PCI INT CLOCK NB STRP_DATA SEL_VCC_NB TUNE NB VOLTAGE OUTPUT
P04.CLOCK DISTRIBUTION
P05.TURION HT I/F NB VGA N/A N/A A SB RI#EXTEVNT0# KB_SCI# KEYBOARD SCI INPUT
P06.TURION DDR2 MEMORY I/F LPC_PME#/GEVENT3# LPC_PME# PME FROM SIO INPUT
SB AD31(INT) N/A N/A LPC_SMI#/EXTEVNT1# LPC_SMI# SMI FROM EC INPUT
P07.TURION CNTL/DEBUG/THERM
P08.TURION POWER ATA100 AD31 N/A A INT WAKE#/GEVENT8# SB_WAKE# PCI E WAKE INPUT
P09.DDR2_SODIMM GPIO10 BT_DET# BLUETOOTH DETECT INPUT
AC97/AZALIA AD31 N/A B INT GPIO6 BT_LED_EN# BLUETOOTH LED OUTPUT
P10.DDR2_TERMINATIONS
D
USB AD30 N/A D INT GPIO4 802_LED_EN# WIRELESS LAN LED OUTPUT D
P11.RS690M-HT LINK0 I/F GPIO5 CB_HWSUSPEND CARDBUS SUPEND OUTPUT
P12.RS690M-PCIE LINK I/F CARD BUS AD17 0 F,G PCI_CLK0 GPIO8 BT_ON# BLUETOOTH ENABLE(OPTION) OUTPUT
P13.RS690M-SYSTEM I/F&CLKGEN PCI LAN AD18 1 E PCI_CLK1 GPIO0 WLAN_ON# WIRELESS LAN ENABLE OUTPUT
P14.RS690M-POWER LLB#/GPIO66 BAT_LL# BATTERY LOW(OPTION) INPUT
P15.BLANK TEMPIN0 CPU_THRM CPU TEMPERATURE(OPTION)
P16.EXTERNAL CLOCK GENERATOR TEMPIN1 NB_THERM NB TEMPERATURE
P17.SB600-PCIE/PCI/CPU/LPC SMBUS TABLE GPIO11 SB_THRO_CPU CPU OVER TEMP AND SHUT OUTPUT
P18.SB600-ACPI/GPIO/USB/AC97/AZA GPIO12 TV_ON# TV ENABLE OUTPUT
SOURCE SIGNAL NAME LINKED DEVICES GPIO64 PM_THERM# THERM ALERT FROM EC INPUT
P19.SB600-SATA/IDE/HWM/SPI
P20.SB600-POWER&DECOUPLING NB DAC_SCL/DAC_SDAT CRT/LVDS
P21.THERMAL FAN CONTROL
P22.LVDS AND INVERTER I2C_CLK/I2C_DATA LVDS
P23.CRT AND TV CONNECTOR I2C_CLK/DDC_DATA DVI EC ECSMI#/GPM0 EXSMI# SMI TO SB OUTPUT
P24.DVI ECSCI#/GPD3 EXT_SCI# SCI TO SB OUTPUT
SB SCLK0/SDATA0 SO-DIMMs/CLK_GEN/DSP SM0 SM_BAT SMBUS TO BATTERY
P25.PCI LAN
SCLK1/SDATA1 MINI-PCIE(WLAN)/NEW CARD/MINI-PCIE(TV) SM1 SMB1 SMBUS TO THERMAL
P26.MINI PCI-E WLAN ADC0/GPK0 BATO_AD BATTERY VOLTAGE INPUT
P27.NEW CARD EC SMCLK0/SMDAT0 BATTERY ADC2/GPK2 AC_AD AC ADAPTER VOLTAGE INPUT
P28.EC IT8510TE(1/2) SMCLK1/SMDAT1 THERMAL(CPU:98H GPU:4CH) GPK4 KID0 KEYBOARD ID0 INPUT
P29.EC IT8510TE(2/2)-ISA ROM GPK5 KID1 KEYBOARD ID1 INPUT
P30.ALC660 DAC0/GPJ0 FAN_DA FAN CONTROL(OPTION) OUTPUT
P31.AMP AND HEADPHONE DAC2/GPJ2 BRIGHT_PWM LCD BRIGHT CONTROL OUTPUT
C P32.MIC AND LINE IN PWR_SW# GPJ3 BATSEL_2P# 2P BATTERY INPUT C
P33.DSP PWM1/GPA1 FAN_PWM FAN CONTROL OUTPUT
GPA4 CHG_LED_UP# CHARGE LED OUTPUT
P34.MDC
GPA5 PWR_LED_UP# POWER LED OUTPUT
P35.HDD AND ODD PM_PWRBTN# GPA6 BATSEL_3S# 3S BATTERY INPUT
P36.USB CONNECTOR AND BT GPA7 BACK_OFF# LCD BACK OFF OUTPUT
P37.SIO AND SIR GPB0 NUM_LED NUM LOCK LED OUTPUT
P38.CARD BUS R5C832 GPB1 CAP_LED CAP LOCK LED OUTPUT
P39.1394 AND CARD READER PM_SUSB# GPB7 THRO_CPU CPU OVER TEMP AND SHUT OUTPUT
P40.MINI PCI-E(TV) PM_SUSC# GPC0 DJ_LED# AUDIO DJ LED OUTPUT
P41.M76(1/5)PCI-E I/F GPC3 EMAIL_LED# EMAIL LED OUTPUT
P42.M76(2/5)DVI&DAC&DDC&PLL&VID GPC4 ACIN_OC# ADAPTER IN INPUT
SUSB_ON GPC5 OP_SD# AUDIO SHUTDOWN OUTPUT
P43.M76(3/5)MEMORY I/F
P44.M76(4/5)BLANK
SUSC_ON GPC6 BAT_IN_OC# BATTERY IN INPUT
GPC7 EC_IDE_RST# EC CONTROL IDE RST OUTPUT
P45.M76(5/5)POWER RI1#/WUI0/GPD0 PM_SUSB# SB SUSB# IN INPUT
P46.GDDR2 MEMORY(1/2) +3VSUS
RI2#/WUI1/GPD1 PM_SUSC# SB SUSC# IN INPUT
P47.GDDR2 MEMORY(2/2) GPD4 RF_OFF_SW# RF SWITCH OFF INPUT
T1
P48.BLANK GPD6 FAN0_TACH FAN TACH INPUT
P49.BLANK +1.2VSUS GPE0 EMAIL_SW# EMAIL SWITCH INPUT
P50.FUNCTION KEY GPE1 NTERNET# INTERNET SWITCH INPUT
P51.POWER SEQUENCE T2>20ms GPE2 MARATHON# POWER GEAR INPUT
GPE3 DISTP_SW# DISABLE TOUCHPAD INPUT
P52.DISCHARGE PM_RSMRST# PWRSE/GPE4 PWRSW#_EC POWER SWITCH INPUT
T2A<50ms GPE6 LID_EC# LID STATUS IN INPUT
B B
GPE7 BT_ON# BLUETOOTH ENABLE OUTPUT
PS2CLK2/GPF4 TPAD_CLK TOUCHPAD CLK
V5_REF PS2DAT2/GPF5 TPAD_DAT TOUCHPAD DATA
GPF6 PWRLMT# POWER LIMIT OUTPUT
T3 GPF7 DJSW# DJ SWITCH INPUT
GPG4 THRM_CPU ALERT FROM THERMAL IC INPUT
+3VS GPG6 PMTHERM# THERM ALERT TO SB OUTPUT
GPG7 AC_APR_UC# ADAPTER POWER OK INPUT
T4 GPH0 VSUS_ON ENABLE VSUS POWER OUTPUT
+1.2VS GPH1 VSUS_GD_EC# VSUS OK INPUT
GPH2 MVPOK# CPU POWER OK INPUT
GPH3 PM_PWRBTN# PWRBTN TO SB OUTPUT
T5
GPH4 SUSC_ON SUSC ON OUTPUT
+VCORE GPH5 SUSB_ON SUSB_ON OUTPUT
GPH6 CPU_VRON ENABLE VCORE OUTPUT
GPH7 PM_RSMRST# SB RSUMRESET OUTPUT
GPI1 WATCH_DOG# WATCH_DOG CONTROL FAN OUTPUT
VDDC_NB GPI3 CHG_EN# ENABLE CHARGE OUTPUT
GPI4 PRECHG BATTERY PRECHARGE OUTPUT
T6>15ms GPI5 BAT_LL# BATTERY LOW OUTPUT
GPI6 BAT_LEARN BATTERY LEARN OUTPUT
NB_PWRGD T7=0
T7A
SB_PWRGD
A
TBD A
CPU_PWROK
SIO PME# LCP_PME# PME TO SB OUTPUT
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Table of Contents 20
Date: 14 2007 Sheet 2 of 69
5 4 3 2 1
A7K POWER ON SEQUENCE BLOCK 10
47~66ms
11
A/D_DOCK_IN
+5VLCM
+2.5VREF 2
PWRSW#_EC Power On
D SWITCH D
1 AMD S1g1 CPU
AC_BAT_SYS +3VA_EC
+3VA
+3VA_EC
EC
8
+5VAO
CPU_VRON
VSUS_ON
IT8511TE
3
+1.2VSUS
+3VSUS 4 13
+5VSUS
VSUS_GD_EC#
5 16
6
C +0.9V 12 C
+1.8V PM_SUSC# SUSC_EC#
+3V CPU_PWROK
+5V
+12V EC
+1.2VS
15
+1.5VS LDT_RESET#
PM_SUSC# SUSB_EC1#
+1.8VS
+2.5VS
+3VS
SB600
+5VS
+12VS
7 RS690M
8 (South Bridge) HT_CPU_STOP#
B CPU_VRON From B
EC
11 (North Bridge)
+VCORE
(MAX8760ETL)
9 PWRGD
CPUPWR_GD
To EC
13
A_RST#
HTVDD_EN
+1.2VS_HT
14
10 PCIRST# PCI Device
VLDT_PWRGD (RICOH R5C833)
A A
SYS PWRGD
11 13
PWRGD Logic PWRGD
PCIE, LPC Device Title : A7K
A_RST#
(Minicard, ASUSTECH CO LTD Engineer: Endy Zhang
Newcard, PCIE LAN, Size Project Name Rev
LPC devices) Custom Power Budget 20
Date: 14 2007 Sheet 3 of 69
5 4 3 2 1
D D
HTREFCLK
66MHZ
ATI NB - RS690M PCI_CLK_CB
24.576MHZ XTAL INPUT
R5C833
NB_OSC 33MHZ
14.318MHZ
TOP SO-DIMM BOT SO-DIMM
PCI_CLK_LAN
33MHZ PCI LAN
HTTCLK0 FS2
NBGFX_CLK_P
SRCLKT1
NBGFX_CLK_N ATI SB
100MHZ LPC_CLK_EC 32.768KHZ XTAL INPUT
EC IT8511E
NBLINK_CLKP SB600 33MHZ TPAD_CLK
NBLINK_CLKN TOUCHPAD
SRCLKT6
100MHZ
CPU_CLK_H
TURION S1g1 CPU CPU_CLK_L GFX_CLK_P LPC_CLK_DEBUG
GFX_CLK_N
200MHZ SRCLKT4 M76-M 33MHZ NEWCARD FOR DEBUG
LGA638 PACKAGE 100MHZ
(CLKREQ#B)
C C
GPP0_CLK_P LPC_CLK_SIO
GPP0_CLK_N
SRCLKT2 MINI PCIE TV 33MHZ SUPER IO
100MHZ
SIO_CLK IT8712F
48MHZ
GPP3_CLK_P
GPP3_CLK_N
SRCLKT7 E-SATA
100MHZ
CODEC_BCLK
ALC660
GPP1_CLK_P
SRCLKT3 GPP1_CLK_N
(CLKREQ#A) 100MHZ MINI PCI-E WLAN
GPP2_CLK_P MDC_BCLK
GPP2_CLK_N
SRCLKT0 MDC
100MHZ NEW CARD
(CLKREQ#C)
SBLINK_CLKP
SBLINK_CLKN
SRCLKT5
100MHZ
B B
FS0 CLK_14M_SB
14.318MHZ
48MHZ_0 CLK_48M_USB
48MHZ
SIO_CLK
48MHZ_1
48MHZ
14.31818MHz
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Clock Distribution 20
Date: 14 2007 Sheet 4 of 69
5 4 3 2 1
D D
U500A
HT_CPU_TX_CLK_H1 J5 Y4 HT_CPU_RX_CLK_H1
11 HT_CPU_TX_CLK_H1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CPU_RX_CLK_H1 11
HT_CPU_TX_CLK_L1 K5 Y3 HT_CPU_RX_CLK_L1
11 HT_CPU_TX_CLK_L1 L0_CLKIN_L1 L0_CLKOUT_L1 HT_CPU_RX_CLK_L1 11
+1 2VS_HT HT_CPU_TX_CLK_H0 J3 Y1 HT_CPU_RX_CLK_H0
11 HT_CPU_TX_CLK_H0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CPU_RX_CLK_H0 11
HT_CPU_TX_CLK_L0 J2 W1 HT_CPU_RX_CLK_L0
11 HT_CPU_TX_CLK_L0 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CPU_RX_CLK_L0 11
R500 1 2 49 9Ohm HT_CPU_TX_CTL_H1 P3 T5
R501 1 HT_CPU_TX_CTL_L1 L0_CTLIN_H1 L0_CTLOUT_H1
2 49 9Ohm P4
L0_CTLIN_L1 L0_CTLOUT_L1
R5
HT_CPU_TX_CTL_H0 N1 R2 HT_CPU_RX_CTL_H0
11 HT_CPU_TX_CTL_H0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CPU_RX_CTL_H0 11
HT_CPU_TX_CTL_L0 P1 R3 HT_CPU_RX_CTL_L0
11 HT_CPU_TX_CTL_L0 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CPU_RX_CTL_L0 11
HT_CPU_TX_CAD_H15 N5 T4 HT_CPU_RX_CAD_H15
HT_CPU_TX_CAD_L15 L0_CAD N_H15 L0_CADOUT_H15 HT_CPU_RX_CAD_L15
LAYOUT: PLACE NEAR CPU P5
L0_CAD N_L15 L0_CADOUT_L15
T3
HT_CPU_TX_CAD_H14 M3 V5 HT_CPU_RX_CAD_H14
STUFF WHEN CONFIGURED AS HT_CPU_TX_CAD_L14 M4
L0_CAD N_H14 L0_CADOUT_H14
U5 HT_CPU_RX_CAD_L14
16-BIT LINK HT_CPU_TX_CAD_H13 L0_CAD N_L14 L0_CADOUT_L14 HT_CPU_RX_CAD_H13
L5 V4 HT_CPU_RX_CAD_L[0 15] 11
HT_CPU_TX_CAD_L13 L0_CAD N_H13 L0_CADOUT_H13 HT_CPU_RX_CAD_L13
M5 V3
HT_CPU_TX_CAD_H12 L0_CAD N_L13 L0_CADOUT_L13 HT_CPU_RX_CAD_H12
K3 Y5
HT_CPU_TX_CAD_L12 L0_CAD N_H12 L0_CADOUT_H12 HT_CPU_RX_CAD_L12
K4 W5 HT_CPU_RX_CAD_H[0 15] 11
HT_CPU_TX_CAD_H11 L0_CAD N_L12 L0_CADOUT_L12 HT_CPU_RX_CAD_H11
H3 AB5
HT_CPU_TX_CAD_L11 L0_CAD N_H11 L0_CADOUT_H11 HT_CPU_RX_CAD_L11
H4 AA5
HT_CPU_TX_CAD_H10 L0_CAD N_L11 L0_CADOUT_L11 HT_CPU_RX_CAD_H10
G5 AB4
HT_CPU_TX_CAD_L10 L0_CAD N_H10 L0_CADOUT_H10 HT_CPU_RX_CAD_L10
H5 AB3
HT_CPU_TX_CAD_H9 L0_CAD N_L10 L0_CADOUT_L10 HT_CPU_RX_CAD_H9
11 HT_CPU_TX_CAD_L[0 15] F3 AD5
HT_CPU_TX_CAD_L9 L0_CAD N_H9 L0_CADOUT_H9 HT_CPU_RX_CAD_L9
F4 AC5
HT_CPU_TX_CAD_H8 L0_CAD N_L9 L0_CADOUT_L9 HT_CPU_RX_CAD_H8
E5 AD4
C HT_CPU_TX_CAD_L8 L0_CAD N_H8 L0_CADOUT_H8 HT_CPU_RX_CAD_L8 C
11 HT_CPU_TX_CAD_H[0 15] F5 AD3
L0_CAD N_L8 L0_CADOUT_L8
HYPERTRANSPORT
HT_CPU_TX_CAD_H7 N3 T1 HT_CPU_RX_CAD_H7
HT_CPU_TX_CAD_L7 L0_CAD N_H7 L0_CADOUT_H7 HT_CPU_RX_CAD_L7
N2 R1
HT_CPU_TX_CAD_H6 L0_CAD N_L7 L0_CADOUT_L7 HT_CPU_RX_CAD_H6
L1 U2
HT_CPU_TX_CAD_L6 L0_CAD N_H6 L0_CADOUT_H6 HT_CPU_RX_CAD_L6
M1 U3
HT_CPU_TX_CAD_H5 L0_CAD N_L6 L0_CADOUT_L6 HT_CPU_RX_CAD_H5
L3 V1
HT_CPU_TX_CAD_L5 L0_CAD N_H5 L0_CADOUT_H5 HT_CPU_RX_CAD_L5
L2 U1
HT_CPU_TX_CAD_H4 L0_CAD N_L5 L0_CADOUT_L5 HT_CPU_RX_CAD_H4
J1 W2
HT_CPU_TX_CAD_L4 L0_CAD N_H4 L0_CADOUT_H4 HT_CPU_RX_CAD_L4
K1 W3
HT_CPU_TX_CAD_H3 L0_CAD N_L4 L0_CADOUT_L4 HT_CPU_RX_CAD_H3
G1 AA2
HT_CPU_TX_CAD_L3 L0_CAD N_H3 L0_CADOUT_H3 HT_CPU_RX_CAD_L3
H1 AA3
HT_CPU_TX_CAD_H2 L0_CAD N_L3 L0_CADOUT_L3 HT_CPU_RX_CAD_H2
G3 AB1
HT_CPU_TX_CAD_L2 L0_CAD N_H2 L0_CADOUT_H2 HT_CPU_RX_CAD_L2
G2 AA1
HT_CPU_TX_CAD_H1 L0_CAD N_L2 L0_CADOUT_L2 HT_CPU_RX_CAD_H1
E1 AC2
HT_CPU_TX_CAD_L1 L0_CAD N_H1 L0_CADOUT_H1 HT_CPU_RX_CAD_L1
F1 AC3
HT_CPU_TX_CAD_H0 L0_CAD N_L1 L0_CADOUT_L1 HT_CPU_RX_CAD_H0
E3 L0_CAD N_H0 L0_CADOUT_H0 AD1
HT_CPU_TX_CAD_L0 E2 AC1 HT_CPU_RX_CAD_L0
L0_CAD N_L0 L0_CADOUT_L0
SOCKET638
Do not cross plane.
U500E
A1 A26
P20 H16 T5021 N/A TPC28T
RSVD_MA0_CLK_H3 RSVD_MA_RESET_L T503 N/A TPC28T
P19 B18
B RSVD_MA0_CLK_L3 RSVD_MB_RESET_L B
N20
RSVD_MA0_CLK_H0
N19 B3
RSVD_MA0_CLK_L0 RSVD_V DSTRB1
C1
RSVD_V DSTRB0
RSVD_VDDNB_FB_H
H6 TURION S1g1
G6
RSVD_VDDNB_FB_L
RSVD_CORE_TYPE
D5 uPGA638
MISC
NTERNAL FREE5
R24
W18
Top View
FREE6
R26 R23
RSVD_MB0_CLK_H3 FREE4
R25 AA8
RSVD_MB0_CLK_L3 FREE1
P22 H18
RSVD_MB0_CLK_H0 FREE2
R22 RSVD_MB0_CLK_L0 FREE3 H19
AF1
SOCKET638
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Turion HT I/F 20
Date: 14 2007 Sheet 5 of 69
5 4 3 2 1
MEM_MA0_CLK_H2 MEM_MB0_CLK_H2
9 MEM_MA0_CLK_H2 9 MEM_MB0_CLK_H2
C600 C601
MEM_MA0_CLK_L2 the cap close to cpu less than 1200mil MEM_MB0_CLK_L2
9 MEM_MA0_CLK_L2 9 MEM_MB0_CLK_L2
1 5PF/50V