Text preview for : jet_way_j694tas_r1.0_schematics.pdf part of Jetway jet way j694tas r1.0 schematics . Rare and Ancient Equipment Jetway Motherboards Материнская плата JetWay J694TAS jet_way_j694tas_r1.0_schematics.pdf
Back to : jet_way_j694tas_r1.0_sche | Home
4 3 2 1
JET WAY INFORMATION
MODEL:694TAS REV: 1.0 (SOCKET 370+VT82C694T+VT82C686B+AGP 4X+1 AMR)
D D
TITLE SHEET
COVER SHEET 1
SOCKET 370 PROCESSOR 2
NORTH BRIDGE (VT82C694T) 3,4
SOUTH BRIDGE (VT82C686B) 5,6
USB2,3 & FREQUENCY RATIO 7
C C
SDRAM 8,9
PCI SLOTS 10,11,12
AGP SLOT 13
ISA PULL UP RESISTANCE 14
IDE & PANEL 15
CLOCK SYNTHESIZER 16
BYPASS CAPACITORS 17
B B
DC-DC CONVERTER 18 |LINK
| 2.SCH
| 3.SCH
PRINTER / COM PORT 17 | 4.SCH
| 5.SCH
| 6.SCH
| 7.SCH
AUDIO CODEC & AUDIO PORT & JOSTICK PORT 20 | 8.SCH
| 9.SCH
| 10.SCH
| 11.SCH
AMR SLOT 21 | 12.SCH
| 13.SCH
| 14.SCH
| 15.SCH
ATX POWER CONNECTOR / VTT TERMINATOR / VCC3 22 | 16.SCH
| 17.SCH
| 18.SCH
| 19.SCH
| 20.SCH
| 21.SCH
| 22.SCH
A A
JETWAY INFORMATION
Title
COVER SHEET
Size Document Number Rev
J-694TAS REV:1.0 0.1
Date: Tuesday, May 07, 2002 Sheet 1 of 23
4 3 2 1
4 3 2 1
VTT
23 AF36
23 VTTGD D[0..63]
D[0..63] 3,22
R286 R287
AF36
AN3
AK4
U35
S33
S37
1K 1K
A[3..31] CPU -SMI C52 NC-56p
3,22 A[3..31] A3 D0
AK8 W1
GND/DYN_OE
GND/VTTPWRGD
VSS/NC
VTT
VTT
VTT
A4 A3 D0 D1 -STPCLK C49
AH12 T4 NC-56p
A5 A4 D1 D2
AH8 A5 D2 N1
A6 AN9 M6 D3 -SLP C51 NC-56p
A7 A6 D3 D4
AL15 A7 D4 U1
A8 AH10 S3 D5 -CPUINIT C50 NC-56p
A9 A8 D5 D6
AL9 A9 D6 T6
A10 AH6 J1 D7 INTR C44 NC-56p
D BSEL0 A11 A10 D7 D8 D
AK10 S1
BSEL1 Jumper function A12
A13
AN5
AL7
A11
A12
A13
SOCKET 370 D8
D9
D10
P6
Q3
D9
D10
-FERR C37 NC-56p
A14 AK14 GND VCCP VCC_1.5V VCC_CMOS M4 D11 -IGNNE C38 NC-56p
Short Bus freq. auto A15 A14 D11 D12
AL5 A15 D12 Q1
Short detected by CPU. A16 AN7 A37 D34 AA5 F2 AD36 AB36 L1 D13 -A20M C48 NC-56p
A17 A16 AB32 E7 AA37 F4 D13 D14
AE1 A17 D14 N3
A18 Z6 AC5 E11 F14 U3 D15
Open Test 66/100 MHz CPU A19 A18 AC33 E15 AB34 F22 D15 D16
AG3 A19 D16 H4
Short run 100/133 MHz. A20 AC3 AD2 E19 AD32 F26 R4 D17
A21 A20 AD34 F20 AE5 F30 D17 D18 VTT
AJ1 A21 D18 P4
A22 AE3 AF32 F24 AF2 F34 H6 D19
Short Test 100 MHz CPU A23 A22 F28 AF34 H32 D19 D20 Place 0603 Package
AB6 A23 D20 L3
Open run 133 MHz. A24 AB4 AG5 F32 AH24 H36 G1 D21 R80 C152,C153 near AB36
A25 A24 AH2 F36 AH32 J5 D21 D22 PIN
AF6 A25 D22 F8
A26 Y3 AH34 G5 AH36 K2 G3 D23 75 1%
A27 A26 H2 AJ5 K32 D23 D24
AA1 A27 D24 K6
A28 AK6 AJ7 H34 AJ9 K34 E3 D25 CPUVREF
A29 A28 AJ11 K36 AJ13 M32 D25 D26
Z4 A29 D26 E1
A30 AA3 AJ15 L5 AJ17 N5 F12 D27 R82 C81 C88 C89 C87
A31 A30 AJ19 M2 AJ21 P2 D27 D28
AD4 A31 D28 A5
AJ23 M34 AJ25 P34 A3 D29 150 1% 0.1u 0.1u 0.1u 0.1u
-ADS AJ27 P32 AJ29 R32 D29 D30
3,22 -ADS AN31 ADS D30 J3
-DRDY AN27 GTL P36 AK2 R36 C5 D31
3,22 -DRDY -DBSY DRDY AL1 Q5 AK34 S5 D31 D32
3,22 -DBSY AL27 DBSY D32 F6
-HTRDY AN25 AL3 R34 AM4 T2 C1 D33 Use 0603 Packages and
3,22 -HTRDY TRDY AM6 T32 AM8 T34 D33 D34 distribute within 500
3,22 -HREQ[0..4] D34 C7
-HREQ0 AK18 AM10 T36 AM12 V32 B2 D35 mils of CPUVREF inputs
-HREQ1 REQ[0] AM14 U5 AM16 V36 D35 D36 (1 cap for every 2 inputs)
C AH16 REQ[1] D36 C9 C
-HREQ2 AH18 AM18 V2 AM20 W5 A9 D37
-HREQ3 REQ[2] AM22 V34 AM24 D37 D38
AL19 REQ[3] D38 D8
-HREQ4 AL17 AM26 X32 AM28 Y35 D10 D39
-BREQ0 REQ[4] AM30 X36 AM32 Z32 D39 D40
3,22 -BREQ0 AN29 BR0 D40 C15
-BPRI AN17 AM34 Y5 B6 D14 D41 VCC2_5
3,22 -BPRI -BNR BPRI Y37 B10 D41 D42
3,22 -BNR AH14 BNR D42 D12
-HLOCK AK20 B4 Z2 B14 A7 D43
3,22 -HLOCK LOCK B8 Z34 B18 D43 D44
D44 A11
-HIT AL25 B12 B22 C11 D45 R25
3,22 -HIT -HITM HIT B16 B26 D45 D46
3,22 -HITM AL23 HITM D46 A21 150 1%
-DEFER AN19 B20 B30 A15 D47
3,22 -DEFER DEFER B24 B34 D47 D48 CLKREF
D48 A17
-RS0 AH26 B28 C3 C13 D49
3,22 -RS[0..2] -RS1 RS[0] B32 D6 D49 D50
AH22 RS[1] D50 C25
-RS2 AK28 D2 D20 A13 D51 C26 C71 R24
RS[2] D4 D24 D51 D52
D52 D16
C35 D18 D28 A23 D53 10u 0.1u 150 1%
-CPURST BPM[0] D22 D32 D53 D54
3,22 -CPURST E35 BPM[1] D54 C21
G33 D26 D36 C19 D55
VCC_CMOS BP[2] D30 E5 D55 D56 VCC3
E37 BP[3] D56 C27
E9 A19 D57
R288 1K E13 D57 D58
X4 RESET D58 C23
AH4 E17 C17 D59
R52 330 NC/RESET* D59 D60
J37 PREQ CMOS I/O D60 A25
R60 220 A35 GTL A27 D61
PRDY D61 D62 C45 R47
D62 E25
-FERR AC35 F16 D63 NC-330
5 -FERR -IGNNE FERR D63
B AG37 NC-18p B
7 -IGNNE -A20M IGNNE *:Intel Old/New
7 -A20M AE33 A20M BCLK W37 CPUCLK 16
AJ3 CMOS I/O **:cyrix AK30
R53 470 GND/NC **BSEL1 -BSEL0
J35 PICD[0] BSEL0 AJ33 1 2 100_-66 16
R54 470 L35 AK26 VCCP_GD
PICD[1] PWRGOOD VCCP_GD 22
APICLK1 J33 AJ31 1 BSEL0
23 APICLK 1 PICCLK BSEL1 133_-100
U37 VTT THERMDP AL31 2 133_-100 16
INTR M36 BSEL0,BSEL1: AL29 3 BSEL1
7 INTR NMI INTR/LINT[0] Cyrix:Input THERMDN VCCP_GD
7 NMI L37 NMI/LINT[1]
-SMI AJ35 Intel:Output C37 VCC_CMOS
5 -SMI -STPCLK SMI CMOS I/O CPUPRES R289
5 -STPCLK AG35 STPCLK EDGCTRL AG1 AG1
-SLP AH30 AH28 R78 330 1.8K
R49 330 5 -SLP -FLUSH AE37
SLP THERMTRIP
AL35 VID0 CB13
FLUSH VID[0] VID0 18
-CPUINIT AG33 AM36 VID1 0.1u VCCP
5 -CPUINIT INIT VID[1] VID1 18
AE35 AL37 VID2
IERR VID[2] VID2 18
R50 330 E33 AJ37 VID3
VREF0 VID[3] VID3 18
F18 AK36 VID4
VREF1 **VID[4] VID4 18
K4 AL33 TCK RN8 1 2 330 8P4R
CPUVREF VREF2 TCK TDI L10
R6 VREF3 TDI AN35 3 4
V6 AN37 TDO 5 6 VCC_CMOS 4.7uH
C46 C16 C86 VREF4 TDO TMS
AD6 VREF5 TMS AK32 7 8
VTT AK12 AN33 -TRST
0.1u 0.1u AK22 AK22 VREF6 TRST R57 680 C77
0.1u VREF7 PLL1 W33 C76
VCC_CMOS AD36 U33
VCC_1.5V PLL2
VCC2_5 Z36 VCC_2.5V RSRVD48 E21 R79 330
VCC_CMOS
22u 22u
AB36 VCC_CMOS RSRVD49 E27 SLEWCTRL 22
AH20 S35 SMD 1206
NC/VTT* RSRVD51 RTTCTRL 22
AK16 AN11 VTT C80
R290 NC/VTT* *NC/VTT
AL13 NC/VTT* *NC/VTT AN15
A 75_1% A
AL21 NC/VTT* *NC/VTT G35
W35 Y33 CLKREF 0.1u
C132 C42 NC/PU** *GND/CLKREF
C47 AM2 G37
GND/NC* VTT
X34 VTT
E23 VTT
AN21VTT
AA35VTT
N37 NCHCTRL VTT AA33
AK22 0.1u 0.1u 0.1u JET WAY INFORMATION
SOCKET 370T_1
R292 VCC_CMOS R291 R55 C131 Title
150_1% C280 14 NMI 1 2 SOCKET 370 PROCESSOR
0.1U VCC_CMOS
C35 C22
NC-2.7K JP2 0.1u Size Document Number Rev
0.1u 1u B 1.0
J-694TAS REV:1.0