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Morar Block Diagram 2005/05/28
A B C D E




Mobile CPU G792 Project Code:91.4E101.001 SYSTEM DC/DC
CLK GEN.
4
19
PCB:05210-SB TPS5130 35,36
4

IDT CV125 Dothan INPUTS OUTPUTS
3 4, 5 3D3V_S5
5V_S5

HOST BUS 400MHz
RGB CRT DCBATOUT
1D05V_S0
CONN 14 2D5V_S0(LDO)
DDR II 400MHz
LCD SYSTEM DC/DC
400 MHz Intel 910GML XGA/WXGA ISL6227 37
11,12 LVDS
13 INPUTS OUTPUTS
DDR II 400MHz DCBATOUT
5V_S5

400 MHz 6,7,8,9,10 3D3V_S3

11,12
TPS51100DGQ 37
DMI I/F 100MHz DDR_VREF
3 5V_S5 3
DDR_VREF_S3

Line In27 ACLINK ENE
Codec PCI BUS CB1410 PWR SW CHARGER
PCMCIA ISL6255
ALC655 CP2211 38
Int. 26 25
24,25
ONE SLOT
MIC In 27 25
INPUTS OUTPUTS


DCBATOUT
BT+
ICH6-M Mini-PCI 16.8V 3A
Line Out OP AMP 802.11 B/G 28
27
G1421B 27 LAN
10/100
RTL8110CL
TXFM RJ4523 CPU DC/DC
23 ISL6218CV-T
22, 23
2 34 2

INT.SPKR MODEM
27 INPUTS OUTPUTS
MDC Card
21 VCC_CORE
LPC BUS DCBATOUT
0.844~1.3V
27A
15,16,17,18
Xbus BIOS ROM
PATA




KBC 4M BITS
ENE KB3910 PM39LV040-70JCE

USB 29 31
4 PORT
HDD CD ROM 21
20 20
1 1

MINI USB 21 Touch INT_KB Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Blue-tooth Pad 30 30 Taipei Hsien 221, Taiwan, R.O.C.

Title
BLOCK DIAGRAM
Size Document Number Rev
Custom
MORAR SB
Date: Thursday, June 09, 2005 Sheet 1 of 40

A B C D E
A B C D E
Alviso Strapping Signals ICH6-M Integrated Pull-up
and Configuration page 7 and Pull-down Resistors ICH6-M EDS 14308 0.8V1
Pin Name Strap Description Configuration
ACZ_BIT_CLK, DPRSLP#, EE_DIN,
CFG[2:0] FSB Frequency Select 000 = Reserved
001 = FSB533 EE_DOUT, GNT[5]#/GPO[17],
010 = FSB800 ICH6 internal 20K pull-ups
011-111 = Reversed GNT[6]#/GPO[16], LDRQ[1]/GPI[41],
4 CFG[3:4] Reversed LAD[3:0]#/FB[3:0]#, LDRQ[0],
4
CFG5 DMI x2 Select 0 = DMI x2 PME#, PWRBTN#, TP[3]
1 = DMI x4 (Default)
0 = DDR II
CFG6 DDR I / DDR II 1 = DDR I LAN_RXD[2:0] ICH6 internal 10K pull-ups
CFG7 CPU Strap 0 = Prescott
1 = Dothan (Default) ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ICH6 internal 20K pull-downs
CFG[8:11] Reversed ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR,
CFG[12:13] XOR/ALL Z test 00 = Reserved SPKR, EE_CS,
straps 01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation USB[7:0][P,N] ICH6 internal 15K pull-downs
(Default)
CFG[14:15] Reversed DD[7], SDDREQ ICH6 internal 11.5K pull-downs
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled LAN_CLK ICH6 internal 100K pull-downs
(Default)
CFG17 Reversed
CFG18 CPU core VCC 0 = 1.05V (Default)
Select 1 = 1.5V
3 CFG19 CPU VTT Select 0 = 1.05V (Default)
ICH6-M IDE Integrated Series 3
1 = 1.2V
CFG20 Reversed
PCI Routing Termination Resistors
DD[15:0], DIOW#, DIOR#, DREQ,
SDVOCRTL SDVO Present 0 = No SDVO device present IDSEL IRQ REQ/GNT approximately 33 ohm
_DATA (Default) DDACK#, IORDY, DA[2:0], DCS1#,
1= SDVO device present
7411 25 B.F.G 0 DCS3#, IDEIRQ
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.
MiniPCI 21 F 1
LAN 23 E 2




2 2




1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Memo
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 2 of 40
3D3V_S0 3D3V_S0 3D3V_S0
R191 R166 R155
1 2 3D3V_APWR_S0 1 2 3D3V_48MPWR_S0 1 2 3D3V_CLKGEN_S0
1 0R3-U




1




1




1




1




1




1




1




1




1




1




1




1




1




1
0R3-U 0R3-U
C201 C203 C215 C192 C191 C190 C200 C202 C214 C216 C217 C189 C193 C194 C188
SCD1U16V SC4D7U10V5ZY SCD1U16V SCD1U16V SC4D7U6D3V3KX SCD1U16V SCD1U16V SC10U10V5ZY-L SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2




2




2




2




2




2




2




2




2




2




2




2




2




2




2
DREFSSCLK1 2 3 DREFSSCLK 7
DREFSSCLK#1 1 4 DREFSSCLK# 7

RN16
SRN33-2-U2



U13

R222 1 2 33R2 56 17
28 PCLK_MINI R175 33R2 PCI0 LVDS
22 PCLK_LAN 1 2 3 PCI1 LVDS# 18
R174 1 2 22R2 4
24 PCLK_PCM R173 33R2 PCI2
29 PCLK_KBC 1 2 5 PCI3 SRC1 19
H/L: 100/96MHz SRC1# 20
SS_SEL 9 22
R172 PCIF1/SEL100/96# SRC2
16 CLK_ICHPCI 1 2 33R2 ITP_EN 8 PCIF0/ITP_EN SRC2# 23
3D3V_S0
H/L : CPU_ITP/SRC7 SRC3 24
16 PM_STPPCI# 55 PCI_STOP# SRC3# 25
26 RN20 1 4 SRN33-2-U2 CLK_PCIE_ICH 16
SRC4
SRC4# 27 2 3 CLK_PCIE_ICH# 16
1




46 31 CLK_PCIE_ICH1
R151 11,18 SMBC_ICH SCL SRC5 CLK_PCIE_ICH#1 RN21
11,18 SMBD_ICH 47 SDA SRC5# 30 1 4 SRN33-2-U2 CLK_MCH_3GPLL 7
10KR2 33 CLK_MCH_3GPLL1 2 3
SRC6 CLK_MCH_3GPLL# 7
RN17 SRN33-2-U2 32 CLK_MCH_3GPLL#1
SRC6#
3 2 14
2




7 DREFCLK DOT96 CLK_XDP_CPU1 RN22
7 DREFCLK# 4 1 15 DOT96# CPU2_ITP/SRC7 36 1 4 SRN33-2-U2 CLK_XDP_CPU 4
Morar_SB VTT_PWRGD# 35 CLK_XDP_CPU#1 2 3 CLK_XDP_CPU# 4
CPU2_ITP#/SRC7#
C205 50 44 CLK_CPU_BCLK1 RN24 1 4 SRN33-2-U2 CLK_CPU_BCLK 4
XTAL_IN CPU0 CLK_CPU_BCLK#1
Q14 1 2 49 43 2 3 CLK_CPU_BCLK# 4
XTAL_OUT CPU0#
3 OUT 2 26 CLK_Audio
R218 1 2 33R2 CPU1 41 CLK_MCH_BCLK1
2 R1 SC33P50V2JN R217 1 2 33R2 40 CLK_MCH_BCLK#1 RN23 1 4 SRN33-2-U2
32,34 6218_PGOOD 16 CLK_ICH14 CPU1# CLK_MCH_BCLK 6
IN 1 GND 52 REF 2 3 CLK_MCH_BCLK# 6
R2 X1 R212 1 2 475R2F 39 54
IREF CPU_STOP# PM_STPCPU# 16,34
DTC124EKA C204 X-14D31818M-1 53 CPU_SEL0
1



FSC/TEST_SEL CPU_SEL1
1 2 FSB/TEST_MODE 16
VTT_PWRGD# 10 12 FS_A R163 2 1 22R2
SC33P50V2JN VTT_PWRGD#/PD USB48/FSA CLK48_ICH 16
CLK_ICH14 & CLK14_SIO
2 34 3D3V_CLKGEN_S0
3D3V_S0 need equal length 6
VSS_PCI VDD_SRC
21
VSS_PCI VDD_SRC
51 VSS_REF VDD_PCI 7
45 VSS_CPU VDD_PCI 1
1




1




38 VSSA
R167 R168 13 48
10KR2 10KR2 VSS48 VDD_REF
29 VSS_SRC VDD_CPU 42
IN EN OUT 37 3D3V_APWR_S0
VDDA 3D3V_48MPWR_S0
(3D3V_S0) (6218_PGOOD) (VTT_PWRGD#) 11
2




2




VDD48
VDD_SRC 28
H L H ITP_EN
SS_SEL
X H Hi - Z
1




1




IDTCV125PA
DY R169 R170 DY
10KR2 10KR2 EMI capacitor
2




2




CLK_ICH14 EC111 SC10P50V2JN-1
DY
3D3V_CLKGEN_S0 1D05V_S0

CLK_CPU_BCLK R216 1 2 49D9R2F
1



1




1




R159 R221 CLK_CPU_BCLK# R215 1 2 49D9R2F PCLK_PCM EC93 SC10P50V2JN-1
R162 DY
DUMMY-R2




DUMMY-R2




1KR2 CLK_PCIE_ICH R206 1 2 49D9R2F CLK_MCH_BCLK R214 1 2 49D9R2F PCLK_MINI EC113 SC10P50V2JN-1
DY
CLK_PCIE_ICH# R205 1 2 49D9R2F CLK_MCH_BCLK# R213 1 2 49D9R2F PCLK_KBC EC92 SC10P50V2JN-1
DY
2



2




2




FS_A DREFSSCLK# R156 1 2 49D9R2F CLK_ICHPCI EC91 SC10P50V2JN-1
CLK_MCH_3GPLL R209 1 2 49D9R2F DY
DREFSSCLK R157 1 2 49D9R2F CLK48_ICH EC90 SC10P50V2JN-1
CPU_SEL1 7
CLK_MCH_3GPLL# R207 1 2 49D9R2F DY
CPU_SEL0 4,7 DREFCLK R161 1 2 49D9R2F
CLK_XDP_CPU R211 1 2 49D9R2F
1



1




1




R165 R158 R220 DREFCLK# R160 1 2 49D9R2F
FS_C FS_B FS_A CPU CLK_XDP_CPU# R210 1 2 49D9R2F
DUMMY-R2



DUMMY-R2




DUMMY-R2




0 0 0 266M
0 0 1 133M
0 1 0 200M Wistron Corporation
2



2




2




0 1 1 166M 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1 0 0 333M Taipei Hsien 221, Taiwan, R.O.C.
1 0 1 100M
1 1 0 400M Title
1 1 1 Reserved
Clock Generator - IDT125
Size Document Number Rev
A3
MORAR SB
Date: Friday, June 24, 2005 Sheet 3 of 40
A B C D E




ADDR GROUP 0
U35A TP6
BGA479-SKT-2-U
TPAD28 1D05V_S0
4 H_A#3 P4 N2 4
6 H_A#[31..3] A3# ADS# H_ADS# 6
H_A#4 U4 L1
A4# BNR# H_BNR# 6
H_A#5 V3 J3 H_BPRI# 6
A5# BPRI#




1
H_A#6 R3
H_A#7 A6# R362
V2 A7# DEFER# L4 H_DEFER# 6
H_A#8 W1 H2 56R2J
A8# DRDY# H_DRDY# 6
H_A#9 T4 M2
A9# DBSY# H_DBSY# 6
H_A#10 W2




2
H_A#11 A10# Place testpoint on
Y4 A11# BR0# N4 H_BREQ#0 6
H_A#12 Y1 H_IERR# with a GND




CONTROL
H_A#13 A12# H_IERR# 0.1" away
U1 A13# IERR# A4
H_A#14 AA3 B5 H_INIT# 15
H_A#15 A14# INIT#