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5 4 3 2 1
(S)JM11_MS (ZH7) BLOCK DIAGRAM
PCB STACK UP
8L HDI POWER
XTAL
CLOCK SYSTEM 5V/3V
D LAYER 1 : TOP D
Y2 CK505 (QFN-64) RT8206B P24
LAYER 2 : GND 14.318MHZ
PG2
LAYER 3 : IN1 CPU Core
LAYER 4 : VCC ISL6261A P25
FAN & THERMAL
LAYER 5 : IN2
P3 DDR Power
LAYER 6 : IN3
CPU RT8207A P26
LAYER 7 : GND
LAYER 8 : BOT Penryn SFF ULV DC/SC VCCP 1.05V
RT8202A P27
Micro-FCBGA956/10W P3,4
1.5V
800/1066 MHz FSB G9334/AO4466 P28
LVDS LED Panel 1.5V_S5
DDR2-SODIMM cahnge A NORTH BRIDGE Connector P22 RT9025 P28
C C
P15 VGA CRT Discharge
667/800MHZ DDR II
Cantiga SFF GS45 Connector P21 P28
DDR2-SODIMM cahnge B
TMDS HDMI Level Shifter HDMI GFX
P16 P22 Connector P22 ISL6263A P29
PG 5,6,7,8,9,10
DMI x 4
PCIE4 MINI CARD 1
2.5HDD SATA0 SOUTH BRIDGE Connector P19
P20
PCIE PCIE5 MINI CARD 2 SIM CARD
On Board USB0 Port 6
Connector P19 Connector P19
P20
B PCIE1 Connector GLAN XTAL B
MINI CARD 1 Port 7 Y2
ICH9-M SFF P21 Atheros AR8131L 25MHZ
P19
MINI CARD 2 Port 2 IHDA Line Out/MIC Connector
P21
P19 CODEC
Speaker Speaker Connector
CCD Port 4 USB Realtek ALC269X
P21
P22
Digital MIC LED Panel
Bule Tooth Port 5 PG 11,12,13,14 XTAL P17 Connector P22
P21 Y4
32.768KHZ
LPC
Port 0
On Board USB2
Connector
EC
Port 1 8x16 Keyboard
On Board USB3 Winbond WPCE775LA0DG
Connector P21
A
XTAL P18 A
Card Reader Port 3
Y1
12MHZ Alcor AU6433 P21 XTAL
Y3
SPI PS/2 QUANTA
32.768KHZ
Title
COMPUTER
FLASH TouchPAD
Schematic Block Diagram
2Mbytes Connector Size Document Number Rev
P18 P21 ZH7 1A
Date: Tuesday, June 16, 2009 Sheet 1 of 31
5 4 3 2 1
5 4 3 2 1
+3V +3V
Clock Generator (CLK)
Q9 Q10
R133 R132
N-2N7002E N-2N7002E
2
2
4.7K_4 4.7K_4
[15,16] SMBDT1 1 3 PDAT_SMB PDAT_SMB [13,19] [15,16] SMBCK1 1 3 PCLK_SMB PCLK_SMB [13,19]
D D
+3V
U9
L18 PBY160808T-301Y-N/2A/300ohm_6 +3V_VDD_CLK 9 55
VDD_PCI NC
16 VDD_48
C234 C217 C215 C231 C224 SMBCK1 +3V
23 VDD_PLL3 CK505 SCLK 7
SMBDT1
4 VDD_REF SDA 6
10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 QFN PM_STPPCI# R167 2.2K_4
46 45 PM_STPPCI# PM_STPPCI# [13] PM_STPCPU# R173 2.2K_4
+1.05V VDD_SRC SRC5/PCI_STOP# PM_STPCPU#
62 VDD_CPU SRC5#/CPU_STOP# 44 PM_STPCPU# [13]
L17 PBY160808T-301Y-N/2A/300ohm_6 +1.05V_VDD_CLK 19 61 CLK_CPU_BCLK CLK_CPU_BCLK [3]
VDD_96_IO CPU0 CLK_CPU_BCLK#
27 VDD_PLL3_IO CPU0# 60 CLK_CPU_BCLK# [3]
C237 C223 C229 C236 C235 C226 33 VDD_SRC_IO_1 CLK_MCH_BCLK
52 VDD_SRC_IO_3 CPU1 58 CLK_MCH_BCLK [5]
10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 43 57 CLK_MCH_BCLK# CLK_MCH_BCLK# [5]
VDD_SRC_IO_2 CPU1#
56 VDD_CPU_IO
SRC8/ITP 54
SRC8#/ITP# 53
[13] CLKREQ#_SATA CLKREQ#_SATA R136 475/F_4 CR#_A 8 41 PECLK_3GPLL PECLK_3GPLL [6]
PCI0/CR#_A SRC10 PECLK_3GPLL#
SRC10# 42 PECLK_3GPLL# [6]
[21] CLKREQ#_LAN CLKREQ#_LAN R145 475/F_4 CR#_B 10
C PCI1/CR#_B CR#_H R168 475/F_4 CLKREQ#_MCH C
SRC11/CR#_H 40 CLKREQ#_MCH [6]
[19] PCLK_DEBUG PCLK_DEBUG 11 39 CR#_G R170 475/F_4 CLKREQ#_MINI1 CLKREQ#_MINI1 [19]
PCI2/TME SRC11#/CR#_G
12 37 PECLK_MINI1 PECLK_MINI1 [19]
PCI3 SRC9 PECLK_MINI1#
SRC9# 38 PECLK_MINI1# [19]
[18] PCICLK_EC PCICLK_EC R139 33_4 PCICLK_EC_R 13 PCI4/LCDCLK_SEL
SRC7/CR#_F 51
[12] PCLK_ICH PCLK_ICH R148 33_4 PCLK_ICH_R 14 50 CR#_E R165 3G@475/F_4 CLKREQ#_MINI2 [19]
PCIF5/ITP_EN SRC7#/CR#_E
No Stuff R162 FOR EMI CG_XIN 3 48 PECLK_MINI2 PECLK_MINI2 [19]
XTAL_IN SRC6 PECLK_MINI2#
SRC6# 47 PECLK_MINI2# [19]
[21] CLK48_CARD CLK48_CARD R162 *22_4 CG_XOUT 2 XTAL_OUT PECLK_LAN
SRC4 34 PECLK_LAN [21]
[13] CLK48_ICH CLK48_ICH R160 22_4 CLK48_ICH_R 17 35 PECLK_LAN# PECLK_LAN# [21]
USB_48/FSA SRC4#
FSB 64 31 PECLK_ICH PECLK_ICH [12]
FSB/TEST/MODE SRC3/CR#_C PECLK_ICH#
SRC3#/CR#_D 32 PECLK_ICH# [12]
[13] CLK14_ICH CLK14_ICH R149 33_4 CLK14_ICH_R 5 REF0/FSC/TESTSEL PECLK_SATA
65 VSS_BODY SRC2/SATA 28 PECLK_SATA [11]
15 29 PECLK_SATA# PECLK_SATA# [11]
VSS_PCI SRC2#/SATA#
REV: B change R183 & R184 to 27P 18 VSS_48
22 24 DREFSSCLK DREFSSCLK [6]
VSS_IO SRC1/SE1 DREFSSCLK#
26 VSS_PLL3 SRC1#/SE2 25 DREFSSCLK# [6]
B 59 B
C183 27P/50V_4 CG_XIN VSS_CPU DREFCLK
30 VSS_SRC1 SRC0/DOT96 20 DREFCLK [6]
36 21 DREFCLK# +3V
VSS_SRC2 SRC0#/DOT96# DREFCLK# [6]
2
Y2 49 VSS_SRC3 VR_PWRGD_CK410 CR#_A R137 10K_4
1 VSS_REF CKPWRGD/PWRDWN# 63 VR_PWRGD_CK410 [13]
CR#_B R150 10K_4
14.318MHZ SLG8SP513 CR#_E R166 3G@10K_4
1
C197 27P/50V_4 CG_XOUT CR#_G R171 10K_4
CR#_H R169 10K_4
Clock Request Table
+3V CLKREQ# MAPPING Control
REV: B Change R161 to short pad PCLK_ICH C206 *33p/50V_4 0 1
R146 10K_4 PCLK_DEBUG PCICLK_EC C205 *33p/50V_4 CR#_A SRC0 SRC2 SATA
R153 2.2K_4 CLK48_ICH_R CLK48_ICH C216 *33p/50V_4 CR#_B LCDCLK SRC4 LAN
[3] CPU_BSEL0 CPU_BSEL0 R144 1K_4 MCH_BSEL0 MCH_BSEL0 [6] CLK48_CARD C222 *33p/50V_4 CR#_C SRC0 SRC2 N/A
CLK14_ICH C182 *33p/50V_4 CR#_D LCDCLK SRC4 N/A
R163 *Short_4 FSB R138 10K_4 PCICLK_EC_R CR#_E SRC6 MINI2
[3] CPU_BSEL1 CPU_BSEL1 R161 1K_4 MCH_BSEL1 MCH_BSEL1 [6] CR#_F SRC8 N/A
CR#_G SRC9 MINI1
R135 10K_4 CLK14_ICH_R CR#_H SRC10 MCH
[3] CPU_BSEL2 CPU_BSEL2 R131 1K_4 MCH_BSEL2 MCH_BSEL2 [6] ITP_EN Pin 53/54
0 SRC_8/SRC_8#
1 ITP/ITP#
A
FSC FSB FSA CPU
(MHz)
SRC
(MHz)
PCI
(MHz)
REF
(MHz)
DOT96
(MHz)
USB
(MHz)
QUANTA A
0
0
0
0
0
1
0
1
0
266.6
133.3
200.0
100.0
100.0
100.0
33.3
33.3
33.3
14.318
14.318
14.318
96.0
96.0
96.0
48.0
48.0
48.0
R147 10K_4 PCLK_ICH_R
Title
COMPUTER
0 1 1 166.6 100.0 33.3 14.318 96.0 48.0
1 0 0 333.3 100.0 33.3 14.318 96.0 48.0 CLOCK GENERATOR CK505
1 0 1 100.0 100.0 33.3 14.318 96.0 48.0 LCDCLK_SEL Pin 20/21 Pin 24/25 Size Document Number Rev
1 1 0 400.0 100.0 33.3 14.318 96.0 48.0 0 DOT_96/DOT96# LCDCLK/LCDCLK#
1 1 1 Reserved 1 SRC_0/SRC_0# 27M/27M_SS ZH7 1A
Date: Tuesday, June 16, 2009 Sheet 2 of 31
5 4 3 2 1
1 2 3 4 5 6 7 8
Penryn SFF - Host Bus (CPU)
H_A#[3..16] U18A H_D#[0..15] U18B H_D#[32..47]
[5] H_A#[3..16] [5] H_D#[0..15] H_D#[32..47] [5]
H_A#3 P2 M4 H_D#0 F40 AP44 H_D#32
A[3]# ADS# H_ADS# [5] D[0]# D[32]#
H_A#4 V4 J5 H_D#1 G43 AR43 H_D#33
A[4]# BNR# H_BNR# [5] D[1]# D[33]#
H_A#5 W1 L5 H_D#2 E43 AH40 H_D#34
A[5]# BPRI# H_BPRI# [5] D[2]# D[34]#
1.2G AJSLGAMVT02 H_A#6 T4 H_D#3 J43 AF40 H_D#35
A[6]# D[3]# D[35]#
ADDR GROUP 0
DATA GROUP 0
H_A#7 AA1 N5 H_D#4 H40 AJ43 H_D#36
A[7]# DEFER# H_DEFER# [5] D[4]# D[36]#
H_A#8 AB4 F38 H_D#5 H44 AG41 H_D#37
A[8]# DRDY# H_DRDY# [5] D[5]# D[37]#
DATA GROUP 2
H_A#9 T2 J1 H_D#6 G39 AF44 H_D#38
A[9]# DBSY# H_DBSY# [5] D[6]# D[38]#
H_A#10 AC5 H_D#7 E41 AH44 H_D#39
A[10]# D[7]# D[39]#
CONTROL
H_A#11 AD2 M2 H_D#8 L41 AM44 H_D#40
A[11]# BR0# H_BR0# [5] D[8]# D[40]#
1.4G AJSLGFMTT00 H_A#12 AD4 H_D#9 K44 AN43 H_D#41
H_A#13 A[12]# H_IERR# H_D#10 D[9]# D[41]# H_D#42
A AA5 A[13]# IERR# B40 N41 D[10]# D[42]# AM40 A
H_A#14 AE5 D8 H_D#11 T40 AK40 H_D#43
A[14]# INIT# H_INIT# [11] D[11]# D[43]#
H_A#15 AB2 H_D#12 M40 AG43 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
AC1 A[16]# LOCK# N1 H_LOCK# [5] G41 D[13]# D[45]# AP40
Y4 H_D#14 M44 AN41 H_D#46
[5] H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[14]# D[46]#
G5 H_D#15 L43 AL41 H_D#47
[5] H_REQ#[0..4] RESET# H_RESET# [5] D[15]# D[47]#
H_REQ#0 R1 K2 K40 AK44
REQ[0]# RS[0]# H_RS#0 [5] [5] H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 [5]
H_REQ#1 R5 H4 J41 AL43
REQ[1]# RS[1]# H_RS#1 [5] [5] H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 [5]
H_REQ#2 U1 K4 P40 AJ41
REQ[2]# RS[2]# H_RS#2 [5] [5] H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 [5]
H_REQ#3 P4 L1
REQ[3]# TRDY# H_TRDY# [5] H_D#[16..31] H_D#[48..63]
H_REQ#4 W5
H_A#[17..35] REQ[4]# [5] H_D#[16..31] H_D#[48..63] [5]
H2 H_D#16 P44 AV38 H_D#48
[5] H_A#[17..35] HIT# H_HIT# [5] D[16]# D[48]#
H_A#17 AN1 F2 H_D#17 V40 AT44 H_D#49
A[17]# HITM# H_HITM# [5] D[17]# D[49]#
H_A#18 AK4 H_D#18 V44 AV40 H_D#50
H_A#19 A[18]# H_D#19 D[18]# D[50]# H_D#51
AG1 A[19]# BPM[0]# AY8 AB44 D[19]# D[51]# AU41
ADDR GROUP 1
H_A#20 AT4 BA7 H_D#20 R41 AW41 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
DATA GROUP 1
H_A#21 AK2 BA5 H_D#21 W41 AR41 H_D#53
A[21]# BPM[2]# D[21]# D[53]#
DATA GROUP 3
H_A#22 AT2 AY2 H_D#22 N43 B