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8 7 6 5 4 3 2 1
Rev Description Date
IO 0 : X
IO 1 : X
IO 2 : MELODY_INT
IO 3 : X
IO 4 : X
IO 5 : X
IO 6 : ACCESSORY_IN
S570 IO
IO
IO
IO
IO
7 : NRESET_OUT
8 : DSC_HW_ID
9 : NLED_DRIVE_SD
10 : 2.5V LDO_EN
11 : X
C IO 12 : X C
IO 13 : BSY/RDY
nCS0 : NROM_CS0
nCS1 : NRAM_CS1
nCS2 : NDSCM_CS2
nCS3 : NLCDM_CS3
nCS4 : NMELODY_CS4
B B
ADIN1: LCDM_HW_ID
ADIN2: BATEMP
ADIN3: EARPHONE_IN
ADIN4: HS_TMP
A A
8 7 6 5 4 3 2 1
A B C D E
6 RXD
R:100~149 6 TXD TMS
TP100 TP101 TP102 TP103 VRRTC1(1.8V,1.4V)==>VDDS-RTC,VDD-RTC
C:100~149 TDO
TCK
VRIO1,2(2.8V)==>VDDS-1,VDDS-2,VDDANG
1
1
1
1
VRIO
1
1
2 1 TDI
TP104 TP105 R108 VRIO VRABB(2.8V)==>VRABB
RN102
1 8 BGND 100K
2 7
3 6 DSR
2
4 5
R109
100K (8P4R)
RXD2
4 100K 4
nCS0 : NROM_CS0 TXD2
1
nCS1 : NRAM_CS1
nCS2 : NDSCM_CS2 4,8,9 D[0..15]
nCS3 : NLCDM_CS3
D15
D14
D13
D12
D11
D10
VRDBB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R102 100K C100 33pF
nCS4 : NMELODY_CS4 VRMEM
NMELODY_CS4 8
2 1 2 1
1
2
TCXOEN 10 R107 X100 BGND
DNI DST520
BGND
1 TPL100
1
C10
D10
C11
D11
A10
B10
E10
A11
B11
A12
B12
A13
2
1 2
D4
C4
D5
C5
C6
D6
D7
C7
C8
D8
D9
C9
A2
B3
A3
B4
A4
E5
B5
A5
E6
A6
B6
E7
A7
B7
B8
A8
E8
B9
A9
E9
U100 C101 18pF
B2 B13
VDD
VDD
RX_IRDA
RFEN/NOPC
TDI
VSS
VSS
TX_IRDA
nBSCAN
SD_IRDA/CLKOUT_DSP
VSS
TCK
VDDS-MIF
VDDS-MIF
TCXOEN
VDDS-2
TX_MODEM/XIOSTRBN
RX_MODEM
CTS_MODEM/XF
TMS
DSR_MODEM/LPG
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
nCS4(C035)
RXIR_IRDA/X_A1
TDO
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
TXIR_IRDA/X_A4
nEMU1
nEMU0
RTS_MODEM/TOUT
4,8,9 R N W RnW OSC32K_OUT
C2 A14
4 NROM_CS0 nCS0 VSSO
C3 C13
4 NRAM_CS1 nCS1 OSC32K_IN
B1 C12
C1 VSS CLK32K_OUT B14 CLK32K_OUT 3
4 NDSCM_CS2 D3 nCS2 IT_WAKEUP C14 RTCINT 3
4 NLCDM_CS3 A22D 2 nCS3/INT4N VSSRTC D12
CS4/ADD22 RESPWRONZ NRESET 3
D1 D13
4,8,9 A[0..22] VRMEM F5 VDDS-MIF VDDS-RTC D14
4 NBHE nBHE/IO14 VDDRTC VRRTC
E4 F10
4 NBLE nBLE/IO15 ON_OFF ON_OFF 3
E2 E11
3
4,8 NFOE
E3 nFOE/X_A3 VDDANG E13 VRIO 1 2 3
2
nFWE/X_A0 CLKTCXO BBCLK 10 C105
E1 E12
F4 VDD VSSANG E14 VRDBB C103 C102 470pF 1uF
4 FDP A0 F3 FDP/NIACK VSSPLL F11 2 1
JP100: 1,2 = ADD0 VDDPLL
1
A1 F2 F12
100k (security ) F1 ADD1 CLK13M_0UT/START_BIT F13
CLK13M 3
VSS SIM_CLK S_CLK 3 BGND
JP100: 2, 3 = 0 A2 G5 F14
SIM_PCTL/IO5 3 1uF BGND
A3 G4 ADD2 SIM_PWRCTRL/IO5 G10
ohm(non-security) A4 G2 ADD3 SIM_RST G11 S_RST 3 2 1
A5 G3 ADD4 SIM_CD/MAS0 G13 VRIO
ADD5 SIM_IO S_IO 3
VRIO G1
VDDS-MIF TSPEN3/NSCS2
G12 R104 100K
JP100 A7
A8
A6 H 1
H3
H2
ADD6
ADD7
HERCROM400G2 VSS
TSPEN2
G14
H14
H12
SIM_CD
SMADA
9
3
1 ADD8 TSPEN1 BGND
100K A9 H4 H13 SJ101
2 ADD9 TSPEN0 TPEN0 3
A10 H5 H11 2 1 short jump
3 ADD10 TSPDO DATA 10
A11 J1 H10
A12 J2 ADD11 TSPDI/IO4 J14 2 1
J3 ADD12 TSPCLKX J13 CLK 10
A13
A14 J4 ADD13 TSPACT11/MCLK J12
BGND LE 10 short jump
K1 ADD14 TSPACT10/NWAIT J11 SJ102
VSS TSPACT9/MAS1 BS 10
A15 K3 K14
A16 K2 ADD15 TSPACT8/NMREQ K12
TP106 K4 ADD16 TSPACT7/CLKX_SPI K13
A17
A18 J5 ADD17 TSPACT6/NCS6 K11 TX_ON 10
1 A19 L1 ADD18 TSPACT5/DPLLCLK J10
A20 L2 ADD19 TSPACT4/NREADYMEN L14
A21 L3 ADD20 VDDS-1 L13 VRIO
PCS_RX 10
MCSI_FSYNCH/IO12
M1 ADD21/CK16X_IRDA TSPACT3 L12
N1 VDD TSPACT2 M14 DCS_T/R 10
BCLKR/ARMCLK
MCSI_RXD/IO10
MCSI_CLK/IO11
2 nlBOOT TSPACT1 GSM_T/R 10 2
MCSI_TXD/IO9
IO0/TPU-WAIT
MCUEN2/IO13
IO1/TPU-IDLE
M3 N14
IO3/SIM_RNW
MCUEN1/IO8
3 EXTIRQ
KBC2/XDIO0
KBC3/XDIO1
KBC4/XDIO2
KBR0/XDIO3
KBR1/XDIO4
KBR2/XDIO5
KBR3/XDIO6
KBR4/XDIO7
nSCS1/X_A2
SDO/INT10n
EXT_IRQ VDD
SCLK/INT1n
M2 M12
nSCS0/SCL
BCLKX/IO6
KBC1/NIRQ
KBC0/NFIQ
IDDQ TSPACT0
IO2/IRQ4
P1 M13
MCUEN0
VCLKRX
SDI/SDA
VDDS-1
BU/PWT
MCUDO
LT/PWL
3 EXTFIQ EXT_FIQ VFSRX VFSRX 3
MCUDI
N2 P14
BFSR
BFSX
nRESET_OUT/IO7 VDX VDX 3
2
VDD
BDR
VDR
BDX
VSS
VSS
VSS
VSS
VSS
8,9 NRSTOUT/IO7 R 1 1 3
R106 1K
M10
M11
N10
N11
N12
N13
P10
K10
P11
P12
P13
L10
L11
M4
M5
M6
M7
M8
M9
47K
L4
L5
L6
L7
L8
L9
N3
N4
N5
N6
N7
N8
N9
P2