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5 4 3 2 1
Cathedral Peak II Block Diagram
Project code: 91.4K801.001
PCB P/N : 48.4K801.0SB
REVISION : 08219-SB
SYSTEM DC/DC
TPS51125 35
D
CLK GEN. Mobile CPU PCB STACKUP D
ICS 9LPRS365BKLFT (71.09365.A03)
Penryn 479 THERMAL EMC2102 INPUTS OUTPUTS
RTM 875N-606-LFT (71.00875.C03) 21 TOP
3
5V_S5
4, 5 VCC DCBATOUT
3D3V_S5
HOST BUS 667/800/[email protected] CRT S
15
DDR2 DIMM1 S
SYSTEM DC/DC
667/800 MHz 667/800MHz LCD
Cantiga 14
GND TPS51124 37
12 AGTL+ CPU I/F BOTTOM INPUTS OUTPUTS
DDR Memory I/F
DDR2 DIMM2 INTEGRATED GRAHPICS DCBATOUT
1D05V_S0
1D8V_S3
667/800 MHz 667/800MHz LVDS, CRT I/F
13 6,7,8,9,10,11 RT9026 36
DDR_VREF_S0
C X4 DMI 1D8V_S3 C
INT.MIC C-Link0
16
400MHz DDR_VREF_S3
RT9018A 36
Codec
ICH9M 1D8V_S3 1D5V_S0
AZALIA 6 PCIe ports LAN
ALC268 PCIex1 TXFM RJ45
PCI/PCI BRIDGE Giga LAN 26 26
28 88E8071 25 CFXCORE DC/DC
ACPI 2.0 ISL6263 38
MIC In 4 SATA
New card PWR SW INPUTS OUTPUTS
29 12 USB 2.0/1.1 ports PCIex1
27 TPS2231 27
ETHERNET (10/100/1000MbE) VGFXCORE
PCIex1 DCBATOUT
High Definition Audio 0.7~1.25V
Mini Card
LPC I/F Kedron a/b/g/n 27
29 OP AMP Serial Peripheral I/F CPU DC/DC
APA2057
29 Matrix Storage Technology(DO) ISL6266A 34
B
LPC BUS B
INT.SPKR Active Managemnet Technology(DO)
INPUTS OUTPUTS
BIOS
Winbond VCC_CORE_S0
29
KBC W25X16 LPC DCBATOUT
0.35~1.5V
16M Bits 31
Line Out ENE3310 DEBUG
CONN.31
(NO SPDIF) 30 CHARGER
17,18,19,20 Launch
MODEM BQ24745 39
USB Buttom
RJ11 MDC Card 16
INPUTS OUTPUTS
23 Touch INT.
Blue Tooth Camera
Pad 30 KB 30 BT+
(USB) 23 (USB) 14
SATA DCBATOUT
DCBATOUT
HDD SATA
CardReader MS/MS Pro/xD
USB USB Realtek /MMC/SD
22
3 Port 23 RTS5158E 5 in 1 24
A 24 A
ODD SATA Wistron Corporation
22 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SATA Taipei Hsien 221, Taiwan, R.O.C.
Title
Launch Board
LED Board BLOCK DIAGRAM
Size Document Number Rev
A3
16 Cathedral Peak II SB
Date: Friday, June 20, 2008 Sheet 1 of 43
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Rev.1.5 page 92 Hub strapping configuration
ICH9 EDS 642879 and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for nativeCFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
SMBus
EMC2102 Thermal
USB Table KBC
USB
BAT_SCL
Pair Device BATTERY
PCIE Routing 0 USB1
LANE1 LAN MARVELL 88E8071
1 NC
LANE2 MiniCard WLAN
2 USB2
LANE3 NC
3 NC
LANE4 NC
4 USB3
LANE5 NewCard
5 Bluetooth
LANE6 NC
1 6 NC ICH9M 1
7 MINIC1
Wistron Corporation
8 WEBCAM 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
9 NEW1
Title
10 Card Reader SMBC_ICH 9LPRS365BKLFT
Reference
11 NC Size Document Number Rev
A3
DDR Cathedral Peak II SB
Date: Friday, June 20, 2008 Sheet 2 of 43
A B C D E
3D3V_S0 3D3V_S0
3D3V_S0
1 R146 2 3D3V_48MPWR_S0 3D3V_CLKPLL_S0 1 R197 2 3D3V_CLKGEN_S0 1 R157 2
0R0603-PAD 0R0603-PAD 0R0603-PAD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C190 C183 EC58 C463 C235 C459 C465 C231 C462 C246 C195 C214 C453 C198 C234 C184
SC1U16V3ZY-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY DY DY DY DY
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY DY
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4 4
3D3V_CLKGEN_S0
PCLK_ICH CLK_ICH14
CLK48_ICH 3D3V_CLKPLL_S0
1
1
1
EC57 EC55
SC5P50V2CN-2GP EC137 3D3V_48MPWR_S0 SC5P50V2CN-2GP
2
2
DY SC5P50V2CN-2GP DY
2
DY
16
46
62
23
19
27
43
52
33
56
4
9
U19
SB CL=20pF