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PAMS Technical Documentation Schematics / Layouts 8270 NSD-5
BB-RF Interface
BB RF_DCT3
VR1 VR1
VR1 VR1
VR2 VR2
VR2 VR2
VR3 VR3
VR3 VR3
VR4 VR4
VR4 VR4
VR5 VR5
VR5 VR5
VR7 VR7
VR7 VR7
5V 5V
5V 5V
BVOLT BVOLT
BVOLT BVOLT
RXIQ(3:0) RXIQ(3:0)
RXIQ(3:0) RXIQ(3:0)
TXIQ(3:0) TXIQ(3:0)
TXIQ(3:0) TXIQ(3:0)
TIF_EN TIF_EN
TIF_EN TIF_EN
RIF_EN RIF_EN
RIF_EN RIF_EN
CAFE_TX_GATE CAFE_TX_GATE CAFE_TX_GATE
CAFE_TX_GATE
TX_LIM_ADJ TX_LIM_ADJ
TX_LIM_ADJ TX_LIM_ADJ
TX_IF_AGC TX_IF_AGC
TX_IF_AGC TX_IF_AGC
TX_RF_AGC TX_RF_AGC
TX_RF_AGC TX_RF_AGC
TX_LIM TX_LIM
TX_LIM TX_LIM
RF_TX_GATE_P RF_TX_GATE_P
RF_TX_GATE_P RF_TX_GATE_P
RX_IF_AGC RX_IF_AGC
RX_IF_AGC RX_IF_AGC
RX_GS RX_GS
RX_GS RX_GS
FILT_SEL_P FILT_SEL_P
FILT_SEL_P FILT_SEL_P
FILT_SEL_N FILT_SEL_N
FILT_SEL_N FILT_SEL_N
AFC AFC
AFC AFC
SYN_CLK SYN_CLK
SYN_CLK SYN_CLK
SYN_LE1 SYN_LE1
SYN_LE1 SYN_LE1
SYN_DAT SYN_DAT
SYN_DAT SYN_DAT
CLK19M2RF CLK19M2RF
CLK19M2RF CLK19M2RF
PA_TEMP PA_TEMP
PA_TEMP PA_TEMP
Issue 1 05/02 Nokia Corporation Page A-1
PAMS Technical Documentation Schematics / Layouts 8270 NSD-5
Circuit Diagram of Baseband
FBUS / MBUS CONNECTOR X052
FBUS_TX 1 FBUS_TX
FBUS_RX 2 FBUS_RX
MBUS 3 MBUS
XEAR 4 XEAR
SGND 5 SGND
J55 MBUS XMICP 6 XMIC
J56 FBUS_RX L_GND 7 L_GND
J57 FBUS_TX 8 CHRG_CTRL
J58 V_IN 9 VIN
E060
E061
E062
VPP_FLASH 10
CAFE WDDIS 11
VPP
WDDIS
HF_MUTE HF_MUTE
HF_MUTE HF_MUTE
RESETX
RESETX RESETX
RESETX
FLASH CONNECTOR
CLK_EN CLK_EN
CLK_EN CLK_EN
EAD_HEADINT
EAD_HEADINT PARTS PLACED ON PANEL
HOOKINT HOOKINT
HOOKINT HOOKINT
CAFE_TX_GATE CAFE_TX_GATE
CAFE_TX_GATE CAFE_TX_GATE
XEAR
XEAR
CAFESIO(2:0) CAFESIO(2:0) SGND
CAFESIO(2:0) CAFESIO(2:0) SGND VPP_FLASH
TXD(7:0) TXD(7:0) XMICP
TXD(7:0) TXD(7:0) XMICP
RXD(11:0) RXD(11:0) XMICN
RXD(11:0) RXD(11:0) XMICN
IQSEL IQSEL WDDIS VR1
IQSEL IQSEL WD_DIS VR1 VR1
TXIQ(3:0)
TXIQ(3:0)
RXIQ(3:0) EAD EAD VR2 VR2
RXIQ(3:0) EAD EAD VR2
SYN_CLK
SYN_CLK SYN_CLK
CLK19M2O CLK19M2O VREF VREF VR3
CLK19M2O CLK19M2O VREF VREF VR3 VR3
SYN_DAT CLK9M83 CLK9M83 VR6 VR6
SYN_DAT SYN_DAT CLK9M83 CLK9M83 VR6 VR6
CLK19M2RF VR1_SW VR1_SW VR4 VR4
CLK19M2RF VR1_SW VR1_SW VR4
SYN_LE1
SYN_LE1 SYN_LE1
VPP_CCONT VR5
VPP_CCONT VR5 VR5
TX_RF_AGC FBUS_TX
V_IN
V_IN CCONT VR7
VR7
VR7
TX_RF_AGC TX_RF_AGC FBUS_TX
FBUS_RX CAFE_TX_GATE 5V
FBUS_RX CAFE_TX_GATE 5V 5V
TX_IF_AGC
TX_IF_AGC TX_IF_AGC
PA_TEMP
PA_TEMP PA_TEMP
TX_LIM
TX_LIM TX_LIM
MBUS CLK_EN
MBUS CLK_EN
TX_LIM_ADJ
TX_LIM_ADJ TX_LIM_ADJ
STOP_CH STOP_CH
STOP_CH STOP_CH
RX_GS
RX_GS RX_GS
SLEEPCLK SLEEPCLK
SLEEPCLK SLEEPCLK
RX_IF_AGC
RX_IF_AGC RX_IF_AGC
VLIM VLIM
VLIM VLIM
FILT_SEL_P
FILT_SEL_P FILT_SEL_P
PURX PURX
PURX PURX
FILT_SEL_N
FILT_SEL_N FILT_SEL_N
CCONT_INT CCONT_INT
CCONT_INT CCONT_INT
RF_TX_GATE_P CCONTCSX CCONTCSX
RF_TX_GATE_P RF_TX_GATE_P CCONTCSX CCONTCSX
AFC UIF_CCONT_SCLK UIF_CCONT_SCLK
AFC AFC UIF_CCONT_SCLK UIF_CCONT_SCLK
UIF_CCONT_SDIO UIF_CCONT_SDIO
UIF_CCONT_SDIO UIF_CCONT_SDIO
TIF_EN
TIF_EN TIF_EN
PWRONX
PWRONX
RIF_EN
RIF_EN RIF_EN
BSI
BSI
BTEMP VMAD
UI BTEMP VMAD VMAD
BVOLT VBB
BVOLT BVOLT VBB VBB
VPP_FLASH
VPP_FLASH
LCD_CD LCD_CD VPP_CCONT
LCD_CD LCD_CD VPP_CCONT
LCD_RESETX LCD_RESETX
LCD_RESETX LCDRSTX
LCD_CS LCD_CS
LCD_CS LCD_CS
MAD4 UIF_CCONT_SDIO
UIF_CCONT_SDIO
UIF_CCONT_SCLK
UIF_CCONT_SCLK BVOLT
BACKLIGHT BACKLIGHT
BACKLIGHT BACKLIGHT
BUZZER BUZZER
BUZZER BUZZER X050
VIBRA VIBRA
VIBRA VIBRA
6 SGND
COL(4:0) COL(4:0) 7 XMICP X051
COL(4:0) COL(4:0)
ROW(5:0) ROW(5:0) PWRONX 9 EAD_HEADINT BVOLT VBATT
ROW(5:0) ROW(5:0) PWRONX
8 XEAR BSI BSI
5 XMICN BTEMP BTEMP
L050 GND
4 L_GND
2 V_IN
33R/100MHz
TXIQ(3:0)
RXIQ(3:0)
SYSTEM CONNECTOR BATTERY CONNECTOR
CLK19M2RF
CAFE_TX_GATE
V050 V051
RSA6.1EN RSA6.1EN
E050
E051
E052
E053
E054
E056
E057
Issue 1 05/02 Nokia Corporation Page A-2
PAMS Technical Documentation Schematics / Layouts 8270 NSD-5
Circuit Diagram of MAD4
LCD_RESETX
D100
MAD4_V14_F741718B
HF_MUTE
LCD_RESETX A2 mdP0GPIO0 mdP1GPO0 E3
BACKLIGHT
HF_MUTE B3 mdP0GPIO1 mdP1GPO1 D1
R131 100R
BACKLIGHT A3 mdP0GPIO2 mdP1GPO2 D2 RIF_EN'
LCD_CS RIF_EN
TP100 LCD_CS C4 mdP0GPIO3 mdP1GPO3 D3
M3 mdP0GPIO4 mdP1GPO4 C1
STOP_CH TIF_EN
TP101 STOP_CH N1 mdP0GPIO5 mdP1GPO6 J4 TIF_EN
R134 10k
J3 mdP0GPIO7
EEPROMSDA TX_LIM_ADJ
TP102 EEPROMSDA A4 mdP2GPIO0 mdGPPDM0 G16
R144 2k2
TP103 EEPROMSCLK C5 mdP2GPIO1 mdGPPDM1 D17
EEPROMSCLK FILT_SEL_P
B5 mdP2GPIO2 mdGPPDM2 D16 TX_LIM_ADJ'
R145 2k2
TP105 LCD_CD A5 mdP2GPIO3 mdGPPDM3 D15 FILT_SEL_P'
LCD_CD FILT_SEL_N
MBUS' H3 mdMCUSDIO mdGPPDM4 B15 FILT_SEL_N'
R135 2k2
mdTXIFAGC A15 TX_IF_AGC'
DATA(15:0) TX_IF_AGC
mdTXRFAGC C14 TX_RF_AGC'
R136 2k2
DATA(0) TP106 T10 mdMemDa0 mdRFTXPGate B14 J130
TX_RF_AGC
DATA(1) O01 P10 mdMemDa1 mdRXGS C2 RX_GS' D130
DATA(2) O02 U11 mdMemDa2 2
R137 560R
DATA(3) O03 T11 mdMemDa3 mdMemAd0 U10 TP131 ADD(0) & 4
DATA(4) O04 R11 mdMemDa4 mdMemAd1 T9 ADD(1) 1
DATA(5) O05 P11 mdMemDa5 mdMemAd2 R9 ADD(2) 3= GND5= VBB
R133 10R
DATA(6) O06 U12 mdMemDa6 mdMemAd3 U9 ADD(3) TC7S00F
RF_TX_GATE_P
DATA(7) O07 T12 mdMemDa7 mdMemAd4 T8 ADD(4)
R146 1k0
DATA(8) U13 mdMemDa8 mdMemAd5 R8 ADD(5)
SLEEPCLK RX_GS
DATA(9) T13 mdMemDa9 mdMemAd6 P8 ADD(6)
DATA(10) R13 mdMemDa10 mdMemAd7 U8 ADD(7)
CCONT_INT
DATA(11) U14 mdMemDa11 mdMemAd8 T7 O08 ADD(8)
DATA(12) T14 mdMemDa12 mdMemAd9 R7 O09 ADD(9)
PURX
DATA(13) U15 mdMemDa13 mdMemAd10 P7 O10 ADD(10)
DATA(14) T15 mdMemDa14 mdMemAd11 U6 O11 ADD(11)
HOOKINT C131 C134 C144 C145 C135 C136 C138 C146
DATA(15) U16 mdMemDa15 mdMemAd12 T6 O12 ADD(12)
mdMemAd13 R6 O13 ADD(13) 10n 10n 10n 10n 10n 10n 10n 100p
VBB mdMemAd14 T5 ADD(14)
SLEEPCLK R2 ccSleepClk mdMemAd15 R5 ADD(15)
CCONT_INT G3 ccInt mdMemAd16 U4 ADD(16)
PURX H15 ccPURX mdMemAd17 T4 ADD(17)
R100
HOOKINT G2 acHookInt mdMemAd18 U3 ADD(18)
220k
EAD_HEADINT' H1 acHeadInt mdMemAd19 T3 ADD(19)
Z100
FBUS_RX J1 acAccRxData mdMemAd20 U2 ADD(20)
EAD_HEADINT
TX_LIM E15 rfTXLim mdMemAd21 T1 ADD(21)
BLM11A601SPT C100
R101
12p TP110 SER_CLK K2 teqDSPSerClk mdRFSClk E16 SYN_CLK
C16 tmTstMode mdRFTXCGate G15
10k
M1 emEMU0 mdRFSLE2 F17
M2 emEMU1 mdRFSLE1 F16 SYN_LE1
ADD(21:0)
TP111 JTAG(1) K3 emJTDI mdRFSData E17 SYN_DAT
TX_LIM
TP112 JTAG(2) L1 emJTSClk
TP113 JTAG(3) L3 emJTRstX mdTXD0 B12 TP132 TXD(0)
TP114 JTAG(4) L4 emJTMS mdTXD1 A12 TXD(1)
ROW(5:0) SYN_CLK
mdTXD2 D11 TXD(2)
ROW(0) N16 mdP1UIF0 mdTXD3 C11 TXD(3)
SYN_LE1
ROW(1) N17 mdP1UIF1 mdTXD4 B11 TXD(4)
ROW(2) M15 mdP1UIF2 mdTXD5 A11 TXD(5)
SYN_DAT
ROW(3) M16 mdP1UIF3 mdTXD6 A10 TXD(6)
ROW(4) L14 mdP1UIF4 mdTXD7 C10 TXD(7)
ROW(5) L15 mdP1UIF5
UIF_CCONT_SDIO
UIF_CCONT_SDIO J16 mdUIFSDIO mdP0UIF0 L16 COL(0)
TXD(7:0)
mdP0UIF1 K17 COL(1)
CLK9M83
CLK9M83 P2 cfCDMAClk mdP0UIF2 K14 COL(2)
CLK19M2O R1 cfSysClk mdP0UIF3 K15 COL(3)
CLK19M2O
A14 cfAData mdP0UIF4 K16 COL(4)
CAFESIO(1) C13 cf2MDSerD
CLK19M2O
RXD(0) TP115 B10 cfRXD0 mdModeSel E2 XIECD TP133
COL(4:0)
RXD(1) A9 cfRXD1 mdBandSel E1 XIECLOCK TP134
RXD(2) D9 cfRXD2 mdLoByteSelX F2
RXD(3) C9 cfRXD3 mdVibraPWM F1 VIBRA
RXD(4) A8 cfRXD4 mdBuzzPWM G4 BUZZER
RXD(5) B8 cfRXD5 mdAccTxData H2 FBUS_TX'
RXD(6) D8 cfRXD6 mdDSPSerFSync J2 DSP_SER_FSNC TP140
VIBRA
RXD(7) C8 cfRXD7 mdJTDO K4 JTAG(0) TP141
RXD(8) A7 cfRXD8 mdCContCSX J14 CCONTCSX