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RX MID CHANNELS
850: CH190 -- 881,6
GSM: CH 62 -- 947,4 MHz J1050
EGSM: CH 37 -- 942,4Mhz
DCS: CH 700 -- 1842,8MHz
PCS: CH 661 -- 1960MHz Coax Cable to Keyboard PCB
DCS/PCS OUT
TX_OUT_HB 9
1 2 3
21
5
B+
TX_OUT_LB 2
1 2 3 Power and
Antenna
GSM850/ Control 1 RF_SENSE
U50 GSM900 OUT
PA + Antenna Switch 16 15 14 13 8 7 3 4 6
1900 MHZ
NEPTUNE LTS H1 IO_REG (VCC + 2.775V)
1800 MHz U800 A11 PERIPH_REG
TX_START
( to Atlas )
(VCC + 2.775V)
DSP Peripherals Power E2 REF_REG (VCC + 1,575V)
(to U200) (Clock ) MCLK
( Frontend Control
T9 accelerator, encryption V5 VBUCK (VCC + 1,875V)
900 MHz (Reset ) MS W10 SPI Timer, Interupts
and Digital Modulation)
(Data In /OUT) MDI
U9 VSIM (from Atlas)
K2
SIM DIO (Data In /OUT)
850 MHz K3
(Transmitt Enable)
RAMP (PA Power Control)
U6 DSP SIM RST (Reset )
DSP SIM J4 (from / to J508)
from Neptune V8 L1 Timer Memory
UltraLite Interface L1 SIM CLK (Clock )
( Frontend Control
and Digital Modulation) 104 MHz SIM_PD
R1
RX_ANT_EN
(from Atlas)
(Transmitt Enable)
(Receive Enable)
TX_START
CNTRL_1
CNTRL_2
CNTRL_3
TXI (NC)
VSIM_EN (to Atlas)
(Band select)
M1
TX_EN
MCLK
B10 PA Control
DATA BUS D0-15
MDI
RF_SENSE
MS
Shared Memory
1Mbit RAM ADDRESS BUS A1-24
G8 E8 E7 D7 C3 D2 B7 D6 G5 E6 C2
W7 W18 CE0B K1 U700
DAC1 GPIO MCU External CE_2 (NC) G8
MCU Memory
A2 SAW/ LNA G12 ARM7 Memory V17 CS2B D6
LNA
Matching IIN VoiceBand 52 MHz G17 EB1B F3
RX/TX ADC Sync Anti Anti Chanel DAC A13 Interface FLASH
IBIN LPF F8 K16 EB0B C2
A3 Switch 13 bit Filter Drop Alias Filter 12 bit N10
SAW/ LNA
LNA ENR J19 R WB F4 RESET OUT
F5,D5
Matching F7 T16 OEB J2,H1,H8
Output Mixer
Quadrature Polyphase
Mixer
DC CLKR 26 MHz T19 BURSTCLK C6 E4... VBUCK (from Atlas)
Filter Correct Serial A4
A5 SAW/ LNA (100KHz) (100KHz)
F6 Oscillator Clock Generator L16 LBAB E5
LNA Interface
Matching FSR N18 ECBB
H7
G7 16MB SRam
A6
QBIN DRI 64 MB Flash
SAW/ LNA
LNA P2 LCD_RS
RX/TX ADC Sync Anti Anti Chanel DAC LCD_CS
Matching QIN Switch 13 bit Filter Drop Alias Filter 12 bit
LPF MQSPI N3
Display M4 LCD_CLK_DATA6
Quadrature P1 LCD_SDATA_DATA7 (to U1301 ATI
1 2 G1 Generator D8 OSCO
U1051 Digital TX L3... LCD DATA (0 - 5)
PERIPH_IO_REG
Clock Generator
Interface G7
Oscilator and
F1 Reference E5 OSCM (Clock enable)
1 W8 INT3 (interupt for FM IC)
EDGE
Devider C5
3
Y1201 2
U250 GMSK EDGE
FIR C6 26MHz U10 TOUT12 (Bias output for THERM signal)
Modulator Modulator
GSM/ EDGE Filter V6 STANDBY_GATEB (to Clock enable Circuit)
TRANCEIVER F4 RF_DATA
(Data In /OUT) GPIO U12 ANT_DETB (from J508)
(Clock ) (U250 Control Bus) U8
Interface
GMSK/ EDGE Select F5 RF_CLK V7 SPI T15 RTCK (to J508 Tri data write)
Serial
(Chip select)
( VCO Feedback ) G4 RF_CS W9
FIN On
Devider Pre-Distortion Anti G3 LDTO (NC)
( VCO Tuning) Filter Alias Off C18 LT_SNS_CTL
( Lock Detect Out)
E1 ADC DATA
VCO1 (TX_LB) One BaseBand UART2
UART / USB Keypad Timer 6
Loop Filter
CP
MQSPI Wire Serial Audio Universal
Phase Det. ADC H3 VCO_REG Interface Interface Interface Bus Port Interface Asynchron. BT 1
VCO2 (TX_HB) Voltage G7.. PERIPH_IO_REG Q801
PA Control Reg. (rx) (tx) Rx /Tx
TX_EN
C1.. RF_REG
A17 C15 D15 A15 F3.... V12 W12 D18 T12 V13 E3 U11 A12 B13 N13 D16 B17 B15 Light Sensor 2
(VCC's from Atlas) B16 C16 A16 G3.... W13T11 V11 B14 T10 G8 U13 W5 W11 D13 B12 N17 V16 D19
OSCM