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Compal Confidential
Model Name : V5MM2_Ezel_HW
File Name : LA-A021P
1 1




Compal Confidential
2 2




M/B Schematics Document
Intel Shark Bay ULT (Hasswell + Lynx Point-LP)
nVidia N14P-GT


3 2013-08-XX 3




REV:1.0




4 4




ZZZ1
Part Number Description Security Classification Compal Secret Data Compal Electronics, Inc.
2012/11/XX EOP Title
DAZ0YY00100 PCB V5MM2 LA-A021P LS-A001P/A002P/A003P/A005P/A006P/A007P
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5MM2 M/B LA-A021P Schematic
Date: Tuesday, August 27, 2013 Sheet 1 of 57
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Fan Control
page 37




Lighting Bolt HDMI Conn. eDP Conn.
1 1
page 27 page 26
204pin DDR3L-SO-DIMM X1
page 28,29
eDP x 4 lanes
Intel Haswell ULT BANK 0, 1, 2, 3 page 15
DP x 4 lanes HDMI x 4 lanes Memory BUS
2.7GT/s 2.97GT/s Dual Channel
DDI
Haswell ULT
Processor 1.35V DDR3L 1333/1600 204pin DDR3L-SO-DIMM X1
BANK 4, 5, 6, 7 page 16

MINI Card nVidia N14P-GT OPI
WLAN GDDR5*8
USB port 8 page 30 page 17~25

PCIe 2.0 PCIe 2.0 x4 USB3.0 conn x2 USB/B CMOS
5GT/s 5GT/s USB2.0 Bluetooth
USB3.0 port 1,2
conn x1 USB port 4
Camera
port 4 port 5 Flexible IO
2
Lynx Point - LP USB2.0 port 0,1
USB port 3
USB port 7 2


page 32 page 31 page 30 page 26
PCIe 2.0 PCIe 2.0 PCH
5GT/s 5GT/s USBx8 48MHz
SATA3.0 SATA3.0
port 3 port 2 6.0 Gb/s 6.0 Gb/s
port 1 port 0
Lightning Bolt x1 Touch Panel Sensor Hub
USB3.0 port 3
Card Reader mSATA HDD SATA HDD USB2.0 port 2 USB port 5 STM32F
2 in 1 Conn. Conn. page 28 USB port 6
(SD/MMC) page 26 page 26
page 30 page 31
page 31 1168pin BGA
page 04~14 3.3V 24MHz
HD Audio
Sub Board
RTC CKT. LPC BUS LPC SPI HDA Codec
3
LS-A001P CLK=24MHz ALC3225 ALS GYRO 3

page 6 page 35
IO/B CM3218
page 26
L3GD20TR
page 26
(USB*1+Card Reader)
page 31 ENE TPM SPI ROM x2
Power On/Off CKT. KB901233
page page 38 page 7 ACCEL with
page 34 LS-A002P
Sensor/B page 26 E-COMPASS
Amplifier LSM303D
DC/DC Interface CKT. LS-A003P page 36 page 26
page 39
Redriver/B page 26
Touch Pad Int.KBD
page 34 page 34
Power Circuit DC/DC LS-A005P Int. Speaker Int. MIC Combo Jack
page 39~51 LED/B page 34
page 36 page 36
(HP/MIC) 36
page
4 4

LS-A006P
Power/B page 34
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/11/XX EOP Title
LS-A007P Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
E-Compass/B page 26 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Custom
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5MM2 M/B LA-A021P Schematic
Date: Tuesday, August 27, 2013 Sheet 2 of 57
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+0.675VS +0.675VSP to +0.675VS switched power rail for DDR terminator ON OFF OFF Board ID / SKU ID Table for AD channel
+1.05VSDGPU +1.05VSDGPU switched power rail for GPU ON OFF OFF Vcc 3.3V +/- 5%
+1.05VS_VTT +1.05VSP to +1.05VS_VTT switched power rail for CPU ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.35V +1.35VP to +1.35V power rail for DDRIIIL ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+1.5VSDGPU +1.5VSDGPUP to +1.5VSDGPU switched power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VALW +3VALW always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VLP B+ to +3VLP power rail for suspend power ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+3VSDGPU +3VS to +3VSDGPU switched power rail for GPU ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
+5VALW +5VALWP to +5VALW power rail ON ON ON*
+5VS +5VALW to +5VS switched power rail ON OFF OFF
BOARD ID Table B0M Option Table
2 2
Item BOM Structure
+RTCVCC RTC power ON ON ON Board ID PCB Revision Unpop @
0 0.1 Connector CONN@
1 0.2 UMA only UMA@
2 0.3 nVidia N14P-GT DIS@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 3 0.4 VRAM Selection X76@
4 1.0 With GC6 GC6@
EC SM Bus1 address EC SM Bus2 address 5 Without GC6 NGC6@
6 USB Charger CHR@
Device Address Device Address
Smart Battery 0001 011X On Board Thermal Senser 0100 110x
7 TPM Module TPM@
VGA Internal Thermal Senser 0100 000x
without TPM NTPM@
USB Port Table Buzzer BUZZ@
G Senser 0011 000x
EMI,ESD parts EMC@
PCH SM Bus address USB 2.0 Port
XEMC@
0 USB3.0 Connector (Left) RF parts RF@
Device Address
ChannelA DIMM0 1001 000x JDIMM1
1 USB3.0 Connector (Left) XRF@
3 3
ChannelB DIMM1 1001 010x JDIMM2
2 Lightning Bolt mDP Conn. Support DP++ DM@
3 USB2.0 (USB/B) no support DP++ NDM@
EHCI1
4 Mini Card (WLAN+BT)
5 Touch Panel
6 Sensor Hub
7 Camera


USB 3.0 Port
1 USB Port(Left 3.0)
2 USB Port(Left 3.0)
XHCI
3 Lightning Bolt USB3.0
4




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Security Classification Compal Secret Data Compal Electronics, Inc.
2012/11/XX EOP Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5MM2 M/B LA-A021P Schematic
Date: Tuesday, August 27, 2013 Sheet 3 of 57
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5 4 3 2 1

HASWELL_MCP_E
U1A @




C54 C45
<28> CPU_DP1_N0 DDI1_TXN0 EDP_TXN0 EDP_TXN0 <26>
C55 B46
<28> CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 <26>
1, 0 Directly to mDP connector B58 A47
<28> CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 <26>
C58 B47
<28> CPU_DP1_P1 DDI1_TXP1 EDP_TXP1 EDP_TXP1 <26>
CPU_DP1_N2_C C904 1 2 .1U_0402_16V7K CPU_DP1_N2 B55
DP for Lightning-Bolt <28> CPU_DP1_N2_C
<28> CPU_DP1_P2_C
CPU_DP1_P2_C C905 1 2 .1U_0402_16V7K CPU_DP1_P2 A55 DDI1_TXN2 C47
EDP_TXN2 <26>
CPU_DP1_N3_C C907 1 2 .1U_0402_16V7K CPU_DP1_N3 A57 DDI1_TXP2 EDP_TXN2 C46
3, 2 connected to TI-HD3SS2521 <28> CPU_DP1_N3_C
CPU_DP1_P3_C C906 1 2 .1U_0402_16V7K CPU_DP1_P3 B57 DDI1_TXN3 EDP_TXP2 A49
EDP_TXP2 <26>
<28> CPU_DP1_P3_C DDI1_TXP3 EDP_TXN3 EDP_TXN3 <26>
D DDI EDP B49 D
EDP_TXP3 EDP_TXP3 <26>
C51
<27> CPU_DP2_N0 DDI2_TXN0
C50 A45 EDP_AUXN <26>
<27> CPU_DP2_P0 DDI2_TXP0 EDP_AUXN
C53 B45 EDP_AUXP <26>
<27> CPU_DP2_N1 DDI2_TXN1 EDP_AUXP
B54
HDMI <27>
<27>
CPU_DP2_P1
CPU_DP2_N2
C49 DDI2_TXP1 D20 EDP_COMP R1 1 2 24.9_0402_1% +VCCIOA_OUT
B50 DDI2_TXN2 EDP_RCOMP A43
<27> CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL Trace width=20 mils,Spacing=25mil,Max length=100mils
A53
<27> CPU_DP2_N3 DDI2_TXN3
B53
<27> CPU_DP2_P3 DDI2_TXP3 EDP_DISP_UTIL <26>




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Reserved for ESD
HASWELL_MCP_E
U1B @
XEMC@
C94 1 2 6.8P_0402_50V8C
T20 @ D61
T2 @ K61 PROC_DETECT MISC
N62 CATERR J62 @ T107
+1.35V <33> H_PECI PECI PRDY K62 @ T108
2 1 R68 R8 JTAG
PREQ E60 @ T109
+1.05VS_VTT PROC_TCK
62_0402_5% 56_0402_5% E61 @ T110
1 2 H_PROCHOT#_R K63 PROC_TMS E59 @ T111
<33,40> H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 @ T112
PROC_TDI
1




C Reserved for ESD C95 1 2 6.8P_0402_50V8C F62 @ T113 C
R184 XEMC@ PROC_TDO
470_0603_5% R6 1 2 10K_0402_5% H_CPUPW RGD C61
PROCPWRGD PWR
C60 1 2 6.8P_0402_50V8C J60
2




XEMC@ BPM#0 H60
BPM#1 H61
Reserved for ESD BPM#2
DIMM_DRAMRST# H62
DIMM_DRAMRST# <15,16> BPM#3
R11 1 2 200_0402_1% SM_RCOMP0 AU60 K59
R13 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3 BPM#4 H63
R41 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60
1 SM_RCOMP2 BPM#6
Reserved for ESD XEMC@ DIMM_DRAMRST# AV15 J61
C1450 DDR_PG_CTRL AV61 SM_DRAMRST BPM#7
placed near to the CPU <15> DDR_PG_CTRL SM_PG_CNTL1
100P_0402_50V8J
2
DDR3 Compensation Signals
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B B




ES: 43L:
U1 U1 U1 U1 SA000067060 - QDJB B1 0.8G 4319NZBOL05
SA000067H50 - QDJ7 B1 0.8G 4319NZBOL06
SA00006G710 - QDJ8 B1 0.8G 4319NZBOL07
4319NZBOL08
Pre-QS: 4319NZBOL09
CPU_QDJB_B1 CPU_QDJ7_B1 CPU_QDJ8_B1 CPU_QEA4_C0 SA00006NM00 - QEA4 C0 1.3G
QDJB@ QDJ7@ QDJ8@ QEA4@
SA000067060 SA000067H50 SA00006G710 SA00006NM00
A A


U1 U1 U1 U1 U1 43L:
4319NZBOL01
4319NZBOL02
4319NZBOL03 Security Classification Compal Secret Data Compal Electronics, Inc.
4319NZBOL04 2012/11/XX EOP Title
CPU_QDJB_B1 CPU_QDJ7_B1 CPU_QDJ6_B1 CPU_QDJ9_B1 CPU_QDJC_B1
Issued Date Deciphered Date HSW MCP(1/11) DDI,MSIC,XDP
QDJBe@ QDJ7e@ QDJ6@ QDJ9@ QDJC@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SA000067060 SA000067H50 SA00006FY20 SA00006G120 SA00006EY30 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5MM2 M/B LA-A021P Schematic
Date: Tuesday, August 27, 2013 Sheet 4 of 57
5 4 3 2 1
5 4 3 2 1


HASWELL_MCP_E
U1C @
HASWELL_MCP_E
U1D @

DDR_A_D0 AH63 AU37
SA_DQ0 SA_CLK#0 SA_CLK_DDR#0 <15>
DDR_A_D1 AH62 AV37
SA_DQ1 SA_CLK0 SA_CLK_DDR0 <15>
DDR_A_D2 AK63 AW36 DDR_B_D0 AY31 AM38
SA_DQ2 SA_CLK#1 SA_CLK_DDR#1 <15> SB_DQ0 SB_CK#0 SB_CLK_DDR#0 <16>
DDR_A_D3 AK62