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C115 Level 3 Circuit Description
C115
Level 3
Circuit Description
07 / 30 / 04
V1.0
Motorola Proprietary Information 1
C115 Level 3 Circuit Description
Index
1 Receive ................................................................................................................................. 4
1.1 Band selection............................................................................................................... 4
1.2 Frontend........................................................................................................................ 4
1.3 Demodulation................................................................................................................ 5
1.4 Audio............................................................................................................................. 7
1.4.1 Voice Downlink Patch ................................................................................................ 7
1.5 Earpiece Receiver ......................................................................................................... 7
1.6 Headset ......................................................................................................................... 7
1.7 Download Receive Path................................................................................................ 7
1.8 26MHz System Clock .................................................................................................... 8
1.9 Tracking Oscillator....................................................................................................... 8
2 TRANSMIT......................................................................................................................... 9
2.1 Audio ( Voice uplink Patch )......................................................................................... 9
2.2 Download Transmit Path............................................................................................ 10
2.3 Modulation.................................................................................................................. 10
2.4 Transceiver ................................................................................................................. 11
2.5 TX PA.......................................................................................................................... 12
2.6 TX PA Power Control in SKY77324 U17 ................................................................... 12
3 Iota Monitoring ADC ....................................................................................................... 14
4 Baseband Serial Port(BSP) .............................................................................................. 14
5 Microcontroller Serial Port(USP) ................................................................................... 15
6 Pulse Width Tones (PWT) ............................................................................................... 15
7 Pulse Width Light (PWL) ................................................................................................ 15
8 General purposes I/O (GPIO).......................................................................................... 15
9 Mono Display .................................................................................................................... 15
9.1 Display Backlights ...................................................................................................... 16
10 32KHz RTC ................................................................................................................... 16
Motorola Proprietary Information 2
C115 Level 3 Circuit Description
11 SIM Circuit.................................................................................................................... 16
11.1 SIM Card Supply Voltage Generation ........................................................................ 16
12 Keypad ........................................................................................................................... 17
12.1 Keypad Matrix ............................................................................................................ 18
13 Vibrater circuit ............................................................................................................. 19
14 Memory.......................................................................................................................... 19
15 Power.............................................................................................................................. 19
15.1 Low-Dropout Voltage Regulators............................................................................... 19
15.2 Radio Power Down Methods ...................................................................................... 20
16 Sleep Module ................................................................................................................. 20
16.1 Sleep Up Sequence...................................................................................................... 21
16.2 Sleep off Sequence ...................................................................................................... 21
17 Power Tree..................................................................................................................... 22
18 Charging Circuit and External Power........................................................................ 22
18.1 Battery support ........................................................................................................... 22
18.2 Charger support.......................................................................................................... 22
Motorola Proprietary Information 3
C115 Level 3 Circuit Description
1 Receive
1.1 Band selection
The received signal is received through the antenna. Received GSM RF signal enters the unit at
the antenna. C144, C145, and C146 components provide antenna matching. The RF signal then
enters mechanical 50-ohm RF connector JP1. This RF connector is used for phasing, testing.
From A1 the RF signal enters U17 (TX/RX antenna switch) on Pin 3 (ANT), where through
control voltages the RX path is isolated from the TX path. The following voltages control the
RF Switch:
VC1 put low and VC2 put high, these signals put the phone into TX GSM900/850 Mode (from
U7 Pin K13 and K14).
VC1 put high and VC2 put low, these signals put the phone into TX DCS1800/PCS1900 Mode.
VC1 and VC2, these signals put the phone into RX Mode when both Low.
The low band RX output from U17 (Pin 11) is connected to the SAW filter F2. The high band
RX output from U17 (Pin 1) is connected to the SAW filter F3. The RF signal of the selected
frequency band is then sent to single ended input to differential output to the front end IC U15
(Rita).
1.2 Frontend
The receiver block diagram in the Rita IC U15 is shown in Figure 1. Three LNAs are provided
to support the receiver frequency bands. The LNAs drive an AGC current steering stages that
feed integrated transformer matching network. The transformer drives the quadrature mixers
that convert the RF signal to baseband, DCR(Direct Conversion Receiver), quadrature I and Q
signals. The signal then passes through the baseband amplification and 3-cascaded low pass
filters into an analog to digital converter in the Iota IC.
Figure 1 Receiver Path
Motorola Proprietary Information 4
C115 Level 3 Circuit Description
Figure 2 Iota and CalpysoLite_G2 IC
1.3 Demodulation
The RXI and RXQ signals are feed in the . Dual ADC stage on Iota IC U1 (Pin F9, F10, E9
and E10). The baseband codec (BBC) is composed of a baseband uplink path (BUL) and a
baseband downlink path (BDL).
The BDL path includes two identical circuits for processing the analog baseband I and Q
components generated by the RF circuits. The first stage of the BDL path is a continuous
second-order antialiasing filter that prevents aliasing of out-of-band frequency components due
to sampling in the ADC. This filter serves also as an adaptation stage between external and on-
chip circuitry.
The antialiasing filter is followed by a fourth-order modulator that performs analog-to-
digital conversion at a sampling rate of 6.5 MHz. The ADC provides 2-bit words to a digital
filter that performs the decimation by a ratio of 24 to lower the sampling rate to 270.833 kHz.
The ADC also provides channel separation by providing enough rejection of the adjacent
channels to allow the demodulation performances required by the GSM specification.
The BDL path includes an offset register, in which the value representing the channel dc offset
is stored. This value is subtracted from the output of the digital filter before transmitting the
digital samples to the CalpysoLite_G2 IC U7 (DSP) via the BSP. Upon reset, the offset register
is loaded with 0s; its content is updated during the calibration process.
The typical sequence of burst reception consists of:
1. Power up the BDL path
2. Perform an offset calibration
3. Convert and filter the I and Q components and transmit digital samples
Timing of this sequence is controlled via the TSP, which receives serial real-time control
signals from the TPU of the CalpysoLite_G2 IC U7 (DSP) device. Three real-time signals
control the transmission of a burst: BDLON, BDLCAL, and BDLENA. Each signal
corresponds to a time window.
BDLON high sets the BDL path in power-on mode after a delay corresponding to the power-on
settling time of the analog block. BDLCAL enables the offset calibration window. Two offset
calibration modes are possible and are selected by the state of bit 9 (EXTCAL) of the baseband
codec control register. When EXTCAL is 0, the analog inputs are disconnected from the
external world and internally shorted. The result of conversion done in this state is stored in the
Motorola Proprietary Information 5
C115 Level 3 Circuit Description
offset register. When EXTCAL is 1, the analog input remains connected to external circuitry,
and the result of conversion, including in this case internal offset plus external circuitry offset,
is stored in the offset register. The duration of the calibration window depends mainly on the
settling time of the digital filter.
Data conversion starts with the rising edge of the BDLENA signal; however, the first eight I
and Q samples are not transmitted to the CalpysoLite_G2 IC U7 (DSP), since they are
meaningless due to the group delay of the digital filter. The rising edge of BDLENA is also
used by the IBIC to affect the transmit path of the BSP to the BUL path during the entire
reception window. At the falling edge of BDLENA, the conversion in progress is completed
and samples are transmitted before stopping the conversion process. Finally, BDLON low sets
the BDL path in power-down mode.
Figure 3 Baseband Downlink Block Diagram
Figure 4 Voice Codec Block Diagram
Motorola Proprietary Information 6
C115 Level 3 Circuit Description
1.4 Audio
The voice codec circuitry processes analog audio components in the uplink path and applies
this signal to the voice signal interface for eventual baseband modulation. In the downlink path,
the codec circuitry changes voice component data received from the voice serial interface into
analog audio. The following paragraphs describe these uplink/downlink functions in more
details.
1.4.1 Voice Downlink Patch
The VDL path receives speech samples at the rate of 8 kHz from the CalpysoLite_G2 IC U7
(DSP) via the VSP and converts them to analog signals to drive the external speech transducer.
The digital speech coming from the CalpysoLite_G2 IC U7 (DSP) is first fed to a speech digital
filter that has two functions. The first function is to interpolate the input signal and to increase
the sampling rate from 8 kHz up to 40 kHz to allow the digital-to-analog conversion to be
performed by an oversampling digital modulator. The second function is to band-limit the
speech signal with both low-pass and high-pass transfer functions. The filter, the PGA gain, and
the volume gain can be bypassed by programming bit 9 (VFBYP) in the voiceband control
register 1.
The interpolated and band-limited signal is fed to a second order digital modulator sampled
at 1 MHz to generate a 4-bit (9 levels) oversampled signal. This signal is then passed through a
dynamic element-matching block and then to a 4-bit digital-to-analog converter (DAC).
The volume control and the programmable gain are performed in the voiceband digital filter.
Volume control is performed in steps of 6 dB from 0 dB to