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5 4 3 2 1
D D
Discrete/UMA /Muxless Schematics Document
AMD LIANO CPU FS1
AMD GPU Manhattan(Park/Madison M2)
C C
and Vancouver(Seymour/Whistler M2)
B B
Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A4
JE50_SB SB
Date: Friday, April 01, 2011 Sheet 1 of 102
5 4 3 2 1
5 4 3 2 1
SYSTEM DC/DC
JE50-SB Project code:91.4M701.001 RT8239 41
JE50-SB Block Diagram INPUTS
DCBATOUT
OUTPUTS
5V_S5(5.5A)
3D3V_S5(5A)
SYSTEM DC/DC
AMD Liano APU X8 PCI EXPRESS GRAPHIC(Muxless Lan8 ~Lan15) RT8207 44
D
DDR3 ( FS1 socket 45W ) X16 PCI EXPRESS GRAPHIC(Diserete only Lan0 ~Lan15)
Madison/Park
5V_S5 1D5V_S3(15A) D
1066/1333 MHz 722-Pin uFCPGA722 DDR3 RT8207 44
DP2(PCI EXPRESS Lan0~Lan3) Whistler/Seymour 512MB/1GB/2GB
14,15,16 VRAM 5V_S5 0D75_S0(1.2A)
GPP X4 port ATI
DP0 83,84,85,86,87 88,89,90,91 SYSTEM DC/DC
DP X6 Port
RT8238 46
DDR3 HDMI 1.Park/Seymour (64Mx16b*4)=>512MB INPUTS OUTPUTS
1066/1333 MHz 4,5,6,7,8 51 2.Park/Seymour(128MX16b *4) =>1GB
3.Madison/Whistler(64Mx16b*8)=>1GB 5V_S5 1D1V_S5(1.4A)
14,15,16 DP1 EDP 4.Madison/Whistler(128Mx16b*8)=>2GB
Panel 49 RT8238 45
UMI-Link
4X4 (Diserete only) 5V_S5 1D2V_S0(5.2A)
LCD
TRAVIS 49
PS8612 9 RT9025 93
FCH CRT 3D3V_S5 1D8V_VGA_S0
INT MIC 50
Codec HUDSON-M3
C 49
ALC271X
AZALIA PCB STACKUP 1D5V_S3 1V_VGA_S0 C
Integrated Display DAC
29 LAN TXFM RJ45 59 TOP RT9025 48
PCIE x 1 59
MIC In USB 3.0 (4parts) Giga LAN VCC 2D5V_S0
3D3V_S0
USB 2.0 BCM57785 31 (200mA)
58 (10 parts or 14 port MS/MS Pro/xD S
if USB 3.0 do not used) /MMC/SD RT8208 92
INT.SPKR 5 in 1 74 S 5V_S5 VGA_CORE
GPP X4 port
GND
58 USB 1.1 (2 parts) CHARGER
SATA (6 parts) PCIE x 1,USB x 1 Mini Card BOTTOM BQ24745 40
INT RTC WLAN 65
INPUTS OUTPUTS
Line Out INT CLK GEN
PCIE x 1,USB x 1
HW MONITOR Mini-Card CHG_PWR
58 SIM 18V 6.0A
ACPI 1.1 WWAN 66 66
DCBATOUT
UP+5V
5V 100mA
B B
USB 3.0 x3,USB x 3
17,18,19,20,21,22 USB3.0 3 PORT61 82
CPU DC/DC
ISL6267 42,43
LPC BUS INPUTS OUTPUTS
VCC_CORE_S0
SATA 0~1.55V 18A
KBC BIOS LPC
DCBATOUT
ENE MXIC DEBUG VDDNB
USB 3.0 x1 MX25L1605 CONN. 71
USB KB3936 0~1.55V 4A
CCD3.0 27 60
HDD SATA 35
56
Mini USB
Blue Tooth 63
Camera
49 Touch INT.
ODD SATA 56 Pad 69 KB 69
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Block Diagram
Size Document Number Rev
A3
JE50_SB SB
Date: Friday, April 01, 2011 Sheet 2 of 102
5 4 3 2 1
5 4 3 2 1
Strapping
REQUIRED SYSTEM STRAPS USE this pin to determine INT/EXT CLK
D D
EC_PWM2 PCI_CLK1 RTC_CLK CLK_PCI_LPC PCI_CLK4 LPC_CLK0 LPC_CLK1
PCH GPO199
PULL Allow USE CLKGEN
LPC ROM PCIE GEN2 S5_PLUS Mode DEBUG non_Fusion ENABLE EC ENABLED
HIGH
DISABLE STRAPS CLOCK mode
(Use Internal)
DEFAULT DEFAULT DEFAULT
DEFAULT
PULL Force S5_PLUS Mode IGNORE Fusion DISABLE EC CLKGEN
LOW SPI ROM PCIE GEN1 ENABLE DEBUG CLOCK mode DISABLED
STRAPS DEFAULT (Use External)
DEFAULT DEFAULT
USB Table PCIE Routing
USB
C Pair Device
APU C
0 USB 2.0 EXT2(For SW Debug) LANE0 LAN
1 WLAN
2 NC
LANE1 WWAN
3 WWAN LANE2 LAN
4 BT
5 3G SIM Card
LANE3
6 NC
7 CCD FCH
8 NC
9 Card Reader
LANE0
10 USB 3.0 port 1 LANE1
11 USB 2.0 EXT2
12 USB 2.0 EXT3
LANE2
B
13 NC LANE3 B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Table of Content
Size Document Number Rev
A3
JE50_SB SB
Date: Friday, April 01, 2011 Sheet 3 of 102
5 4 3 2 1
5 4 3 2 1
APU1F 6 OF 6
PCI EXPRESS
PEG_RXP0 AA8 AA2 GTXP0 DIS 1 2 C401 SCD1U16V2KX-3GP PEG_TXP0 GTXP0 UMA_PX C433 1 2 SCD1U16V2KX-3GP
P_GFX_RXP0 P_GFX_TXP0 APU_HDMI_DATA2 51
PEG_RXN0 AA9 AA3 GTXN0 DIS 1 2 C402 SCD1U16V2KX-3GP PEG_TXN0 GTXN0 UMA_PX C434 1 2 SCD1U16V2KX-3GP
P_GFX_RXN0 P_GFX_TXN0 APU_HDMI_DATA2# 51
SAINE
PEG_RXP1 Y7 Y2 GTXP1 DIS 1 2 C403 SCD1U16V2KX-3GP PEG_TXP1 GTXP1 UMA_PX C435 1 2 SCD1U16V2KX-3GP
P_GFX_RXP1 P_GFX_TXP1 APU_HDMI_DATA1 51
PEG_RXN1 Y8 Y1 GTXN1 DIS 1 2 C404 SCD1U16V2KX-3GP PEG_TXN1 GTXN1 UMA_PX C436 1 2 SCD1U16V2KX-3GP
P_GFX_RXN1 P_GFX_TXN1 APU_HDMI_DATA1# 51
PEG_RXP2 W5 Y4 GTXP2 DIS 1 2 C405 SCD1U16V2KX-3GP PEG_TXP2 GTXP2 UMA_PX C437 1 2 SCD1U16V2KX-3GP
P_GFX_RXP2 P_GFX_TXP2 APU_HDMI_DATA0 51
PEG_RXN2 W6 Y5 GTXN2 DIS 1 2 C406 SCD1U16V2KX-3GP PEG_TXN2 GTXN2 UMA_PX C438 1 2 SCD1U16V2KX-3GP
P_GFX_RXN2 P_GFX_TXN2 APU_HDMI_DATA0# 51
PEG_RXP3 W8 W2 GTXP3 DIS 1 2 C407 SCD1U16V2KX-3GP PEG_TXP3 GTXP3 UMA_PX C439 1 2 SCD1U16V2KX-3GP
P_GFX_RXP3 P_GFX_TXP3 APU_HDMI_CLK 51
D PEG_RXN3 W9 W3 GTXN3 DIS 1 2 C408 SCD1U16V2KX-3GP PEG_TXN3 GTXN3 UMA_PX C440 1 2 SCD1U16V2KX-3GP D
P_GFX_RXN3 P_GFX_TXN3 APU_HDMI_CLK# 51
PEG_RXP4 V7 V2 GTXP4 DIS 1 2 C409 SCD1U16V2KX-3GP PEG_TXP4
PEG_RXN4 P_GFX_RXP4 P_GFX_TXP4 GTXN4 C410 SCD1U16V2KX-3GP PEG_TXN4
V8 P_GFX_RXN4 P_GFX_TXN4 V1 DIS 1 2
PEG_RXP5 U5 V4 GTXP5 DIS 1 2 C411 SCD1U16V2KX-3GP PEG_TXP5
PEG_RXN5 P_GFX_RXP5 P_GFX_TXP5 GTXN5 C412 SCD1U16V2KX-3GP PEG_TXN5
U6 P_GFX_RXN5 P_GFX_TXN5 V5 DIS 1 2
PEG_RXP6 U8 U2 GTXP6 DIS 1 2 C413 SCD1U16V2KX-3GP PEG_TXP6
PEG_RXN6 P_GFX_RXP6 P_GFX_TXP6 GTXN6 C414 SCD1U16V2KX-3GP PEG_TXN6
U9 U3 DIS 1 2
GRAPHICS
PEG_RXP7 P_GFX_RXN6 P_GFX_TXN6 GTXP7 C415 SCD1U16V2KX-3GP PEG_TXP7
T7 P_GFX_RXP7 P_GFX_TXP7 T2 DIS 1 2
PEG_RXN7 T8 T1 GTXN7 DIS 1 2 C416 SCD1U16V2KX-3GP PEG_TXN7
PEG_RXP8 P_GFX_RXN7 P_GFX_TXN7 GTXP8 C417 SCD1U16V2KX-3GP PEG_TXP8
R5 P_GFX_RXP8 P_GFX_TXP8 T4 DIS_PX1 2
PEG_RXN8 R6 T5 GTXN8 DIS_PX1 2 C418 SCD1U16V2KX-3GP PEG_TXN8
PEG_RXP9 P_GFX_RXN8 P_GFX_TXN8 GTXP9 C419 SCD1U16V2KX-3GP PEG_TXP9
R8 P_GFX_RXP9 P_GFX_TXP9 R2 DIS_PX1 2
PEG_RXN9 R9 R3 GTXN9 DIS_PX1 2 C420 SCD1U16V2KX-3GP PEG_TXN9
PEG_RXP10 P_GFX_RXN9 P_GFX_TXN9 GTXP10 C421 SCD1U16V2KX-3GP PEG_TXP10
P7 P_GFX_RXP10 P_GFX_TXP10 P2 DIS_PX1 2
PEG_RXN10 P8 P1 GTXN10 DIS_PX1 2 C422 SCD1U16V2KX-3GP PEG_TXN10
PEG_RXP11 P_GFX_RXN10 P_GFX_TXN10 GTXP11 C423 SCD1U16V2KX-3GP PEG_TXP11
N5 P_GFX_RXP11 P_GFX_TXP11 P4 DIS_PX1 2
PEG_RXN11 N6 P5 GTXN11 DIS_PX1 2 C424 SCD1U16V2KX-3GP PEG_TXN11
PEG_RXP12 P_GFX_RXN11 P_GFX_TXN11 GTXP12 C425 SCD1U16V2KX-3GP PEG_TXP12
N8 P_GFX_RXP12 P_GFX_TXP12 N2 DIS_PX1 2
PEG_RXN12 N9 N3 GTXN12 DIS_PX1 2 C426 SCD1U16V2KX-3GP PEG_TXN12
PEG_RXP13 P_GFX_RXN12 P_GFX_TXN12 GTXP13 C427 SCD1U16V2KX-3GP PEG_TXP13
M7 P_GFX_RXP13 P_GFX_TXP13 M2 DIS_PX1 2
PEG_RXN13 M8 M1 GTXN13 DIS_PX1 2 C428 SCD1U16V2KX-3GP PEG_TXN13
PEG_RXP14 P_GFX_RXN13 P_GFX_TXN13 GTXP14 C429 SCD1U16V2KX-3GP PEG_TXP14
L5 P_GFX_RXP14 P_GFX_TXP14 M4 DIS_PX1 2
PEG_RXN14 L6 M5 GTXN14 DIS_PX1 2 C430 SCD1U16V2KX-3GP PEG_TXN14
PEG_RXP15 P_GFX_RXN14 P_GFX_TXN14 GTXP15 C431 SCD1U16V2KX-3GP PEG_TXP15
L8 P_GFX_RXP15 P_GFX_TXP15 L2 DIS_PX1 2
PEG_RXN15 L9 L3 GTXN15 DIS_PX1 2 C432 SCD1U16V2KX-3GP PEG_TXN15
P_GFX_RXN15 P_GFX_TXN15
AC5 AD4 PCIE_TXP0_C C441 1 2 SCD1U16V2KX-3GP
31 PCIE_RXP0 P_GPP_RXP0 P_GPP_TXP0 PCIE_TXP0 31
LAN 31 PCIE_RXN0 AC6 P_GPP_RXN0 P_GPP_TXN0 AD5 PCIE_TXN0_C C442 1 2 SCD1U16V2KX-3GP
PCIE_TXN0 31 LAN
66 PCIE_RXP1 AC8 P_GPP_RXP1 P_GPP_TXP1 AC2 PCIE_TXP1_C C443 1 2 SCD1U16V2KX-3GP 3G PCIE_TXP1 66 110325 -1
C WWAN 66 PCIE_RXN1 AC9 P_GPP_RXN1 P_GPP_TXN1 AC3 PCIE_TXN1_C C444 1 2 SCD1U16V2KX-3GP 3G PCIE_TXN1 66 WWAN C
AB7 AB2 PCIE_TXP2_C C457 1 2 SCD1U16V2KX-3GP
GPP
65 PCIE_RXP2 P_GPP_RXP2 P_GPP_TXP2 PCIE_TXP2 65
WLAN 65 PCIE_RXN2 AB8 P_GPP_RXN2 P_GPP_TXN2 AB1 PCIE_TXN2_C C460 1 2 SCD1U16V2KX-3GP
PCIE_TXN2 65 WLAN
AA5 P_GPP_RXP3 P_GPP_TXP3 AB4
AA6 P_GPP_RXN3 P_GPP_TXN3 AB5
AF8 AF1 UMI_TX0P_C C445 1 2 SCD1U16V2KX-3GP
17 UMI_FCH_APU_RX0P P_UMI_RXP0 P_UMI_TXP0 UMI_APU_FCH_TX0P 17
AF7 AF2 UMI_TX0N_C C446 1 2 SCD1U16V2KX-3GP
17 UMI_FCH_APU_RX0N P_UMI_RXN0 P_UMI_TXN0 UMI_APU_FCH_TX0N 17
AE6 AF5 UMI_TX1P_C C447 1 2 SCD1U16V2KX-3GP
17 UMI_FCH_APU_RX1P P_UMI_RXP1 P_UMI_TXP1 UMI_APU_FCH_TX1P 17
AE5 AF4 UMI_TX1N_C C448 1 2 SCD1U16V2KX-3GP
17 UMI_FCH_APU_RX1N P_UMI_RXN1 P_UMI_TXN1 UMI_APU_FCH_TX1N 17
AE9 AE3 UMI_TX2P_C C449 1 2 SCD1U16V2KX-3GP
17 UMI_FCH_APU_RX2P P_UMI_RXP2 P_UMI_TXP2 UMI_APU_FCH_TX2P 17
UMI_TX2N_C C450 SCD1U16V2KX-3GP
UMI-LINK
17 UMI_FCH_APU_RX2N AE8 P_UMI_RXN2 P_UMI_TXN2 AE2 1 2 UMI_APU_FCH_TX2N 17
AD8 AD1 UMI_TX3P_C C451 1 2 SCD1U16V2KX-3GP
17 UMI_FCH_APU_RX3P P_UMI_RXP3 P_UMI_TXP3 UMI_APU_FCH_TX3P 17
AD7 AD2 UMI_TX3N_C C452 1 2 SCD1U16V2KX-3GP
17 UMI_FCH_APU_RX3N P_UMI_RXN3 P_UMI_TXN3 UMI_APU_FCH_TX3N 17
1 2 P_ZVDDP K5 K4 P_ZVSS PEG_TXP[0..15]
1D2V_S0 P_ZVDDP P_ZVSS PEG_TXP[0..15] 83
R402
1
196R2F-GP PEG_TXN[0..15]
SAINE PEG_TXN[0..15] 83
62.10055.481 R401
196R2F-GP
PEG_RXP[0..15]
PEG_RXP[0..15] 83
2
PEG_RXN[0..15]
PEG_RXN[0..15] 83
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
APU_PCIE(1/5)
Size Document Number Rev
A3
JE50_SB SB
Date: Friday, April 01, 2011 Sheet 4 of 102
5 4 3 2 1
5 4 3 2 1
APU1A 1 OF 6
MEMORY CHANNEL APU1B 2 OF 6
A
14 M_A_A0 U20 MA_ADD0 MA_DATA0 E13 M_A_DQ0 14 MEMORY CHANNEL B
14 M_A_A1 R20 MA_ADD1 MA_DATA1 J13 M_A_DQ1 14 15 M_B_A0 T27 MB_ADD0 MB_DATA0 A14 M_B_DQ0 15
14 M_A_A2 R21 MA_ADD2 MA_DATA2 H15 M_A_DQ2 14 15 M_B_A1 P24 MB_ADD1 MB_DATA1 B14 M_B_DQ1 15
SAINE
P22 J15 P25 D16
SAINE
14 M_A_A3 MA_ADD3 MA_DATA3 M_A_DQ3 14 15 M_B_A2 MB_ADD2 MB_DATA2 M_B_DQ2 15
14 M_A_A4 P21 MA_ADD4 MA_DATA4 H13 M_A_DQ4 14 15 M_B_A3 N27 MB_ADD3 MB_DATA3 E16 M_B_DQ3 15
14 M_A_A5 N24 MA_ADD5 MA_DATA5 F13 M_A_DQ5 14 15 M_B_A4 N26 MB_ADD4 MB_DATA4 B13 M_B_DQ4 15
14 M_A_A6 N23 MA_ADD6 MA_DATA6 F15 M_A_DQ6 14 15 M_B_A5 M28 MB_ADD5 MB_DATA5 C13 M_B_DQ5 15
14 M_A_A7 N20 MA_ADD7 MA_DATA7 E15 M_A_DQ7 14 15 M_B_A6 M27 MB_ADD6 MB_DATA6 B16 M_B_DQ6 15
14 M_A_A8 N21 MA_ADD8 15 M_B_A7 M24 MB_ADD7 MB_DATA7 A16 M_B_DQ7 15
D 14 M_A_A9 M21 MA_ADD9 MA_DATA8 H17 M_A_DQ8 14 15 M_B_A8 M25 MB_ADD8 D
14 M_A_A10 U23 MA_ADD10 MA_DATA9 F17 M_A_DQ9 14 15 M_B_A9 L26 MB_ADD9 MB_DATA8 C17 M_B_DQ8 15
14 M_A_A11 M22 MA_ADD11 MA_DATA10 E19 M_A_DQ10 14 15 M_B_A10 U26 MB_ADD10 MB_DATA9 B18 M_B_DQ9 15
14 M_A_A12 L24 MA_ADD12 MA_DATA11 J19 M_A_DQ11 14 15 M_B_A11 L27 MB_ADD11 MB_DATA10 B20 M_B_DQ10 15
14 M_A_A13 AA25 MA_ADD13 MA_DATA12 G16 M_A_DQ12 14 15 M_B_A12 K27 MB_ADD12 MB_DATA11 A20 M_B_DQ11 15
14 M_A_A14 L21 MA_ADD14 MA_DATA13 H16 M_A_DQ13 14 15 M_B_A13 W26 MB_ADD13 MB_DATA12 E17 M_B_DQ12 15
14 M_A_A15 L20 MA_ADD15 MA_DATA14 H19 M_A_DQ14 14 15 M_B_A14 K25 MB_ADD14 MB_DATA13 B17 M_B_DQ13 15
MA_DATA15 F19 M_A_DQ15 14 15 M_B_A15 K24 MB_ADD15 MB_DATA14 B19 M_B_DQ14 15
14 M_A_BS0 U24 MA_BANK0 MB_DATA15 C19 M_B_DQ15 15
14 M_A_BS1 U21 MA_BANK1 MA_DATA16 H20 M_A_DQ16 14 15 M_B_BS0 U27 MB_BANK0
14 M_A_BS2 L23 MA_BANK2 MA_DATA17 F21 M_A_DQ17 14 15 M_B_BS1 T28 MB_BANK1 MB_DATA16 C21 M_B_DQ16 15
MA_DATA18 J23 M_A_DQ18 14 15 M_B_BS2 K28 MB_BANK2 MB_DATA17 B22 M_B_DQ17 15
14 M_A_DM0 E14 MA_DM0 MA_DATA19 H23 M_A_DQ19 14 MB_DATA18 C23 M_B_DQ18 15
14 M_A_DM1 J17 MA_DM1 MA_DATA20 G20 M_A_DQ20 14 15 M_B_DM0 D14 MB_DM0 MB_DATA19 A24 M_B_DQ19 15
14 M_A_DM2 E21 MA_DM2 MA_DATA21 E20 M_A_DQ21 14 15 M_B_DM1 A18 MB_DM1 MB_DATA20 D20 M_B_DQ20 15
14 M_A_DM3 F25 MA_DM3 MA_DATA22 G22 M_A_DQ22 14 15 M_B_DM2 A22 MB_DM2 MB_DATA21 B21 M_B_DQ21 15
14 M_A_DM4 AD27 MA_DM4 MA_DATA23 H22 M_A_DQ23 14 15 M_B_DM3 C25 MB_DM3 MB_DATA22 E23 M_B_DQ22 15
14 M_A_DM5 AC23 MA_DM5 15 M_B_DM4 AF25 MB_DM4 MB_DATA23 B23 M_B_DQ23 15
14 M_A_DM6 AD19 MA_DM6 MA_DATA24 G24 M_A_DQ24 14 15 M_B_DM5 AG22 MB_DM5
14 M_A_DM7 AC15 MA_DM7 MA_DATA25 E25 M_A_DQ25 14 15 M_B_DM6 AH18 MB_DM6 MB_DATA24 E24 M_B_DQ24 15
MA_DATA26 G27 M_A_DQ26 14 15 M_B_DM7 AD14 MB_DM7 MB_DATA25 B25 M_B_DQ25 15
14 M_A_DQS0 G14 MA_DQS_H0 MA_DATA27 G26 M_A_DQ27 14 MB_DATA26 B27 M_B_DQ26 15
14 M_A_DQS#0 H14 MA_DQS_L0 MA_DATA28 F23 M_A_DQ28 14 15 M_B_DQS0 C15 MB_DQS_H0 MB_DATA27 D28 M_B_DQ27 15
14 M_A_DQS1 G18 MA_DQS_H1 MA_DATA29 H24 M_A_DQ29 14 15 M_B_DQS#0 B15 MB_DQS_L0 MB_DATA28 B24 M_B_DQ28 15
14 M_A_DQS#1 H18 MA_DQS_L1 MA_DATA30 E28 M_A_DQ30 14 15 M_B_DQS1 E18 MB_DQS_H1 MB_DATA29 D24 M_B_DQ29 15
14 M_A_DQS2 J21 MA_DQS_H2 MA_DATA31 F27 M_A_DQ31 14 15 M_B_DQS#1 D18 MB_DQS_L1 MB_DATA30 D26 M_B_DQ30 15
14 M_A_DQS#2 H21 MA_DQS_L2 15 M_B_DQS2 E22 MB_DQS_H2 MB_DATA31 C27 M_B_DQ31 15
14 M_A_DQS3 E27 MA_DQS_H3 MA_DATA32 AB28 M_A_DQ32 14 15 M_B_DQS#2 D22 MB_DQS_L2
14 M_A_DQS#3 E26 MA_DQS_L3 MA_DATA33 AC27 M_A_DQ33 14 15 M_B_DQS3 B26 MB_DQS_H3 MB_DATA32 AG26 M_B_DQ32 15
C AE26 AD25 A26 AH26 C
14 M_A_DQS4 MA_DQS_H4 MA_DATA34 M_A_DQ34 14 15 M_B_DQS#3 MB_DQS_L3 MB_DATA33 M_B_DQ33 15
14 M_A_DQS#4 AD26 MA_DQS_L4 MA_DATA35 AA24 M_A_DQ35 14 15 M_B_DQS4 AG24 MB_DQS_H4 MB_DATA34 AF23 M_B_DQ34 15
14 M_A_DQS5 AB22 MA_DQS_H5 MA_DATA36 AE28 M_A_DQ36 14 15 M_B_DQS#4 AG25 MB_DQS_L4 MB_DATA35 AG23 M_B_DQ35 15
14 M_A_DQS#5 AA22 MA_DQS_L5 MA_DATA37 AD28 M_A_DQ37 14 15 M_B_DQS5 AG21 MB_DQS_H5 MB_DATA36 AG27 M_B_DQ36 15
14 M_A_DQS6 AB18 MA_DQS_H6 MA_DATA38 AB26 M_A_DQ38 14 15 M_B_DQS#5 AF21 MB_DQS_L5 MB_DATA37 AF27 M_B_DQ37 15
14 M_A_DQS#6 AA18 MA_DQS_L6 MA_DATA39 AC25 M_A_DQ39 14 15 M_B_DQS6 AG17 MB_DQS_H6 MB_DATA38 AH24 M_B_DQ38 15
14 M_A_DQS7 AA14 MA_DQS_H7 15 M_B_DQS#6 AG18 MB_DQS_L6 MB_DATA39 AE24 M_B_DQ39 15
14 M_A_DQS#7 AA15 MA_DQS_L7 MA_DATA40 Y23 M_A_DQ40 14 15 M_B_DQS7 AH14 MB_DQS_H7
MA_DATA41 AA23 M_A_DQ41 14 15 M_B_DQS#7 AG14 MB_DQS_L7 MB_DATA40 AE22 M_B_DQ40 15
14 M_A_DIM0_CLK_DDR0 T21 MA_CLK_H0 MA_DATA42 Y21 M_A_DQ42 14 MB_DATA41 AH22 M_B_DQ41 15
14 M_A_DIM0_CLK_DDR#0 T22 MA_CLK_L0 MA_DATA43 AA20 M_A_DQ43 14 15 M_B_DIM0_CLK_DDR0 R26 MB_CLK_H0 MB_DATA42 AE20 M_B_DQ42 15
14 M_A_DIM0_CLK_DDR1 R23 MA_CLK_H1 MA_DATA44 AB24 M_A_DQ44 14 15 M_B_DIM0_CLK_DDR#0 R27 MB_CLK_L0 MB_DATA43 AH20 M_B_DQ43 15
14 M_A_DIM0_CLK_DDR#1 R24 MA_CLK_L1 MA_DATA45 AD24 M_A_DQ45 14 15 M_B_DIM0_CLK_DDR1