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5 4 3 2 1
VITAS Block Diagram Project code :
91.4I501.001
VGA DC/DC
SC421A
SYSTEM DC/DC
INPUTS
TPA51125
OUTPUTS
INPUTS OUTPUTS
PCB P/N : 07263 +5VALW
+5VALW VGA_CORE_S0 42 DCBATOUT
Intel CPU Revision : SC +3VALW
+3VL
38
D
Penryn SV SYSTEM DC/DC D
Clock Generator APL5913 SYSTEM DC/DC
4X64MB TPS51116
ICS9LPRS355 3,4,5
16 DDRII 47,48 INPUTS OUTPUTS
INPUTS OUTPUTS
+1.8V +1.1VS 42
FSB +0.9VS
DCBATOUT
800/1066MHz +1.8V
39
14
CRT
DDRII
RGB CRT
1600X1200@75 SYSTEM DC/DC
Slot 0 DDRII 667/800 Channel A Cantiga-PM nVIDIA SC412A
667/800 12
LCD
AGTL+ CPU I/F DDR I/F LVDS(Dual Channel) INPUTS OUTPUTS
INTEGRATED GRAHPICS NB9M-GE WXGA+ 15
DDRII DDR II 667/800 Channel B PCIE x 16 +5VALW +1.05V
Slot 1 44,45,46 40
667/800 13
LVDS, CRT I/F
6,7,8,9,10,11
HDMI HDMI
26 MAXIM CHARGER
MAX8731
C
DMIx4 C-LINK INPUTS OUTPUTS C
BT+
WEBCAM DCBATOUT 18V 3.0A
15 5V 100mA
34
SD/MMC Realtek INTEL BLUETOOTH
MS/MS Pro/xD RTS5158
USB 2.0 22 CPU DC/DC
25 25
ICH9-M USB 2.0 USB x 3
ISL6260CCRZ
22
Realtek INPUTS OUTPUTS
RJ45 12 USB 2.0/1.1 ports
RTL8101-GR PCIE
CONN ETHERNET (10/100/1000Mb) +VCC_CORE
27 10/100 23 SATA HDD DCBATOUT
High Definition Audio 22 0.844~1.3V
4 SATA ports 22A
6 PCIE ports 36,37
AMOM
ACPI 1.1
ODD
RJ11 MODEM 22
B
CONN CX20548-11Z HD AUDIO LPC I/F
LPC Bus
PCB LAYER B
28
PCI/PCI BRIDGE SYSTEM DC/DC
G972 L1: Signal 1
HD AUDIO 17,18,19,20,21
CODEC INPUTS OUTPUTS L2: GND
LINE OUT
CX20561-14Z 41
28 KBC +1.8VS +1.5VS L3: Signal 2
PCIE+USB 2.0
SPI WINBOND L4: Signal 3
MIC IN WPCE775L 30
L5: VCC
INTERNAL MIC
L6: Signal 4
Thermal L7: GND
Mini-Card Flash ROM Touch Int.
OP AMP & Fan
802.11a/b/g/n 2MB PAD KB L8: Signal 5
GMT G1431 26 32 31 31
GMT G7921
24
A
29 A
2CH SPEAKER
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Block Diagram
Size Document Number Rev
A3
VITAS SA
Date: Monday, May 05, 2008 Sheet 1 of 48
5 4 3 2 1
A B C D E
ICH9M Functional Strap Definitions ICH9 Integrated pull-up Cantiga chipset and ICH9M I/O controller
ICH9 EDS 642879 Rev.1.5 page 92
and pull-down Resistors Hub strapping configuration
Signal Usage/When Sampled Comment
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3
ICH9 EDS 642879 Rev.1.5 Montevina Platform Design guide 22339 0.5 page 218
PCIE Port Config1 bit1, pulled low. When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value Pin Name Strap Description Configuration
Rising Edge of PWROK. of PWROK, sets bit1 of RPC.PC (Cofig Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency Select 000 = FSB1067
offset 224h). This signal has weak internal 011 = FSB667
pull-down. CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0, This signal has a weak internal pull-down.
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
Rising Edge of PWROK. Sets bit0 of PRC.PC (Config Registers: Offset DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
224h). CFG[15:14]
ENERGY_DETECT PULL-UP 20K CFG[18:17]
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. HDA_BIT_CLK PULL-DOWN 20K CFG5 DMI x2 Select 0 = DMI x2
GPIO53 Rising Edge of PWROK. Sets bit2 of PRC.PC2 (Config Registers: Offset 1 = DMI x4 (Default)
224h). HDA_DOCK_EN#/GPIO33 PULL-UP 20K
CFG6 iTPM Host Interface 0 = The iTPM Host Interface is enabled (Note 2)
HDA_RST# PULL-DOWN 20K 1 = The iTPM Host Interface is disabled (default)
GPIO20 Reserved. This signal should not be pulled high.
HDA_SDIN[3:0] PULL-DOWN 20K CFG7 Intel Management 0 = Transport Layer Security (TLS) cipher
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. engine crypto strap suite with no confidentiality
GPIO51 Rising Edge of PWROK. This signal should not be pulled low for desktop HDA_SDOUT PULL-DOWN 20K 1 = TLS cipher suite with confidentiality(Default)
and mobile. HDA_SYNC PULL-DOWN 20K CFG9 PCIE Graphics Lane 0 = Reserved Lanes, 15->0, 14->1 ect..
1 = Normal operation (Default): Lane Numbered in
GNT3#/ Top-Block Swap Sampled low: Top-Block Swap mode (inverts A16 for GLAN_DOCK# The pull-up or pull-down Order
GPIO55 override. Rising Edge all cycles targeting FWH BIOS space). active when configured
of PWROK. Note: Software will not be able to clear the for native GLAN_DOCK# CFG10 PCIE Loopback enable 0 = Enable (Note 3)
1 = Disable (Default)
Top-Swap bit until the system is rebooted functionality and determined
without GNT3# being pulled down. by LAN controller. CFG[13:12] XOR/ALL 00 = Reserve
10 = XOR mode Enabled
01 = ALLZ mode Enable (Note 3)
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K 11 = Disabled (Default)
SPI_CS1#/ Selection 0:1. (Config Registers: Offset 3410h:bit 11:10).
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC GPIO20 PULL-DOWN 20K CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
3 1 = Dynamic ODT Enabled (Default) 3
GPIO49 PULL-UP 20K
SPI_MOSI Integrated TPM Enable, Sample low: the Integrated TPM will be disable. CFG19 DMI Lane Reversal 0 = Normal operation (Default): Lane Numbered in
Rising Edge of CLPWROK. Sample high: the MCH TPM enable strap is sampled LDA[3:0]#/FHW[3:0]# PULL-UP 20K Order
low and the TPM Disable bit is clear, the 1 = Reverse Lanes
LAN_RXD[2:0] PULL-UP 20K DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)
Integrated TPM will be enable. DMI x2 mode [MCH->ICH]: (3->0, 2->1)
LDRQ[0] PULL-UP 20K
GPIO49 DMI Termination The signal is required to be low for desktop CFG20 Digital Display Port 0 = Only Digital Display Port or PCIE is
Voltage. Rising Edge applications and required to be high for mobile LDRQ[1]/GPIO23 PULL-UP 20K (SDVO/DP/iHDMI) operational (Default)
of CLPWROK. applications. PME# PULL-UP 20K
and PCIe are
Concurrent with PCIe 1 = Digital display Port the PEG port operating
simulataneously via
SATALED# PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K SDVO SDVO Present 0 = No SDVO Card Present (Default)
Reversal. Rising Edge of MPC.LR (Device 28: Function 0:Offset D8). _CTRLDATA 1 = SDVO Card Present
of PWROK. SATALED# PULL-UP 15K
L_DDC_DATA Local Flat Panel (LFP) =
0 LFP Disabled (Default)
SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Present 1 = LFP Card Present; PCIE disabled
No Reboot. If sampled high, the system is strapped to the
SPKR Rising Edge of PWROK. "No Reboot" mode (ICH9 will disable the TCO Timer SPI_MOSI PULL-DOWN 20K
system reboot feature). The status is readable NOTE:
SPI_MISO PULL-UP 20K
via the NO REBOOT bit. 1. All strap signals are sampled with respect to the leading edge of the (G)MCH
SPKR PULL-DOWN 20K Power OK (PWROK) signal.
XOR Chain Entrance. This signal should not be pull low unless using 2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of
TP3 Rising Edge of PWROK. XOR Chain testing. TACH_[3:0] PULL-UP 20K
the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6.
GPIO33/ Flash Descriptor Sampled low: the Flash Descriptor Security will be TP[3] PULL-UP 20K Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
HDA_DOCK Security Override overridden. If high, the security measures will be
2 _EN# Strap. Rising Edge of in effect. This should only be enabled in USB[11:0][P,N] PULL-DOWN 15K 2
PWROK. manufacturing environments using an external
pull-up resister.
SMBus
PCIE Routing page 19 USB Table page 19
USB Thermal
Pair Device
KBC
LANE1 LAN 0 USB3
1 FREE
LANE2 MiniCard WLAN 2 External USB3 BATTERY
3 FREE
4 External USB2
5 FREE
MINI
6 WLAN
1 7 BLUETOOTH ICH9M 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
8 CARD_READER Taipei Hsien 221, Taiwan, R.O.C.
9 FREE Title
10 CAMERA Table of Content
Clock Size Document Number Rev
11 FREE
Generator A3
VITAS SA
Date: Monday, May 05, 2008 Sheet 2 of 48
5 4 3 2 1
H_A#[35..3]
6 H_A#[35..3]
Reserve for ITP, when
U65A 1 OF 4
install ITP connector,
H_A#3 J4 H1 H_ADS# 6
install R338.
H_A#4 A3# ADS#
L5 A4# BNR# E2 H_BNR# 6
H_A#5 L4 G5 H_BPRI# 6
A5# BPRI#
ADDR GROUP 0
H_A#6 K5
H_A#7 A6# +1.05VS
M3 A7# DEFER# H5 H_DEFER# 6
H_A#8 N2 F21
CONTROL
A8# DRDY# H_DRDY# 6
D H_A#9
H_A#10
J1
N3
A9# DBSY# E1 H_DBSY# 6 D
A10#
1
H_A#11 P5 F1 H_BREQ#0 6
H_A#12 A11# BR0# 56R2J-4-GP R338
H_A#13
P2 A12# DY 51R2F-2-GP
L2 A13# IERR# D20 CPU_IERR# 1 2 R49 +1.05VS
H_A#14 P4 B3 H_INIT# 18
H_A#15 A14# INIT#
P1
2
H_A#16 A15#
R1 A16# LOCK# H4 H_LOCK# 6
6 H_ADSTB#0 M1 ADSTB0# H_CPURST# 6
6 H_REQ#[4..0] RESET# C1 H_RS#[2..0] 6
H_REQ#0 K3 F3 H_RS#0
H_REQ#1 H2 REQ0# RS0# H_RS#1
REQ1# RS1# F4
H_REQ#2 K2 G3 H_RS#2
H_REQ#3 J3 REQ2# RS2#
REQ3# TRDY# G2 H_TRDY# 6
H_REQ#4 L1
REQ4#
G6
1218
HIT# H_HIT# 6
H_A#17 Y2 E4 H_HITM# 6
H_A#18 A17# HITM#
U5 A18#
H_A#19 R3 AD4 XDP_BPM#0
H_A#20 A19# BPM0# XDP_BPM#1
W6 AD3
XDP/ITP SIGNALS
A20# BPM1#
H_A#21
H_A#22
U4
Y5
A21# ADDR GROUP 1 BPM2# AD1
AC4
XDP_BPM#2
XDP_BPM#3
H_A#23 A22# BPM3# XDP_BPM#4
U1 A23# PRDY# AC2
H_A#24 R4 AC1 XDP_BPM#5
A24# PREQ#
H_A#25 T5 A25# TCK AC5 XDP_TCK H_THERMDA, H_THERMDC routing together,
H_A#26 T3 AA6 XDP_TDI
H_A#27 W2
A26# TDI
AB3 XDP_TDO Trace width / Spacing = 10 / 10 mil
H_A#28 A27# TDO XDP_TMS
W5 A28# TMS AB5
H_A#29 Y4 AB6 XDP_TRST# Connect to V Core
A29# TRST#
C H_A#30
H_A#31
U2
V4
A30# DBR# C20 XDP_DBRESET#_R 4/23 Houston
C
H_A#32 A31#
W3 A32# CPU_PROCHOT#_R 36
H_A#33 AA4 THERMAL
H_A#34 A33#
AB2 A34# 1 2 +1.05VS
H_A#35 AA3 D21 R47 68R2-GP
A35# PROCHOT#
6 H_ADSTB#1 V1 ADSTB1# THRMDA A24 H_THERMDA 24
THRMDC B25 H_THERMDC 24
18 H_A20M# A6 A20M#
18 H_FERR# A5 FERR# THERMTRIP# C7 PM_THRMTRIP-A# 7,18
ICH
ICH
18 H_IGNNE# C4
D5
IGNNE#
ITP Connector
18 H_STPCLK# STPCLK#
18 H_INTR C6 LINT0 HCLK BCLK0 A22 CLK_CPU_BCLK 16
18 H_NMI B4 LINT1 BCLK1 A21 CLK_CPU_BCLK# 16
18 H_SMI# A3 SMI# PM_THRMTRIP#
TPAD30 TP65 RSVD_CPU_1 M4 should connect to +1.05VS Reserve for ITP
TPAD30 TP61 RSVD_CPU_2 RSVD#M4 ICH9 and MCH
N5 RSVD#N5
TPAD30 TP66 RSVD_CPU_3 T2 without T-ing
RESERVED
TPAD30 TP64 RSVD_CPU_4 RSVD#T2 ( No stub)
V3 RSVD#V3 1012 DB
1
TPAD30 TP73 RSVD_CPU_5 B2 R97
RSVD#B2 C271
TEST7
0R2J-2-GP
TPAD30 TP70 RSVD_CPU_6 C3 DY DY
TPAD30 TP69 RSVD_CPU_7 RSVD#C3
D2 RSVD#D2 2 1
TPAD30 TP59 RSVD_CPU_8 D22 ITP1
TPAD30 TP72 RSVD_CPU_9 RSVD#D22
D3 1012 DB
2
TPAD30 TP60 RSVD_CPU_10 RSVD#D3 SCD1U16V2KX-3GP
F6 RSVD#F6 29 30
+1.05VS 1
TPAD30 TP74 RSVD_CPU_11 B1 2 +1.05VS
KEY_NC ITP_VDD R73
3
B BGA479-SKT6-GPU6 5 4 XDP_DBRESET#_R 1 DY 2 0R2J-2-GP XDP_DBRESET#
XDP_DBRESET# 19
B
62.10079.001 7 6 XDP_BPM#0
9 8 XDP_BPM#1 1 DY 2 R74 0R2J-2-GP
XDP_BPM#2 MCH_CLKSEL2 7,16
11 10 1 DY 2 R75 0R2J-2-GP
MCH_CLKSEL1 7,16
1012 DB 13 12 XDP_BPM#3 1 DY 2 R76 0R2J-2-GP
XDP_BPM#4 MCH_CLKSEL0 7,16
H_CPURST#
DY 15 14