Text preview for : compal_la-6421p_r1.0_schematics.pdf part of acer compal la-6421p r1.0 schematics acer Netbook Нетбук Acer Aspire One AOHAPPY compal_la-6421p_r1.0_schematics.pdf
Back to : compal_la-6421p_r1.0_sche | Home
A B C D E
1 1
Compal Confidential
2 2
PAV70 DDR3 Schematics Document
Intel Pineview Processor with Tigerpoint + DDRIII
3
2010-06-25 3
REV: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6421P
Date: Friday, June 25, 2010 Sheet 1 of 39
A B C D E
A B C D E
Clock Generator
Compal Confidential CK505 page 8
Model Name : PAV50
File Name : LA-6421P CRT Conn
page 10
1 ZZZ 1
RGB
Memory BUS(DDRIII) DDRIII-SO-DIMM
PCB
Pineview page 7
DA60000I610
LCD Conn. LVDS FCBGA 559 1.5V DDRIII 667
page 9 22x22mm
Thermal Sensor page 4,5,6
EMC1402
page 5
DMI
X2 mode
GEN1
PCI-Express USB USB Port x2(L)
2
Tigerpoint HDA page 20
2
PCBGA360 SATA BlueTooth
LPC BUS
page 15
TPM 17x17mm
page 27
page 11,12,13,14
MINI Card x1 10/100 Ethernet CMOS CAM
WLAN HDD page 9
3G page 15 page 26
AR8152
page 16
page 25
3G
page 15
Transfermer LPC BUS
USB Port x1(R)
3 3
page 20
Aralia Codec
RJ45
ALC272 page 22
Power ON/OFF DC/DC Interface Card Reader
page 29
ENE6252
page 18
3VALW/5VALW Int.KBD ENE KBC SPI page 25
page 33
page 19
DC IN
page 30
KB926
page 17
1.5VP/VCCP
page 34 AMP & INT INT MIC HeadPhone & SD/MMC/MS
BATT IN MIC Jack
page 31 Speaker CONN
0.89VP/1.8VP SPI ROM
page 17
CHARGER 0.75VS Light Sensor Touch Pad
page 32
4
page 35 page27 page19 4
CPU_CORE
page 36
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6421P
Date: Friday, June 25, 2010 Sheet 2 of 39
A B C D E
A B C D E
1 1
Voltage Rails External PCI Devices
Power Plane Description S1 S3 S5 DEVICE IDSEL # REQ/GNT # PIRQ
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.5V 1.5V power rail for DDR ON ON OFF
+0.89V Graphic core power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
2
+5VS 5V switched power rail ON OFF OFF 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON EC SM Bus1 address EC SM Bus2 address
Device Address Device Address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Smart Battery 0001 011X b EMC1402 100_1100
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
3
ICH7M SM Bus address 3
BOARD ID Table(Page 17) Device Address
Clock Generator 1101 001Xb
VCC 3.3V (SLG8SP556VTR)
Ra 100K DDR DIMMA 1010 000Xb
ID BRD ID Rb Vab-Min Vab-Typ Vab-Max
0 R01 (EVT) 0 0V 0V 0V
1 R02 (DVT) 8.2K 0.216V 0.250V 0.289V
PAV50
2 R03 (PVT) 18K 0.436V 0.503V 0.538V
3 R10A (MP) 33K 0.712V 0.819V 0.875V
4 R01 (EVT) 56K 1.036V 1.185V 1.264V
5 R02 (DVT) 100K 1.453V 1.650V 1.759V
6 R03 (PVT) 200K 1.935V 2.200V 2.341V
7 R10A (MP) NC 2.500V 3.3V 3.3V
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6421P
Date: Monday, May 03, 2010 Sheet 3 of 39
A B C D E
5 4 3 2 1
(7) DDR_A_DQS#[0..7]
PINEVIEW_M
U71
PINEVIEW_M
N475@ (7) DDR_A_D[0..63] N475@
U71A U71B
REV = 1.1
(7) DDR_A_DM[0..7]
REV = 1.1 DDR_A_MA0 AH19 AD3 DDR_A_DQS0
DMI_RX0_R (7) DDR_A_DQS[0..7] DDR_A_MA1 DDR_A_MA_0 DDR_A_DQS_0 DDR_A_DQS#0
F3 DMI_RXP_0 DMI_TXP_0 G2 DMI_TX0 (13) AJ18 DDR_A_MA_1 DDR_A_DQS#_0 AD2
N455@ DMI_RX#0_R F2 G1 DMI_TX#0 (13) DDR_A_MA2 AK18 AD4 DDR_A_DM0
DMI_RX1_R DMI_RXN_0 DMI_TXN_0 (7) DDR_A_MA[0..14] DDR_A_MA3 DDR_A_MA_2 DDR_A_DM_0
H4 DMI_RXP_1 DMI_TXP_1 H3 DMI_TX1 (13) AK16 DDR_A_MA_3
DMI_RX#1_R G3 J2 DMI_TX#1 (13) DDR_A_MA4 AJ14 AC4 DDR_A_D0
DMI_RXN_1 DMI_TXN_1 DDR_A_MA5 DDR_A_MA_4 DDR_A_DQ_0 DDR_A_D1
AH14 AC1
DMI
DDR_A_MA6 DDR_A_MA_5 DDR_A_DQ_1 DDR_A_D2
AK14 AF4
DDR_A_MA7 DDR_A_MA_6 DDR_A_DQ_2 DDR_A_D3
AJ12 AG2
DDR_A_MA8 DDR_A_MA_7 DDR_A_DQ_3 DDR_A_D4
AH13 DDR_A_MA_8 DDR_A_DQ_4 AB2
D DDR_A_MA9 DDR_A_D5 D
AK12 AB3
DDR_A_MA10 DDR_A_MA_9 DDR_A_DQ_5 DDR_A_D6
(8) CLK_CPU_EXP# N7 EXP_CLKINN EXP_RCOMPO L10 AK20 DDR_A_MA_10 DDR_A_DQ_6 AE2
N6 L9 R162 DDR_A_MA11 AH12 AE3 DDR_A_D7
(8) CLK_CPU_EXP EXP_CLKINP EXP_ICOMPI DDR_A_MA_11 DDR_A_DQ_7
L8 R203 49.9_0402_1% DDR_A_MA12 AJ11
EXP_RBIAS 750_0402_1% DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
R10 AJ24 AB8
EXP_TCLKINN DDR_A_MA14 DDR_A_MA_13 DDR_A_DQS_1 DDR_A_DQS#1
R9 N11 T38 AJ10 AD7
EXP_TCLKINP RSVD_TP DDR_A_MA_14 DDR_A_DQS#_1 DDR_A_DM1
N10 RSVD RSVD_TP P11 T39 Must be placed within 500 mils from Pineview-M pins DDR_A_DM_1 AA9
N9 RSVD DDR_A_WE# AK22 AB6 DDR_A_D8
(7) DDR_A_WE# DDR_A_WE# DDR_A_DQ_8
U71 DDR_A_CAS# AJ22 AB7 DDR_A_D9
(7) DDR_A_CAS# DDR_A_CAS# DDR_A_DQ_9
DDR_A_RAS# AK21 AE5 DDR_A_D10
(7) DDR_A_RAS# DDR_A_RAS# DDR_A_DQ_10 DDR_A_D11
K2 K3 AG5
RSVD RSVD DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
J1 L2 (7) DDR_A_BS0 AJ20 AA5
RSVD RSVD DDR_A_BS1 DDR_A_BS_0 DDR_A_DQ_12 DDR_A_D13
M4 RSVD RSVD M2 (7) DDR_A_BS1 AH20 DDR_A_BS_1 DDR_A_DQ_13 AB5
L3 N2 DDR_A_BS2 AK11 AB9 DDR_A_D14
RSVD RSVD (7) DDR_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
N550@ AD6 DDR_A_D15
DDR_A_DQ_15
1 OF 6 DDR_A_DQS2
PINEVIEW-M_FCBGA8559 AD8
DDR_CS#0 DDR_A_DQS_2 DDR_A_DQS#2
(7) DDR_CS#0 AH22 AD10
DDR_CS#1 DDR_A_CS#_0 DDR_A_DQS#_2 DDR_A_DM2
(7) DDR_CS#1 AK25 DDR_A_CS#_1 DDR_A_DM_2 AE8
JP16 AJ21
XDP_PREQ# CONN@ DDR_A_CS#_2 DDR_A_D16
(5) XDP_PREQ# 1 1 AJ25 DDR_A_CS#_3 DDR_A_DQ_16 AG8
(5) XDP_PRDY# XDP_PRDY# 2 AG7 DDR_A_D17
2 DDR_CKE0 DDR_A_DQ_17 DDR_A_D18
3 (7) DDR_CKE0 AH10 AF10
XDP_BPM#3 3 DDR_CKE1 DDR_A_CKE_0 DDR_A_DQ_18 DDR_A_D19
(5) XDP_BPM#3 4 4 (7) DDR_CKE1 AH9 DDR_A_CKE_1 DDR_A_DQ_19 AG11
(5) XDP_BPM#2 XDP_BPM#2 5 AK10 AF7 DDR_A_D20
5 DDR_A_CKE_2 DDR_A_DQ_20 DDR_A_D21
6 6 AJ8 DDR_A_CKE_3 DDR_A_DQ_21 AF8
C435 DMI_RX0_R XDP_BPM#1 7 AD11 DDR_A_D22
(13) DMI_RX0 1 2 (5) XDP_BPM#1 7 DDR_A_DQ_22
0.1U_0402_10V7K (5) XDP_BPM#0 XDP_BPM#0 8 M_ODT0 AK24 AE10 DDR_A_D23
8 (7) M_ODT0 M_ODT1 DDR_A_ODT_0 DDR_A_DQ_23
9 (7) M_ODT1 AH26
C436 DMI_RX#0_R R354 1 @ 1K_0402_5% 9 DDR_A_ODT_1 DDR_A_DQS3
(13) DMI_RX#0 1 2 (5,13) H_PWRGD 2 10 10 AH24 DDR_A_ODT_2 DDR_A_DQS_3 AK5
R347 1 @2 1K_0402_5% 11 AK27 AK3 DDR_A_DQS#3
C 0.1U_0402_10V7K (13) SLPIOVR# 11 DDR_A_ODT_3 DDR_A_DQS#_3 C
12 AJ3 DDR_A_DM3
C437 (8) CPU_ITP 12 DDR_A_DM_3
1 2 DMI_RX1_R (8) CPU_ITP# 13
(13) DMI_RX1 13 DDR_A_D24
0.1U_0402_10V7K +VCCP 14 AH1
PLTRST# 1 R348 @2 1K_0402_1% 14 M_CLK_DDR0 DDR_A_DQ_24 DDR_A_D25
C438 (5,13,15,17,25,26,27) PLTRST# 15 15 (7) M_CLK_DDR0 AG15 DDR_A_CK_0 DDR_A_DQ_25 AJ2
(13) DMI_RX#1 1 2 DMI_RX#1_R 16 M_CLK_DDR#0 AF15 AK6 DDR_A_D26
16 (7) M_CLK_DDR#0 M_CLK_DDR1 DDR_A_CK_0# DDR_A_DQ_26 DDR_A_D27
0.1U_0402_10V7K 17 17 (7) M_CLK_DDR1 AD13 DDR_A_CK_1 DDR_A_DQ_27 AJ7
(5) XDP_TDO XDP_TDO 18 M_CLK_DDR#1 AC13 AF3 DDR_A_D28
XDP_TRST# 18 (7) M_CLK_DDR#1 DDR_A_CK_1#