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A B C D E
1 1
Compal Confidential
2 2
PEW71/91/51 M/B Schematics Document
Intel Arrandale Processor with DDRIII + Ibex Peak-M
NV N11P-GV2H and N11P-GE
3 2010-06-07 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 1 of 56
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A B C D E
Clock Generator
Compal Confidential IDT: 9LVS3199AKLFT
Realtek: RTM890N-631-VB-GRT
Model Name : NEW71/91 133/120/100/96/14.318MHZ to PCH
File Name : LA5893P Fan Control
page 41 page 12
1 1
100MHz PCI-E 2.0x16 5GT/s PER LANE
PEG(DIS) Intel Memory BUS(DDRIII)
NV N11P-GV2H 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
NV N11P-GE BANK 0, 1, 2, 3 page 10,11
page
Arrandale (UMA/DIS) 1.5V DDRIII 800/1066
22,23,24,25,26,27
LVDS(DIS) Processor
rPGA988A
page 4,5,6,7,8,9
HDMI(DIS) CRT(DIS)
FDI x8 DMI x4 USB conn x3 Bluetooth CMOS Camera Card Reader
(UMA) USB port 1 Conn RTS5160
USB port 0, 2 on USB port 11 USB port 8 USB port 9
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz USB/B page 35 page 35 page 28 page 35
page 30 page 29 page 28 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2
HDMI(UMA) LVDS(UMA)
CRT(UMA) Intel 3.3V 24MHz
HDMI HD Audio
Level Shift TMDS(UMA) Ibex Peak-M
page 30
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz PCH HDA Codec
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz page 13,14,15,16 ALC272X
port 2 port 1 17,18,19,20,21
SPI page 39
MINI Card x2 LAN(GbE)
WLAN, WWAN
USB port 12,13
BCM57780
page 34 page 32 SPI ROM x1 Audio AMP
port 0 port 1 TI TPS6017 40
page 13 page
SATA HDD SATA CDROM
Conn. page 31
Conn. page 31
3
RJ45 LPC BUS 3
page 33
33MHz
Int. Speaker Phone Jack x 2
Sub-board ENE KB926 page 40 page 40
page 36
LS-5891P
USB/B 2 Ports
RTC CKT. USB Port 0,2 page 35
page 15
Touch Pad Int.KBD
LS-5896P page 37 page 37
Card Reader
Power On/Off CKT. USB Port9 CPU XDP
page 38 RTS5160
page 35 page 5
EC ROM
page 37
DC/DC Interface CKT. LS-5893P LS-5894P PCH XDP
4
page 42
Power/B LID_SW/B 4
page 38 page 21
Power Circuit DC/DC LS-5895P
3G Security Classification Compal Secret Data Compal Electronics, Inc.
USB Port10,13 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
page 43~53 page 35 SCHEMATICS,MB A5893
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 2 of 56
A B C D E
A B C D E
Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+VGFX_CORE Core voltage for Arrandale GPU (only for arrandaleCPU) ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for ARD CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW +3VALW always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW_EC +3VALW always to KBC ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V +3VALW to +3V power rail for PCH (Short Jumper) ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS +3VALW to +3VS power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5V +5VALW to +5V switched power rail for PCH (Short resister) ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2 2
+5VS +5VALW to +5VS switched power rail ON OFF OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
BOARD ID Table BTO Option Table
+RTCVCC RTC power ON ON ON
BTO Item BOM Structure
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Board ID PCB Revision
UMA ONLY UMA ONLY@
0 0.1
EC SM Bus1 address EC SM Bus2 address Discrete DIS@
1 0.2
Discrete Only DIS ONLY@
2 0.3
Device Address Device Address VRAM X76@
3 1.0
Smart Battery 0001 011X b Switchable SG@
4
UMA ONLY & OPTIMUS UMOP@
PCH SM Bus address 5
3G 3G@
6
Blue Tooth BT@
Device Address 7
OPTIMUS OPT@
Clock Generator (9LVS3199AKLFT, 1101 0010b NonSG SKU NonSG@
RTM890N-631-VB-GRT)
DDR DIMM0 1001 000Xb USB Port Table NEW71 71@
NEW91 91@
DDR DIMM2 1001 010Xb 3 External
USB 2.0 USB 1.1 Port N11P-GV2H GV2H@
3
USB Port 3
N11P-GE1 GE1@
0 USB/B (Right Side)
UHCI0 N11P-GV2H-A2 GV2HA2@
1 USB Port (Left Side)
N11P-GV2H-A3 GV2HA3@
2 USB/B (Right Side)
UHCI1 Non OPT SKU NonOPT@
BOM Config move to page 56 EHCI1
UHCI2
3
4
SG or OPT SGOPT@
5
VRAM BOM Config 6
UHCI3
X7621@: X76198BOL21 ALT. GROUP PARTS 1G SAM 7
8 Camera
X7622@ X76198BOL22 ALT. GROUP PARTS 1G HYN UHCI4
9 Card Reader
10 SIM Card
EHCI2 UHCI5
11 Blue Tooth VRAM P/N :
12 Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!)
Mini Card(WLAN)
UHCI6 Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO! )
13 Mini Card(GPS)
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5893
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401869
Date: Wednesday, June 30, 2010 Sheet 3 of 56
A B C D E
5 4 3 2 1
JCPU1E
JCPU1A R485 AJ13
PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 49.9_0402_1% RSVD33 AJ12
DMI_PTX_HRX_N0
10mil PEG_ICOMPO A26
R493
A24 DMI_RX#[0] PEG_RCOMPO B27 AP25 RSVD1
DMI_PTX_HRX_N1 C23 A25 EXP_RBIAS 1 2 750_0402_1% AL25 AH25
DMI_PTX_HRX_N2 DMI_RX#[1] PEG_RBIAS RSVD2 RSVD34
DMI_PTX_HRX_N3
B22 DMI_RX#[2] 15mil PEG_GTX_C_HRX_N15
AL24 RSVD3 RSVD35 AK26
A21 DMI_RX#[3] PEG_RX#[0] K35 AL22 RSVD4
J34 PEG_GTX_C_HRX_N14 AJ33 AL26
DMI_PTX_HRX_P0 PEG_RX#[1] PEG_GTX_C_HRX_N13 RSVD5 RSVD36
B24 DMI_RX[0] PEG_RX#[2] J33 AG9 RSVD6 RSVD_NCTF_37 AR2
DMI_PTX_HRX_P1 D23 G35 PEG_GTX_C_HRX_N12 M27
DMI_RX[1] PEG_RX#[3] RSVD7
DMI
DMI_PTX_HRX_P2 B23 G32 PEG_GTX_C_HRX_N11 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10 RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 J17 SA_DIMM_VREF (CFD Only) RSVD39 AJ27 D
F31 PEG_GTX_C_HRX_N9 H17
DMI_HTX_PRX_N0 PEG_RX#[6] PEG_GTX_C_HRX_N8 SB_DIMM_VREF (CFD Only)
D24 DMI_TX#[0] PEG_RX#[7] D35 G25 RSVD11
DMI_HTX_PRX_N1 G24 E33 PEG_GTX_C_HRX_N7 G17
DMI_HTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6 RSVD12
F23 DMI_TX#[2] PEG_RX#[9] C33 E31 RSVD13 RSVD_NCTF_40 AP1
DMI_HTX_PRX_N3 H23 D32 PEG_GTX_C_HRX_N5 E30 AT2
DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N4 RSVD14 RSVD_NCTF_41
PEG_RX#[11] B32
DMI_HTX_PRX_P0 D25 C31 PEG_GTX_C_HRX_N3 AT3
DMI_HTX_PRX_P1 DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N2 RSVD_NCTF_42
F24 DMI_TX[1] PEG_RX#[13] B28 RSVD_NCTF_43 AR1
DMI_HTX_PRX_P2 E23 B30 PEG_GTX_C_HRX_N1
DMI_HTX_PRX_P3 DMI_TX[2] PEG_RX#[14] PEG_GTX_C_HRX_N0
G23 DMI_TX[3] PEG_RX#[15] A31
J35 PEG_GTX_C_HRX_P15 R58 AL28
PEG_RX[0] PEG_GTX_C_HRX_P14 3.01K_0402_1% @ CFG0 RSVD45
PEG_RX[1] H34 1 2 AM30 CFG[0] RSVD46 AL29
H33 PEG_GTX_C_HRX_P13 AM28 AP30
H_FDI_TXN0 PEG_RX[2] PEG_GTX_C_HRX_P12 R61 CFG[1] RSVD47
E22 FDI_TX#[0] PEG_RX[3] F35 AP31 CFG[2] RSVD48 AP32
H_FDI_TXN1 D21 G33 PEG_GTX_C_HRX_P11 3.01K_0402_1% 1 DIS@ 2 CFG3 AL32 AL27
H_FDI_TXN2 FDI_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P10 R60 @ CFG4 CFG[3] RSVD49
D19 FDI_TX#[2] PEG_RX[5] E34 1 2 AL30 CFG[4] RSVD50 AT31
H_FDI_TXN3 D18 F32 PEG_GTX_C_HRX_P9 3.01K_0402_1% AM31 AT32
H_FDI_TXN4 FDI_TX#[3] PEG_RX[6] PEG_GTX_C_HRX_P8 CFG[5] RSVD51
G21 FDI_TX#[4] PEG_RX[7] D34 AN29 CFG[6] RSVD52 AP33
H_FDI_TXN5 PEG_GTX_C_HRX_P7 R59 @ CFG7
H_FDI_TXN6
E19
F21
FDI_TX#[5]
FDI_TX#[6]
PCI EXPRESS -- GRAPHICS PEG_RX[8]
PEG_RX[9]
F33
B33 PEG_GTX_C_HRX_P6 3.01K_0402_1%
1 2 AM32
AK32
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54
AR33
AT33
Intel(R) FDI
H_FDI_TXN7 G18 D31 PEG_GTX_C_HRX_P5 AK31 AT34
RESERVED
FDI_TX#[7] PEG_RX[10] PEG_GTX_C_HRX_P4 CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 AK28 CFG[10] RSVD_NCTF_56 AP35
C30 PEG_GTX_C_HRX_P3 WW41 Recommend not pull down AJ28 AR35
H_FDI_TXP0 PEG_RX[12] PEG_GTX_C_HRX_P2 CFG[11] RSVD_NCTF_57
D22 FDI_TX[0] PEG_RX[13] A28 PCIE2.0 Jitter is over on ES1 AN30 CFG[12] RSVD58 AR32
H_FDI_TXP1 C21 B29 PEG_GTX_C_HRX_P1 AN32
H_FDI_TXP2 FDI_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0 CFG[13]
D20 FDI_TX[2] PEG_RX[15] A30 AJ32 CFG[14]
H_FDI_TXP3 C18 AJ29 E15
C H_FDI_TXP4 FDI_TX[3] PEG_HTX_GRX_N15 C586 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 CFG[15] RSVD_TP_59 C
G22 FDI_TX[4] PEG_TX#[0] L33 1 2 AJ30 CFG[16] RSVD_TP_60 F15
H_FDI_TXP5 E20 M35 PEG_HTX_GRX_N14 C561 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N14 AK30 A2
H_FDI_TXP6 FDI_TX[5] PEG_TX#[1] PEG_HTX_GRX_N13 C584 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N13 CFG[17] KEY R146
F20 FDI_TX[6] PEG_TX#[2] M33 1 2 H16 RSVD_TP_86 RSVD62 D15
H_FDI_TXP7 G19 M30 PEG_HTX_GRX_N12 C559 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N12 C15 0_0402_5%
FDI_TX[7] PEG_TX#[3] PEG_HTX_GRX_N11 C582 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N11 RSVD63 RSVD64_R 2 @
PEG_TX#[4] L31 1 2 RSVD64 AJ15 1
F17 K32 PEG_HTX_GRX_N10 C557 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N10 AH15 RSVD65_R 2 @ 1
15 H_FDI_FSYNC0 FDI_FSYNC[0] PEG_TX#[5] RSVD65
E17 M29 PEG_HTX_GRX_N9 C580 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N9 R147
15 H_FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 PEG_HTX_GRX_N8 C555 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N8 B19 0_0402_5%
PEG_TX#[7] PEG_HTX_GRX_N7 C578 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N7 R497 RSVD15
15 H_FDI_INT C17 FDI_INT PEG_TX#[8] K29 1 2 A19 RSVD16
H30 PEG_HTX_GRX_N6 C553 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N6 0_0402_5%
PEG_TX#[9] PEG_HTX_GRX_N5 C576 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N5 @ H_RSVD17_R
15 H_FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 1 2 1 2 A20 RSVD17
D17 F29 PEG_HTX_GRX_N4 C551 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N4 1 @ 2 H_RSVD18_R B20
15 H_FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11] RSVD18
E28 PEG_HTX_GRX_N3 C574 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N3 AA5
PEG_TX#[12] PEG_HTX_GRX_N2 C549 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N2 R501 RSVD_TP_66
PEG_TX#[13] D29