Text preview for : FH-X1-ICBLK.pdf part of LG FH-X1-ICBLK LG Audio FH-X1 FH-X1-ICBLK.pdf
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INTERNAL BLOCK DIAGRAM OF ICs
-_ n IC102(KB9223)
FDFCT
RF- Focus Phase
FE-
Interface Logic & Offset cancel circuit
RF0
FE0
PDI
I-
TDFCT
PD2
Focus Error Amp .
FE-BIASAdjustment
TE-
Tracking Phase TEO
F Compensation Block
Tracking Error Amp TE2
& Jump Pulse GEN. '
E E/F Balance & Gain
LPFT
- El MICOM TO SERVO CONTROL
TG2
AUTOSEQUENCER
PD TGU
SLO
LD
SL-
VR SL+
SPDLO
FSI to TM1 to BALl to PSI to GA1 to SPDL-
ARF
FS4 TM6 BAL5 PS4 GA5
IRF SMPD
- SMON
ASY
SMEF
EFM
FSET
RFI
MIRROR
MCP
DCB Built-in Post Filter Amp(L&R)
Defect Detection FOK DETECTION
CircuitT + CIRCUIT FOK
-18-
n IC103(KS9286)
.-
SQDT
REGISTER SQCK
DETECTOR
A
23BIT ' EFM
I
EFMI ' DEMODULATOR
--
CNTVOL
UlUl I AL
DPFIN DI I I, - IA
FRAME SYNC
DPFOUT
DPDO
SMEF
SMON
I DETECTOR
PROTECTOR
INSERTOR
I 16K
SRAM 4
SMDP
SMSD
LOCK
I X-TAL
4 ECC
4
XOUT (9)
TIMING
XIN (
I
83- + GENERATOR +I INTERPOLATOR '
LRCHO
ADATAO
I
BCKO
MDAT I )
TRACK
MCK
b COUNTER BCKI
MLT DIGITAL
4 I ADATAI
9 FILTER
LRCHI
TRCNT & DE-EMPH '
/ISTAT EMPH
I I
MODE VREFLI
SELECTOR VREFHI
-19-
04 (358D)
+ -
REGULATOR
f MUTE
1 M 4) LEVEL
SHIFT
+ -
--
- 20 -
INFORMATION OF ICs MI-COM
n IClOl KS57C0108
Pin No. Port Name. I/O Signal Name Meaning
1 P53 0 XRST CDP LSI Reset (L)
2 P52 Unused
3 P51 Unused \
\
4 P50 0 PLL - CTRL CDP LSI Power Control (H-On, L=Off) `i
5 RESET- I RESET- Micom Reset (L)
6 Xout - Osci I lator Output
7 Xin - Osci I lato Input
8 P63/KS3 0 MCLK CDP LSI CLK for Command TX
9 P62/KS2 0 MDATA CDP LSI Data for Command TX
IO PGl/KSl 0 MLAT CDP LSI Latch for Command TX
11 PGO/KSO 0 MUTE Mute
--
12 P73/KS7 Unused
13 P72/KS6 Unused
14 P71/KS5 Unused
15 P70/KS4 Unused
16 vss - GND GND
17 P13/INT4 Unused
18 P12/INT2 I SLEDSW Sled Limit S/W Detect
19 PI l/INTl I TRCNT Track Count Input
PlO/INTO I SCOR SCOR Input
-
20
21 P23/BUZ I KEY1 Key Signal Input 1
22 P22/CLO I KEY0 Key Signal Input 0
23 P21/TCLOl I SENS SENS Signal
24 P20/TCLOO I FOK Focus OK Signal
25 P03/BTCO Unused
26 PO2/S I I SUBQ Sub-Q Data
27 POl/SO I CLSSW Door Open/Close SW
--_
28 POO/SCK- 0 SQCK Sub-Q Clock for Data Read
29 P83 Unused
30 P82 Unused
31 P81 Unused
32 P80 Unused
33 NC - GND GND
34 NC - GND GND
35 P33 I GFS GFS Signal
36 P32 Unused
37 P31/TCLl l/O BUSY Receiver Communication Line - Busy Signal
38 P30/TCLO l/O SDATA Receiver Communication Line - Data Signal
39 VDD - VDD VDD
40 TEST - GND GND
41 P43 Unused
42 P42 0 KEY-C Key Scan Signal C
43 P41 0 KEY-B Key Scan Signal B
44 P40 0 KEY-A Key Scan Signal A
-2l-