Text preview for : PW166B data sheet.pdf part of Pixelworks PW166 Video Processor
Back to : PW166B data sheet.pdf | Home
Product Specification: PW166B ImageProcessor
XGA/SXGA/UXGA Flat Panel Display Controller IC
General
The PW166B ImageProcessor is a highly integrated "system-on-a-chip" that interfaces analog, digital, and video inputs in virtually any format to a digital projection system or multimedia display. The PW166B is pincompatible with the PW164. An embedded SDRAM frame buffer and memory controller perform frame rate conversion. Computer images from VGA to UXGA at almost any refresh rate can be resized to fit on a fixed-frequency target display device with any resolution up to UXGA with full 24-bit color. The PW166B includes advanced second generation image scaling that provides completely programmable, horizontal and vertical image scaling. Keystoning allows vertical keystoning effects. In addition, non-linear scaling is supported for precise scaling control, with 16:9 aspect ration sources and displays.This high-quality scaling-- coupled with Auto Image Optimization circuitry--provides sharp, full-screen images, centered on the screen, with no manual adjustments required. The PW166B also includes advanced second-generation sync decoding which provides full support for a wide variety of sync types. This includes interlaced, progressive, sync-on-green, and TMDS DE (Data Enable) only. The PW166B ImageProcessor supports NTSC or PAL video data with a 4:3 aspect ratio and 16:9 aspect ratio sources, such as DVD or HDTV. Nonlinear scaling and separate horizontal and vertical scalers allow these inputs to be resized optimally for the native resolution and aspect ratio of the display device. An integrated OSD controller provides bit-mapped based OSDs with 16 colors from a 64K color palette. The OSD controller supports transparent and translucent functions. The PW166B provides a Pulse Width Modulation (PWM) output for low cost backlight or audio control. With reference source code and an on-chip microprocessor, manufacturers can develop feature-rich products with rapid time-to-market. Programmable features include the user interface, custom start-up screen, all automatic imaging features, and special screen effects.
Com puter
ADC/ TMDS Clocks
PW166B
Video
Video Decoder
Display
PW166B System Block Diagram
ROM
Features
· · · · · · · · · · · Second-Generation Image Scaling Second-Generation Automatic Image Optimization Video Processing Picture-in-Picture (PIP) Frame Rate Conversion Multi-region, non-linear scaling Color Matrix for improved color temperature adjustment On-Screen Display On-Chip Microprocessor JTAG Debugging Port Hardware PWM Output
Applications
· · · · LCD Monitors Plasma Display Projection Displays Multimedia Displays
Device
PW166B-10T, -10TL*
Application
Up to SXGA in, XGA out, no keystone
Package
PW166B-10TK, Up to SXGA in, XGA out, with -10TKL* keystone PW166B-20T, -20TL* Up to UXGA in, SXGA/UXGA out, no keystone 256 PBGA
PW166B-20TK, Up to UXGA in, SXGA/UXGA -20TKL* out, with keystone PW166B-30T, -30TL* Up to UXGA/HDTV in, SXGA/UXGA out, no keystone
Note: "L" denotes lead-free (Pb) chip.
7700 SW Mohawk Street Telephone: (503) 612-6700 Tualatin, OR 97062 Fax: (503) 612-6713 www.pixelworks.com
P/N 001-0028-01 Rev A Copyright © 2002 by Pixelworks, Inc. All rights reserved.
Revision History
Revision
001-0028-00 Rev A-C 001-0028-00 Rev D 001-0028-00 Rev E 001-0028-00 Rev F 001-0028-00 Rev G 001-0028-00 Rev H 001-0028-00 Rev I 001-0028-00 Rev J 001-0028-00 Rev K 001-0028-01 Rev A 001-0028-01 Rev B
Date
May 2001September 2001
Description
Initial release& update to include PW166B and PLL.
13 November 2001 Updates to Register Maps. 21 November 2001 Updates to Electrical Specifications. 5 December 2001 Updates to Register Maps.
12 December 2001 Updates to Pin Descriptions and Register Maps. January 2002 5 March 2002 12 March 2002 May 2002 June 2002 0ctober 2003 Updates to Functional Description and Register Maps. Updates to Electrical Specifications and Register Maps. Updates to Front Cover and Electrical Specifications. Updates to Electrical Specifications and Register Maps. Create 166B using new template. Extensive updates to Electrical Specifications and Register Maps.
Copyright © 2002 by Pixelworks, Inc. All rights reserved.
Pixelworks owns all right, title and interest in the property and products described herein, unless otherwise indicated. No part of this document may be translated to another language or produced or transmitted in any form or by any information storage and retrieval system without written permission from Pixelworks. Pixelworks reserves the right to change products and specifications without written notice. Customers are advised to obtain the latest versions of any product specifications. PIXELWORKS MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OTHER THAN COMPLIANCE WITH THE APPLICABLE PIXELWORKS SPECIFICATION SHEET FOR THE PRODUCT AT THE TIME OF DELIVERY. IN NO EVENT SHALL PIXELWORKS BE LIABLE FOR ANY INDIRECT, INCIDENTAL OR CONSEQUENTIAL DAMAGES AS A RESULT OF THE PRODUCT'S PERFORMANCE OR FAILURE TO MEET ANY ASPECT OF SUCH SPECIFICATION. PIXELWORKS PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN LIFE SUPPORT APPLIANCES, DEVICES OR SYSTEMS WHERE A MALFUNCTION OF A PIXELWORKS DEVICE COULD RESULT IN A PERSONAL INJURY OR LOSS OF LIFE. CUSTOMERS USING OR SELLING PIXELWORKS DEVICES FOR USE IN SUCH APPLICATIONS TO SO AT THEIR OWN RISK AND AGREE TO FULLY INDEMNIFY PIXELWORKS FOR ANY DAMAGES RESULTING FROM SUCH IMPROPER USE OR SALE. Information contained herein is presented only as a guide for the applications of our products. Pixelworks does not warrant this product to be free of claims of patent infringement by any third party and disclaims any warranty or indemnification against patent infringement. No responsibility is assumed by Pixelworks for any patent infringement resulting from use of its products by themselves or in combination with any other products. No license is hereby granted by implication or otherwise under any patent or patent rights of Pixelworks or others. The products described herein may be protected by US Patent No. 6,339,434 with other foreign and domestic patents pending. Other restrictions of rights may also apply.
Trademarks
Pixelworks and Fail-Safe are trademarks of Pixelworks, Inc. All other brand names, product names, trademarks, and registered trademarks are the property of their respective owners. Visit our web page at www.pixelworks.com For support requests, contact us at [email protected] For documentation suggestions, corrections, or requests, contact [email protected]
P/N 001-0028-01 Rev A
Contents
General ........................................................................................................ 0-1 Applications .................................................................................................. 0-1 Features ....................................................................................................... 0-1 Applications .................................................................................................. 0-1
Chapter 1:
Functional Description
Input Ports.................................................................................................... 1-1 Graphics Input Port .............................................................................. 1-1 Video Input Port ................................................................................... 1-1 Sync Decoder and Timer ............................................................................. 1-1 Block Diagram .............................................................................................. 1-1 Automatic Image Optimization ..................................................................... 1-3 Memory Buffer and Interface........................................................................ 1-3 PLL and Oscillator........................................................................................ 1-3 Image Scalers .............................................................................................. 1-3 Color Matrix .................................................................................................. 1-3 On-Screen Display (OSD) ............................................................................ 1-3 Gain and Offset ............................................................................................ 1-4 Color Lookup Tables .................................................................................... 1-4 Color Space Expander ................................................................................. 1-4 Display Port Mux and Timing Generator ...................................................... 1-4 Microprocessor............................................................................................. 1-4
Chapter 2:
Pinout Information
Pin Diagram ................................................................................................. 2-1 Pin Descriptions ........................................................................................... 2-2 Graphics Port Pins ............................................................................... 2-2 Video Port Pins .................................................................................... 2-4 Display Port Pins.................................................................................. 2-5 Microprocessor Interface Pins ............................................................. 2-6 Peripheral Interface Pins...................................................................... 2-8 Miscellaneous ...................................................................................... 2-9 Microprocessor Debug Port Pins ......................................................... 2-9 Power and Ground Pins..................................................................... 2-10
Chapter 3:
Electrical Specifications
Absolute Maximum Ratings ......................................................................... 3-1 DC Specifications ......................................................................................... 3-1 AC Specifications ......................................................................................... 3-3 Graphics Input Timing.......................................................................... 3-3 Video Input Timing ............................................................................... 3-4
1-1
PW164B Product Specification
Contents Display Port Timing.............................................................................. 3-5 Microprocessor ROM Interface ............................................................ 3-6 Microprocessor RAM Interface ............................................................ 3-7 Miscellaneous External Device Access ............................................... 3-8 Oscillator and PLL................................................................................ 3-9 Power-On and Power-Off States ....................................................... 3-10
Chapter 4:
Theory of Operations
Functional Description.................................................................................. 4-1 Graphics Port ............................................................................................... 4-1 Backward Compatibility Mode.............................................................. 4-2 Data Register and Multiplexer.............................................................. 4-2 Color Space Conversion ...................................................................... 4-3 RGB Compression ............................................................................... 4-4 Memory Interface ................................................................................. 4-4 Clock Generator................................................................................... 4-5 Sync Decoder ..................................................................................... 4-5 Sync Detection ........................................................................... 4-6 Sync Processing......................................................................... 4-6 Interlace Field Detection............................................................. 4-7 Auto Image Optimization ............................................................ 4-8 Phase Lock Loop (PLL) Control........................................................... 4-9 Video Port .................................................................................................. 4-10 Backward Compatibility Mode............................................................ 4-10 Data Register ..................................................................................... 4-11 Color Space Converter ...................................................................... 4-11 RGB Compression ............................................................................. 4-11 Memory Interface ............................................................................... 4-12 Timing and Sync Decoder.................................................................. 4-13 Clock Generator ....................................................................... 4-13 Sync Decode ............................................................................ 4-13 Interlace Field Detection........................................................... 4-15 Auto Image Optimization .......................................................... 4-15 PLL and Oscillator...................................................................................... 4-16 Memory ...................................................................................................... 4-17 Power Saving Modes ................................................................................. 4-18 On-Screen Display (OSD) .......................................................................... 4-20 OSD Processing ................................................................................ 4-20 OSD Palette ....................................................................................... 4-21 OSD Size and Position ...................................................................... 4-21 Picture-in-Picture........................................................................................ 4-23 Image Scalers ............................................................................................ 4-23 Vertical Scaler.................................................................................... 4-23 Horizontal Scaler................................................................................ 4-26 Microprocessor and Peripherals ................................................................ 4-28 Interrupt Controller ............................................................................. 4-28
PW164B Product Specification
1-2
8086 CPU .......................................................................................... 4-29 Clock and Reset................................................................................. 4-30 Timers ................................................................................................ 4-30 External Memory Interface................................................................. 4-30 UART ................................................................................................. 4-34 Infrared Receiver (IR) ........................................................................ 4-34 GPIO .................................................................................................. 4-36 Display Port................................................................................................ 4-37 PW364 Compatibility.......................................................................... 4-37 On-Screen Display............................................................................. 4-37 Color Matrix........................................................................................ 4-37 Gain ................................................................................................... 4-38 Color Lookup Tables.......................................................................... 4-38 Color Space Expander....................................................................... 4-39 Demultiplexer ..................................................................................... 4-40 Display Timing Generator .................................................................. 4-41
Chapter 5:
Register Maps
Register Map Overview ................................................................................ 5-1 Control Register Definitions ......................................................................... 5-2 Register Organization .......................................................................... 5-2 Register Types..................................................................................... 5-2 Register Shadowing............................................................................. 5-2 General Control............................................................................................ 5-3 Graphics Port ............................................................................................. 5-11 Video Port .................................................................................................. 5-18 On-Screen Display (OSD) .......................................................................... 5-24 Vertical Scaler ............................................................................................ 5-30 Horizontal Scaler........................................................................................ 5-34 Extended Graphics Port ............................................................................. 5-37 Extended Display Port................................................................................ 5-39 Display Port................................................................................................ 5-40 Color Lookup Tables .................................................................................. 5-47 Wait State & Decode.................................................................................. 5-48 I/O Ports ..................................................................................................... 5-50 Timers ........................................................................................................ 5-51 Interrupt Controller ..................................................................................... 5-52 Serial Port .................................................................................................. 5-55 IR Decoder ................................................................................................. 5-56
Chapter 6:
Packaging
Package ....................................................................................................... 6-1 Thermal Resistance ..................................................................................... 6-2
1-3
PW164B Product Specification
1
Functional Description
This section provides a summary of the operation of the PW166B ImageProcessor. The illustration on the following page shows the block diagram upon which this discussion is based.
1.1
Input Ports
The PW166B supports simultaneous acquisition on Graphics and Video input ports. Each input port has its own sync decoder and automatic image optimization circuitry.
1.1.1
Graphics Input Port
The Graphics Port (GPort) captures computer graphics inputs with very high input bandwidth through an external Analog-To-Digital converter (ADC) or digital interface receiver. The GPort accepts single-pixel input at a maximum rate of 135 MPixels/second, or two-pixels-per-clock input at a maximum pixel rate of 236 MPixels/second In the single input pixel mode, this port supports YPbPr inputs. The GPort provides PLL support with an on-chip ÷N counter, phase delay circuitry, black sample pulse for DC restore, and PLL coast control. A Color Space Converter with programmable coefficients and programmable tint and gain has been added to the graphics input port for single pixel inputs, with speeds up to 105 MPixels/second.
1.1.2
Video Input Port
The Video Port (VPort) is generally used to support video inputs. This port is designed to work directly with popular digital video decoders and supports YUV and RGB input data. The PW166B supports picture-in-picture by enabling both the VPort and the GPort simultaneously. The VPort supports input data rates up to 75 MPixels/second. It can support standard interlaced video as well as externally de-interlaced video data and low speed RGB data (up to SVGA). The VPort may be run at up to 75MHz with a small external circuit to support XGA or 1080i resolutions.
1.2
Sync Decoder and Timer
The sync processing for the input ports supports all common sync types including separate syncs, digital composite sync, or composite Sync-on-Green (SOG). In addition the PW166B supports interlaced composite sync, serrated sync, and data enable only input modes. The sync timing is measured for use by the Automatic Image Optimization system.
1.3
Block Diagram
Figure 1-1 provides a detailed block diagram of the PW166B ImageProcessor:
1-1
PW166B Product Specification
\
Port B
Port A
IRRCVR(1:0)
JTAG Debugger
D(15:0) A(19:0) CS(1:0)
EXTINT NMI
TxD
RxD
I/O Ports
PWM
IR Decoder
16-Bit Microprocessor
Processor ROM/ RAM Interface
Watchdog and Timers
Interrupt Controller
UART
Microprocessor Bus
Memory In Bus
VYUV (15:0)
YUV to RGB
GRGB (47:0)
YPbPr to RGB
Graphics Port Pixel Processing
SDRAM Frame Buffer
Memory Out Bus
Video Port Pixel Processing
Processor Memory Interface
OnScreen Display
OSD
Image Scalers Memory Controller
Color Matrix
Gain
OSD
Color Lookup Tables
Color Space Expander
RGBE (23:0) RGBO (23:0)
1-2 PW166B Product Specification
VVS, VHS GVS, GHS
Display Timing Generator
MCLK DCLK UCLK
DVS, DHS, DEN, DCLK
Sync Decoder and Timer
Auto Image Optimization Clock Generator
PW166B Internal Block Diagram
GREF GFBK PLL Control
XI
XO
Figure 1-1 PW166B ImageProcessor Block Diagram
Automatic Image Optimization
Functional Description
1.4
Automatic Image Optimization
The PW166B incorporates second-generation Automatic Image Optimization. This means that more measurement data is available with more support for serrated sync inputs plus additional phase detection circuitry. This includes all of the circuitry necessary to perform fully automatic set-up of all image capture parameters. These include sample clock phase and frequency, image position, image size, and image gain (black and white levels). In addition, Automatic Image Optimization can now be performed without blanking the screen, and the time to lock onto an image has been reduced by 50%.
1.5
Memory Buffer and Interface
The internal SDRAM Memory Buffer stores the entire image on-chip. SXGA (1280x1024) resolution and below are captured and stored as 24-bit RGB pixels. Images above SXGA (UXGA at 1600x1200 and 1080p at 1920x1080) can be stored and displayed with full 24-bit color when operating in frame locked mode when input and output refresh rates are the same. For images above SXGA with frame rate conversion, intelligent compression of the image to 16 bits is performed. The on-chip memory buffer is also used to store OSD bitmaps and provide on-chip RAM for the microprocessor. The Memory Buffer supports frame rate conversion with different input and output refresh rates, frame locked modes, and double buffered modes of operation. The Memory Interface arbitrates between the GPort input, VPort input, Image Scaler, OSD controller, and microprocessor to allow these units access to the frame memory simultaneously.
1.6
PLL and Oscillator
The PW166B integrates PLLs to generate the MCLK and DCLK. Only an external crystal or clock oscillator is required. These PLLs can be turned off for backward compatibility to the PW364. On power-up, these PLLs are initialized to provide a 100MHz MCLK and a 65MHz DCLK when a 14.318MHz reference is used. The PLLs can be used to vary the clock rates to minimize power consumption in lower power modes.
1.7
Image Scalers
The Image Scalers provide high quality up and down image scaling. The PW166B incorporates a flexible scaling architecture using the latest Pixelworks processing. The vertical and horizontal scaling factors are independently programmable. Any scaling factor between 1/64x and 32x can be achieved. The scaling factors can automatically be changed on a line by line and pixel by pixel basis by the hardware.This allows high quality non-linear scaling for applications such as aspect ratio conversion. Filters with up to 320 taps using 10-bit coefficients can be implemented. The filter coefficients are fully programmable, which makes it possible to implement many different filter types. PW166B-10TK and PW166B-20TK support enhanced vertical keystone correction. Multi-region nonlinear scaling provides enhanced control for converting between 16:9 and 4:3 (or any other) aspect ratios.
1.8
Color Matrix
A programmable 3x3 color matrix is provided to allow precise control of the output pixel color temperature. This feature is a matrix multiplier with six 6-bit programmable coefficients.
1.9
On-Screen Display (OSD)
The on-screen display (OSD) can be used for startup screens, menus, and scribble functions. Transparent menus and randomly shaped menus are supported. No additional memory is required to implement OSD displays that can cover up to the entire screen. The OSD data is applied to the image after it has been scaled. This mode supports OSD graphics with 16 colors from a palette of 64k colors, and can have a maximum size of 2048 X 2048 pixels. A typical OSD size for 16-color mode is 512x360 pixels configuration independent. PW166B ImageProcessor also has a 2-bit/pixel OSD Mode for large OSD sizes with only four colors.
1-3
PW166B Product Specification
Functional Description
Gain and Offset
1.10
Gain and Offset
The Gain function is implemented by multiplying each red, green, and blue sub-pixel by an 8-bit value and adding an 8-bit signed offset.
1.11
Color Lookup Tables
The color lookup tables have an effective size of 256 x 10-bits. There are three independent tables, one each for red, green, and blue. Using 10-bit precision allows more colors to be rendered while still correcting the gamma response of the display device. These 10-bit values can be dithered down to 8-bits or less in the Color Space Expander (CSE).
1.12
Color Space Expander
The Color Space Expander (CSE) preserves the full captured color depth (up to 16.7M colors) on display devices without full 24-bit pixel support. Using a programmable combination of spatial and temporal dithering, a variety of display technologies are supported. Typical output configurations include: · · · · 24-bit pixels 18-bit pixels (6+6+6) 15-bit pixels (5+5+5) 12-bit pixels (4+4+4)
The CSE can accept 24-, 27-, or 30-bit pixels from the gamma tables. Dithering 30-bit pixels down to 24- or 18-bit pixels allows significant gamma corrections to be made in the gamma tables with minimum color space loss.
1.13
· ·
Display Port Mux and Timing Generator
The DPort is designed to be connected directly to LCDs and other display devices. Supported output formats are: Single-pixel digital RGB (12-bit to 24-bit pixels, 1 pixel per clock) supported up to 100 MPixels/second (50 MHz). Dual-pixel digital RGB (12-bit to 24-bit pixels, 2 pixels per clock) supported up to 133 MPixels/second (62.5 MHz).
The output timing is fully programmable and is independent of the input timing. A constant optimal output refresh rate can be maintained independent of the input refresh rate. For video modes, the system can run frame locked or double buffered to prevent field tearing.
1.14
Microprocessor
An on-chip 80x86 microprocessor with custom features for image processing applications is provided. Built in port interrupts, General Purpose I/O (GPIO), UART, IR Decoders, Timers and PWM Generator provide a full featured hardware base to build on. The system also includes a glueless interface to a wide variety of PROM, ROM, FLASH, and RAM parts. A 4-pin microprocessor debug port can be connected to an external JTAG debugger in order to set hardware breakpoints (up to 4), stop, single-step, read/write memory, and interrogate the state of the internal 80x86 CPU. A 16 deep trace buffer provides the ability to record bus cycles or branch history.
PW166B Product Specification
1-4
2
Pinout Information
2.1 Pin Diagram
The PW166B is packaged in a 256-pin Plastic Ball Grid Array (PBGA) package. The pin locations are shown in when viewed from the top. The remainder of this chapter provides descriptions of these pins.
20
GBE6 GGO2 GGO3 GGO7 GGE2
G GPEN GGE4 GGE6 GRO0 GRO4 GRE0 GRE4 GRE5 GRE7 DRE1 COAST SOG GBLK SPL GHS VDD 2.5 VSS GCLK GGE5 GGE7 GRO3 GRO7 GRE1 GRE6 DRE0 VDD 2.5 VSS VSS
VDD 3.3
DRE7 DGE2 DGE4
19
GBE4 GBE5 GGO1 GGO6 GGE1 VDD 3.3
DRE5 DGE1 DGE3 DBE0 VDD 3.3 DGE5
18
GBE1 GBE3
GBE7 GGO4 GGE0
GREF GGE3
VDD GRO2 GRO5 GRE2 VDD2.5 DRE2 DRE4 DGE0 2.5 GRO1 GRO6 GRE3 VSS DRE3 DRE6 VSS
DGE7 DBE1 VDD 3.3 DBE4
17
GBO5 GBO7 GBE2
VSS
GGO0 GGO5
GFBK
GVS
VSS
16
GBO1 GBO4 GBO6 GBE0 V GBO0 GBO2 GBO3 FIELD VVS MODE 0 VSS VHS VDD 2.5 VPEN VSS CPU TMS VCLK
DGE6 DBE2
DBE6
15
DBE3
DBE5 VDD 2.5 DVS VDD 3.3 VDD 2.5
DBE7
DEN VDD 2.5 DCK EXT
14
VSS
VSS MCK EXT
13
VB7 VDD 2.5 VSS
DHS
12
VB6 VDD 2.5 VDD 2.5 VG6
VSS
DCLK DRO0
11
VB5
VB4
VSS
DRO1 DRO2
10
VB3
VB2
VSS
DRO3 DRO4 DRO5 DRO6 VDD 3.3
9
VB1
VB0
VG5
VSS
DRO7 DGO0
8
VG7
VG4
VG1 VDD 3.3
VG0
DGO3 DGO2 DGO1 DGO4 VDD 2.5P
7
VG3 CPU TCK
VG2
VSS
VSS
DGO6 DGO5 VDD 3.3
6
MODE PORT PORT 2 B5 B2
DBO1 DBO0
VSS
5
PORT PORT PORT PORT B7 B6 B1 A5 PORT PORT PORT B4 B3 A4 PORT PORT B0 A6 VDD 2.5 VSS IR RCVR0 D0 VSS VDD 2.5 D5 D8 D13 VSS VDD 3.3 RAM WE D15 VSS VDD 2.5 ROM WE RAM OE L WR A3 XTAL OUT XTAL IN A1 A11 A16
MODE DBO4 DBO2 DGO7 1 VSS DBO6 VDD 3.3 A15 VSS CPU TDO A19 DBO3
4
3
TXD RESET
D1
D9
D14
RD
A2
A8
A12
A17
DBO5
2
PORT PORT PORT IR EXT A7 A2 A0 RCVR1 INT PORT PORT A3 A1 A B RXD NMI D2
D3
D10
D12
CS0 ROM OE M
BHEN
A5
A7
A10
DBO7
1
D4
D6
D7
D11
CS1
A0
A4
A6
A9
A13
A14
A18
C
D
E
F
G
H
J
K
N
P
R
T
U
V
W
Y
Figure 2-1 Pin Diagram (Top View)
2-1
PW166B Product Specification
Pinout Information
Pin Descriptions
2.2
· · · · · · IU ID O I/O P NC
Pin Descriptions
(input with pull-up) (input with pull-down) (output) (bidirectional with pull-down) (power) (no connect)
Table 2-1 provides detailed pin descriptions. Pin types include the following:
2.2.1
Graphics Port Pins
Table 2-1 describes pins for the Graphics Port.
Table 2-1 Pin Descriptions for the Graphics Port
Name GCLK Pin(s) H19 Type ID Function Graphics port pixel clock input. Typically driven by an external PLL GPort Clock. The GCLK pin can be selected to be the source for the internal GCLK that is used for GPort image capture and for the PLL divider (see GCKPOL & GCKSRC bits). Graphics port pixel enable input. Used for external flow control when EXTFCE=1. When GPENSOG is high, input RGB pixel is valid. Using GPENSOG allows capture of noncontiguous data.When EXTFCE=0, this is the Graphics port Sync-On-Green (SOG) input. Driven by external sync stripper circuit, this pin is monitored (SOGACT status bit) and can supply composite sync information (depending on SOGEN & COMPEN bits). Graphics port vertical sync input. Indicates start of next field or frame of input data. GVS can be either active-high or active-low as determined by VPOL and VSOK. GVS is not used when a composite digital sync source is used (SOGEN=1 or COMPEN=1). Graphics port horizontal sync input. Indicates the start of the next line of input data. This signal is internally polarity corrected and monitored for composite sync content (HSOK, HPOL, & COMP status bits). GHS can supply horizontal sync information or digital composite sync information (depending on COMPEN bit). GHS is also used as the input to the clock phase delay circuit that produces the GREF signal. Graphics port PLL feedback / line advance input. This pin has three different functions depending on the register settings for EXTFBK and EXTFCE: EXTFBK
0
GPENSOG
G20
ID
GVS
J17
ID
GHS
G19
ID
EXTFCE
X
GFBK Function
GFBKOUT: An output from the internal PLL divider. GFBKIN: An input to the feedback pulse from an external PLL divider. In free running capture mode this signal is used to define the horizontal capture region (along with CAPL and CAPW), and advances the GPort capture controller to the next input line. The LAVPOL bit is used to select the polarity of GFBKIN. GLAV: An input to the graphics port line advance. Used in external flow control capture mode. When GLAV transitions (depending on LAVPOL bit), the GPort capture controller advances to the next input line.
GFBK
H17
I/O
1
0
1
1
PW166B Product Specification
2-2
Pin Descriptions Table 2-1 Pin Descriptions for the Graphics Port
Name GRE0 GRE1 GRE2 GRE3 GRE4 GRE5 GRE6 GRE7 GGE0 GGE1 GGE2 GGE3 GGE4 GGE5 GGE6 GGE7 GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 GRO0 GRO1 GRO2 GRO3 GRO4 GRO5 GRO6 GRO7 GGO0 GGO1 GGO2 GGO3 GGO4 GGO5 GGO6 GGO7 Pin(s) M20 N19 N18 N17 N20 P20 P19 R20 F18 E19 E20 J18 H20 J19 J20 K19 D16 A18 C17 B18 A19 B19 A20 D18 K20 L17 L18 L19 L20 M18 M17 M19 E17 C19 B20 C20 E18 F17 D19 D20 Type ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID Function
Pinout Information
Graphics port red even data sub-pixel input. Red channel data for single pixel mode or even red pixel data for dual pixel input mode. Pr channel data for YPbPr inputs.
Graphics port green even data sub-pixel input. Green channel data for single pixel mode or even green pixel data for dual pixel input mode. Y channel data for YPbPr inputs.
Graphics port blue even data sub-pixel input. Blue channel data for single pixel mode or even blue pixel data for dual pixel input mode. Pb channel data for YPbPr inputs.
Graphics port red odd data sub-pixel input. Not used for single pixel mode, odd red pixel data for dual pixel input mode.
Graphics port green odd data sub-pixel input. Not used for single pixel mode, odd green pixel data for dual pixel input mode.
2-3
PW166B Product Specification
Pinout Information Table 2-1 Pin Descriptions for the Graphics Port
Name GBO0 GBO1 GBO2 GBO3 GBO4 GBO5 GBO6 GBO7 GREF Pin(s) B15 A16 C15 D15 B16 A17 C16 B17 H18 Type ID ID ID ID ID ID ID ID O Function
Pin Descriptions
Graphics port blue odd data sub-pixel input. Not used for single pixel mode, odd blue pixel data for dual pixel input mode.
Graphics port PLL reference output. Delayed version of internal sync separated GHS. Typically connected to the REF input of PLL. Changing the PHASE bits changes the amount of delay between GHS and GREF.
Graphics port black sample clamp pulse output. Used as part of an external DC restoration circuit to clamp the black level of the GPort analog RGB data to ground. This pulse occurs after HSync and is programmable (BKSPOL, BKSCEN, BKSBEG, & BKSWID). Graphics port PLL coast control output. Used to enable PLL coasting (ignore GREF and GFBK) during vertical blanking. Used to prevent the PLL from reacting to extra or missing HS pulses during vertical blanking. Coast enable and duration is programmable (PLLCM, PLLCB & PLLCE).
GBLKSPL
F19
O
GCOAST
F20
O
2.2.2
Video Port Pins
Table 2-2 describes pins for the video port.
Table 2-2 Pin Descriptions for the Video Port
Name VCLK VPEN Pin(s) D12 C13 Type ID ID Function Video port pixel clock. Controls video port image capture. Typically driven by external video decoder. Video port pixel enable input. Used for external flow control when EXTFCE=1. When VPEN is high, input pixel data is valid. Using VPEN allows capture of non-contiguous data. Video vertical sync. Indicates start of next field or frame of data from external video decoder. VVS can be either active-high or active-low as determined by VPOL. VVS is not used when a composite digital sync source is used (COMPEN). Video horizontal sync. Indicates start of next line of data input from external video decoder. VHS can be either active-high or active-low as determined by HPOL. Indicates composite sync when COMP = 1. Video odd/even field indicator. Indicates whether odd or even field of interlaced input is being captured as determined by FLDINV and FLDSEL. Field information can also be derived from VVS and VHS, so VFIELD is not needed in some applications.
VVS
A14
ID
VHS
B14
ID
VFIELD VG0 VG1 VG2 VG3 VG4 VG5 VG6 VG7
A15 D8 C8 B7 A7 B8 D9 C9 A8
ID ID ID ID ID ID ID ID ID
Video Port Y Pixel Data. Can operate in three different modes: Y Data in YUV 4:2:2 mode; V Data in YUV 4:4:4 mode; Green Data in 24-bit RGB mode.
PW166B Product Specification
2-4
Pin Descriptions Table 2-2 Pin Descriptions for the Video Port
Name VBV0 VBV1 VBV2 VBV3 VBV4 VBV5 VBV6 VBV7 Pin(s) B9 A9 B10 A10 D11 A11 C12 B13 Type ID ID ID ID ID ID ID ID Video Port UV Pixel Data. Can operate in three different modes: UV Data in YUV 4:2:2 mode; U Data in YUV 4:4:4 mode; Blue Data in 24-bit RGB mode. Function
Pinout Information
2.2.3
Display Port Pins
Table 2-3 describes pins for the display port.
Table 2-3 Pin Descriptions for the Display Port
Name DCKEXT DCLK DVS DHS DEN DRE0 DRE1 DRE2 DRE3 DRE4 DRE5 DRE6 DRE7 DGE0 DGE1 DGE2 DGE3 DGE4 DGE5 DGE6 DGE7 Pin(s) Y13 W12 V13 U13 Y15 R19 T20 R18 R17 T18 U19 T17 V20 U18 V19 W20 W19 Y20 V17 U16 W18 Type ID O O O O O O O O O O O O O O O O O O O O Display green even data sub-pixel out in dual pixel output mode. Display green data sub-pixel out in single pixel output mode. Display red even data sub-pixel out in dual pixel output mode. Display red data sub-pixel out in single pixel output mode. Function This register provides two different functions: · Display clock input when the internal PLL is disabled. · JTAG CPUTDI when the internal PLL is disabled Display pixel clock output. Enabled when DCLKEN=1. Polarity is inverted when DCPOL=1. Runs at ½ pixel rate when DCK2EN=1. Display vertical sync output. Polarity and timing controlled by VSPOL, VPLSE, and VDLY. Display horizontal sync output. Polarity and timing controlled by HSPOL, HPLSE. Display pixel enable.
2-5
PW166B Product Specification
Pinout Information Table 2-3 Pin Descriptions for the Display Port
Name DBE0 DBE1 DBE2 DBE3 DBE4 DBE5 DBE6 DBE7 DRO0 DRO1 DRO2 DRO3 DRO4 DRO5 DRO6 DRO7 DGO0 DGO1 DGO2 DGO3 DGO4 DGO5 DGO6 DGO7 DBO0 DBO1 DBO2 DBO3 DBO4 DBO5 DBO6 DBO7 Pin(s) Y19 Y18 V16 U15 Y16 V15 W16 W15 Y12 W11 Y11 U10 V10 W10 Y10 W9 Y9 W8 V8 U8 Y8 Y7 W7 Y5 V6 U6 W5 Y4 V5 Y3 V4 Y2 Type O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Display blue odd data sub-pixel out in dual pixel output mode. Unused in single pixel output mode. Display green odd data sub-pixel out in dual pixel output mode. Unused in single pixel output mode. Display red odd data sub-pixel out in dual pixel output mode. Unused in single pixel output mode. Display blue even data sub-pixel out in dual pixel output mode. Display blue data sub-pixel out in single pixel output mode. Function
Pin Descriptions
2.2.4
Microprocessor Interface Pins
Table 2-4 describes pins for the microprocessor interface.
Table 2-4 Pin Descriptions for the Microprocessor Interface
Name WR RD ROMOE ROMWE BHEN RAMOE Pin(s) M4 M3 M1 L2 N2 L1 Type O O O O O O Function Write Enable. Low indicates a write to external RAM or other devices. Read Enable. Low indicates a read to external RAM or other devices. ROM Output Enable. Active low output indicates a read from external ROM. ROM Write Enable. Active low indicates a write to external ROM. High-byte enable. Low indicates upper byte of data is valid. RAM output enable. Active low output indicates a read from external RAM.
PW166B Product Specification
2-6
Pin Descriptions Table 2-4 Pin Descriptions for the Microprocessor Interface
Name RAMWE CS0 Pin(s) K2 M2 Type O O Function
Pinout Information
CS1 EXTINT NMI A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
N1 E2 D1 P1 P2 N3 N4 R1 R2 T1 T2 R3 U1 U2 R4 T3 V1 W1 V2 T4 U3 Y1 W2
O ID ID O O O O O O O O O O O O O O O O O O O O
RAM write enable. Active low output indicates a write to external RAM. Miscellaneous Chip Select 0. Active low output selects external devices. Each Chip Select decodes a 256-byte block of CPU address space (location of block is programmable). Miscellaneous Chip Select 1. Active low output selects external devices. Each Chip Select decodes a 256-byte block of CPU address space (location of block is programmable). External interrupt request 0. Can be programmed to be level or edge sensitive. This pin becomes CPUTDI input when the JTAG debugger is enabled. Non-maskable interrupt. A high input triggers a non-maskable interrupt to the on-chip microprocessor.
Microprocessor address bus output bits (19:0).
2-7
PW166B Product Specification
Pinout Information Table 2-4 Pin Descriptions for the Microprocessor Interface
Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Pin(s) F4 F3 E1 F2 F1 G2 G1 H1 H4 H3 H2 J1 J2 J4 J3 K1 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Microprocessor 16-bit bidirectional data bus. Function
Pin Descriptions
2.2.5
Peripheral Interface Pins
Table 2-5 describes pins for the peripheral interface.
Table 2-5 Pin Descriptions for the Peripheral Interface
Name PORTA0 PORTA1 PORTA2 PORTA3 PORTA4 PORTA5 PORTA6 PORTA7 PORTB0 PORTB1 PORTB2 PORTB3 PORTB4 PORTB5 PORTB6 PORTB7 IRRCVR0 IRRCVR1 RXD TXD Pin(s) C2 B1 B2 A1 C4 D5 B3 A2 A3 C5 D6 B4 A4 C6 B5 A5 E4 D2 C1 D3 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IU IU ID O IR receiver input 0. IR receiver input 1. Receive data to the on-chip serial port. Transmit data from the on-chip serial port. General Purpose I/O Port. Can operate in three different modes: 8 bits of GPIO in VPort YUV 4:2:2 mode; Y Video Data in VPort YUV 4:4:4 mode; Red Video Data in VPort 24-bit RGB mode. General purpose IO port. PORTA7 can be selected as the PWM output. Function
PW166B Product Specification
2-8
Pin Descriptions
Pinout Information
2.2.6
Miscellaneous
Table 2-6 provides detailed pin descriptions.
Table 2-6 Miscellaneous Pin Descriptions
Name RESET MCKEXT MODE2 Pin(s) E3 W13 B6 Type IU ID IU
2
0 0
Function Master reset. A high input initializes all internal logic. Memory system clock. Not needed when using on-chip PLL
Mode 1
0 0 1 1
0
0 1 0 1
Mode Description
Reserved Normal with PLL and OSC Normal 24-bit Addressing Mode Pin test mode
JTAG
--Yes Yes Yes
24-Bit
--No No Yes
PLL
--Yes No Yes
OSC
--Yes No Yes
MODE1
U5
ID
0 0
VG(7:0)
0x80 0x82 1 0 0 1 1 0 1 0 1 0x83
Output
Z 0 1 --No No No --No No No --Yes No Yes --Yes No No
MODE0
A13
ID
1 1 1 PLL and OSC PW364 Emulation Mode PLL, OSC, and 24-bit Mode
Note: Mode 101 is normal operating mode for PW166B.
XTALIN XTALOUT
P3 P4
ID O
Crystal input if OSC is enabled or Clock input if OSC is disabled. Crystal output.
2.2.7
Microprocessor Debug Port Pins
Table 2-7 describes pins for the microprocessor debug port.
Table 2-7 Pin Descriptions for the Microprocessor Debug Port
Name CPUTMS CPUTCK CPUTDO Pin(s) D13 A6 W3 Type ID ID O Function JTAG input Test Mode Select. Active high to enable JTAG test port for CPU debugger. JTAG Test Clock for CPU debugger mode. JTAG Test Data Output CPU debugger mode.
2-9
PW166B Product Specification
Pinout Information
Pin Descriptions
2.2.8
Power and Ground Pins
Table 2-8 describes power and ground pins.
Table 2-8 Power and Ground Pin Descriptions
Name Pin(s) B12,C3, C10, C11, C14, G3, G18, K18, L3, P18, V11, V14, Y14 V7 C7, C18, K3, U20, V9,V12, V18, V3, Y6, Y17 A12, B11, D4, D7, D10, D14, D17, G4, G17, K4, K17, L4, P17, T19, U4, U7, U9, U11, U12, U14, U17, W4, W6, W14, W17 Type Function
VDD2.5
P
2.5V digital power.
VDD2.5P
P
2.5 PLL analog power. Connect to 2.5V supply through a 27 ohm resistor.
VDD3.3
P
3.3V digital power.
VSS
P
Ground.
PW166B Product Specification
2-10
3
Electrical Specifications
This chapter describes the electrical specifications for the PW166BImageProcessor.
3.1
Absolute Maximum Ratings
Table 3-1 lists the absolute maximum ratings for the PW166B ImageProcessor.
Table 3-1 Absolute Maximum Ratings
Parameter 2.5V Digital Supply Voltage 3.3V Digital Supply Voltage Voltage on any input Storage Temperature Soldering Temperature (30 sec.) Symbol V25 V33 VI TS TSOL Min -0.3 -0.3 -0.3 -40 Max 3.6 4.5 V33+0.3 125 230 Units V V V °C °C Conditions
3.2
DC Specifications
Table 3-2 lists the absolute DC electrical specifications for the PW166B ImageProcessor.
Table 3-2 Absolute Maximum Ratings
Parameter Symbol VIH VIL IIL1 IIH1 IIL2 IIH2 CIN VOH VOL V33-0.3 0.4 Min 2.0 -0.3 10 -10 -10 10 Typ Max V33+0.3 0.8 400 10 10 400 7.6 Units V V µA µA µA µA pF IOUT = IOH IOUT = IOL VOUT = VOH
*Note 4
Conditions *Note 1 *Note 2 *Note 2 *Note 3 *Note 3
Digital Inputs
Input High Voltage Input Low Voltage Input Low Leakage Current 1 Input High Leakage Current 1 Input Low Leakage Current 2 Input High Leakage Current 2 Input Capacitance
Digital Outputs
Output High Voltage Output Low Voltage
Display Outputs
Output High Current Output Low Current I0H1 I0L1 6 10 8 14
VOUT = VOL
*Note 4
3-1
PW166B Product Specification
Electrical Specifications Table 3-2 Absolute Maximum Ratings (continued)
Parameter Symbol I0H2 I0L2 V33 V25 I33a I25a I33a I25a I33a I25a TA TJ 0 0 Min 3 5 3.135 2.375 20 200 15 150 Typ 4.5 7.5 3.3 2.5 80 420 60 280 3.465 2.625 150 500 80 350 15 50 70 105 V V mA mA mA mA mA mA °C °C Max Units
DC Specifications
Conditions VOUT = VOH VOUT = VOL
All Other Outputs
Output High Current Output Low Current
Power Requirements
3.3V Digital Power Supply 2.5V Digital Power Supply 3.3V Digital Supply Current 1 2.5V Digital Supply Current 1 3.3V Digital Supply Current 2 2.5V Digital Supply Current 2 3.3V Digital Supply Current 3 2.5V Digital Supply Current 3
*Note 5 *Note 5 *Note 6 *Note 6 *Note 7 *Note 7
Operating Temperature
Ambient temperature, still air Junction temperature
Notes:
1. 2. 3. 4. 5. 6. 7. The input pins of the device are not 5V tolerant. For inputs RESET, CPUEN, UCSRC, MODE2, IRRCVR1, and IRRCVR0. For all other inputs. Display Outputs include DCLK, DVS, DHS, DEN, DRE(7:0), DGE(7:0), DBE(7:0), DRO(7:0), DGO(7:0), DBO(7:0 MCLK = 155MHz, DCLK = 133MHZ, GCLK = 67.5MHz, (dual pixel in) VCLK = 75MHz (worst case power). MCLK = 100MHz, DCLK = 65MHZ, GCLK = 67.5MHz (dual pixel in), VCLK = 30MHz (typical power) MCLK = 40MHz, DCLK = 0MHZ, GCLK = 0MHz, VCLK = 0MHz, OWPWR=1, =1, VCLKOFF=1, DCLKOFF=1 (low power).
PW166B Product Specification
3-2
AC Specifications
Electrical Specifications
3.3
AC Specifications
The following sections detail the AC specifications and the timing diagrams for the PW166B. The specifications include: · · · · · · · · Graphics Input Video Input Display Port ROM Interface RAM Interface External Devices Oscillator and PLL Power-on and Power-off States
3.3.1
Graphics Input Timing
Figure 3-1 illustrates the AC timing characteristics for the Graphics Port:
TGCL GCLK (GCKPOL = 1) GCLK (GCKPOL = 0) GRE(7:0), GGE(7:0),GBE(7:0), GRO(7:0), GGO(7:0), GBO(7:0) GVS, GHS, GFBK GPENSOG TSUG TSUGP T HG T HGP T GCH
Figure 3-1 Graphics Port AC Timing Table 3-3 lists the electrical specifications for the Graphics Port.
Table 3-3 Graphics Port Electrical Specifications
Parameter Set-up time to GCLK for inputs GVS, GHS, GFBK, GRE(7:0), GGE(7:0), GBE(7:0), GRO(7:0), GGO(7:0), GBO(7:0) Hold Time from GCLK, inputs GVS, GHS, GFBK, GRE(7:0), GGE(7:0), GBE(7:0), GRO(7:0), GGO(7:0), GBO(7:0) Propagation Delay from GCLK, outputs GFBK, GHSFOUT Frequency, input clock GCLK and PLLCLK in dual pixel input mode Frequency, input clock GCLK and PLLCLK in single pixel input mode High Time, input clock GCLK, PLLCLK Low Time, input clock GCLK, PLLCLK Duty Cycle, output clocks GCLKOUT, GADCCLK Rise Time, output clocks GCLKOUT, GADCCLK Fall Time, output clocks GCLKOUT, GADCCLK Setup time to GCLK for input GPENSOG Hold time from GCLK , input GPENSOG Symbol TSUG THG TPDG FGD FGS TGCH TGCL CGO TRG TFG TSUGP THGP 5.6 0 3.0 3.0 45 55 3 3 Min 2 2 -2 2 80 118 135 Typ Max Units ns ns ns MHz MHz MHz ns ns % ns ns ns ns 20pF Load 20pF Load 20pF Load 20pF Load -10 -20/-30? Conditions
3-3
PW166B Product Specification
Electrical Specifications
Figure 3-2 illustrates the sync AC timing characteristics:
Ts SYNC DATA VALID Tbp Tfp
AC Specifications
Figure 3-2 Sync, Front Porch, Back Porch Width Limits Table 3-4 lists the horizontal and vertical limits:
Table 3-4 Horizontal and Vertical Limits Settings
Parameter Ts Tbp Tfp Description Sync Pulse Width Sync Back Porch Width Sync Front Porch Width Minimum Horizontal Setting 2 pixels 1% of HRES 1% of HRES Minimum Vertical Setting 2 lines 3 lines 3 lines
3.3.2
Video Input Timing
Figure 3-3 illustrates the AC timing characteristics for the Video Port:
VCLK (VCKPOL = 1) VCLK (VCKPOL = 0) VCLKEN, VPEN, VLAV, VVS, VHS, VFIELD, VR(7.0), VG(7:0), VB(7:0) T SUV T HV
Figure 3-3 Video Port AC Timing Table 3-5 lists the electrical specifications for the Video Port:
Table 3-5 Video Port Electrical Specifications
Parameter Setup Time to VCLK, inputs VCLKEN, VPEN, VLAV, VVS, VHS, VFIELD, VR(7:0), VG(7:0), VB(7:0) Hold Time from VCLK, inputs VCLKEN, VPEN, VLAV, VVS, VHS, VFIELD, VR(7:0), VG(7:0), VB(7:0) Frequency, input clock VCLK High Time, input clock VCLK Low Time, input clock VCLK Symbol TSUV THV FV TVCH TVCL 2.0 9.0 Min 2 2 75 TYP Max Units ns ns MHz ns ns Conditions
Refer to Figure 3-2 for the Sync AC timing characteristics, and Table 3-4 for a list of the horizontal and vertical limit settings.
PW166B Product Specification
3-4
AC Specifications
Electrical Specifications
3.3.3
Display Port Timing
TDCYC1 DCLK (DCPOL = 0) DCLK (DCPOL = 1) DVS, DHS, DENR, DENG, DRE(7:0), DGE(7:0), DBE(7:0), PortC(7:0) if 30-bit is enabled TPDD
Figure 3-4 illustrates the AC timing characteristics for the Display Port:
(DPIXEN = 0, DCK2EN = 0)
TDCYC2 DCLK (DCPOL = 0) DCLK (DCPOL = 1) DVS, DHS, DENR, DENG, DENB, DRE(7:0), DGE(7:0), DBE(7:0), DRO(7:0), DGO(7:0), DBO(7:0) TPDD
(DPIXEN = 1, DCK2EN = 1)
TDCYC2 DCLK DVS, DHS, DENR, DENG, DRE(7:0), DGE(7:0), DBE(7:0), PortC(7:0) if 30-bit is enabled
TPDD
(DPIXEN = 0, DCK2EN = 1)
Figure 3-4 Display Port AC Timing Table 3-6 lists the electrical specifications for the Display Port:
Table 3-6 Display Port Electrical Specifications
Parameter Propagation Delay from DCLK, outputs DVS, DHS, DENR, DENG, DENB, DRE(7:0), DGE(7:0), DBE(7:0), DRO(7:0), DGO(7:0), DBO(7:0) Frequency, output clock DCLK in dual pixel output mode Frequency, output clock DCLK in single pixel output mode Duty Cycle, output clock DCLK Rise Time, output clock DCLK Fall Time, output clock DCLK Cycle Time, output clock DCLK Cycle Time, output clock DCLK Symbol TPDD FDD FDS CDO TRD TFD TDCYC1 TDCYC2 1/FD 2/FD 45 Min -2 Max 2 50 66.5 100 108 55 3 3 1/FD 2/FD ns ns Units ns MHz MHz MHz MHz % ns ns Conditions 30pF Load 50pF Load -10 50pF Load -20 50pF Load -10 50pF Load -20 50pF Load 50pF Load 50pF Load 50pF Load 50pF Load
3-5
PW166B Product Specification
Electrical Specifications
AC Specifications
3.3.4
Microprocessor ROM Interface
Figure 3-5 illustrates the timing diagram for the Microprocessor ROM Interface:
Read Cycle TAA A(19:1) TAS ROMOE TRR ROMWE TDSR D(15:0)
From ROM
Write Cycle TAA TAH TAS TDA TAH
TDA
TDHR
TDSW
To ROM
TDHW
Figure 3-5 Microprocessor External ROM Timing Table 3-7 lists the AC electrical specifications for the Microprocessor ROM Interface.
Table 3-7 Microprocessor External ROM Electrical Specifications
Parameter Internal clock period ROM write cycle time 1 ROM read cycle time 1 A(19:1) setup to ROMOE, ROMWE fall A(19:1) hold from ROMOE, ROMWE rise ROMWE pulse width, low 1 ROMOE pulse width, low
1
Symbol TUCLK TAA TAAR TAS TAH TDA TDAR TDSR TDHR TRR TDSW TDHW TASU TAU TPDU FU TGCH TGCL
Min 15 (ROMAA+3)TUCLK (ROMAA+4)TUCLK TUCLK - 5 TUCLK - 5 (ROMAA+1)TUCLK (ROMAA+2)TUCLK 15 0 (ROMRR+1)TUCLK - 5 (ROMAA+1)TUCLK - 5 TUCLK - 5 10 0
Max (ROMAA+3)TUCLK (ROMAA+4)TUCLK
Units ns ns ns ns ns
(ROMAA+1)TUCLK+2 (ROMAA+2)TUCLK+2
ns ns ns ns ns ns ns ns ns
D(15:0) input set up to ROMOE rise D(15:0) input hold from ROMOE rise Read recovery time: ROMOE rise to ROMWE fall 1 D(15:0) output set up to ROMWE rise 1 D(15:0) output hold from ROMWE rise Setup Time to UCLK, inputs A(19:0), D(15:0), RD, WR, BHEN, CS0 Hold Time from UCLK, inputs A(19:0), D(15:0), RD, WR, BHEN, CS0 Propagation Delay from UCLK, outputs A(19:0), D(15:0), RD, WR, BHEN, ROMOE, ROMWE, RAMOE, RAMWE, CS(3:0) Frequency, input clock CLKIN High Time, input clock CLKIN Low Time, input clock CLKIN
15 67 5.0 5.0
ns MHz ns ns
Notes:
1. ROMAA, ROMDA and ROMRR are register values.
PW166B Product Specification
3-6
AC Specifications
Electrical Specifications
3.3.5
Microprocessor RAM Interface
Figure 3-6 illustrates the timing diagram for the Microprocessor RAM Interface:
Read Cycle TAA A(19:1) TAS TDA TAH TAS
Write Cycle TAA
RAMOE ROMOE
TRR ROMWE
TDA
TAH
RAMOE
TDSR D(15:0)
From ROM From RAM
TDHR
TDSW
To ROM To RAM
TDHW
Figure 3-6 Microprocessor External RAM Timing Table 3-8 lists the AC electrical specifications for the Microprocessor RAM Interface:
Table 3-8 Microprocessor External RAM Electrical Specifications
Parameter Internal clock period RAM write cycle time
1
Symbol TUCLK TAA TAAR TAS TAH TDA TDAR TDSR TDHR TRR TDSW TDHW
Min 15 (RAMAA+3)TUCLK (RAMAA+3)TUCLK TUCLK - 5 TUCLK - 5 (RAMAA+1)TUCLK (RAMAA+1)TUCLK 15 0 (RAMRR+2)TUCLK - 5 (RAMAA+1)TUCLK - 5 TUCLK - 5
Max (RAMAA+3)TUCLK (RAMAA+3)TUCLK
Units ns ns ns ns ns
RAM read cycle time 1 A(19:1) setup to RAMOE, RAMWE fall A(19:1) hold from RAMOE, RAMWE rise RAMWE pulse width, low
1
(RAMAA+1)TUCLK + 2 (RAMAA+1)TUCLK + 2
ns ns ns ns ns ns ns
RAMOE pulse width, low 1 D(15:0) input set up to RAMOE rise D(15:0) input hold from RAMOE rise Read recovery time: RAMOE rise to RAMWE fall 1 D(15:0) output set up to RAMWE rise 1 D(15:0) output hold from RAMWE rise
Notes:
1. RAMAA, RAMDA and RAMRR are register values.
3-7
PW166B Product Specification
Electrical Specifications
AC Specifications
3.3.6
Miscellaneous External Device Access
Figure 3-7 illustrates the timing diagram for Miscellaneous External Device Access:
Read Cycle TAA A(19:1) TAS TDA TAH TAS
Write Cycle TAA TDA TAH
CS (3:0) CS(1:0)
RD TRR WR TDSR D(15:0)
From device
TDHR
TDSW
To device
TDHW
Figure 3-7 Miscellaneous Device Access Timing Table 3-9 lists AC electrical specifications for Miscellaneous External Devices:
Table 3-9 Miscellaneous External Device Electrical Specifications
Parameter Internal clock period Miscellaneous write cycle time
1
Symbol TUCLK TAA TAAR TAS TAH TDA TDAR TDSR TDHR
1
Min 15 (MISCAA+4)TUCLK (MISCAA+3)TUCLK TUCLK - 5 TUCLK - 5 (MISCAA+2)TUCLK (MISCAA+1)TUCLK 15 0 (MISCRR+2)TUCLK - 5 (MISCAA+2)TUCLK - 5 TUCLK - 5 0
Max (MISCAA+4)TUCLK (MISCAA+3)TUCLK
Units ns ns ns ns ns
Miscellaneous read cycle time 1 A(19:1) setup to RD, WR, CS(3:0) fall A(19:1) hold from RD, WR, CS(3:0) rise WR(1:0) pulse width, low RD pulse width, low 1 D(15:0) input setup to RD rise D(15:0) input hold from RD rise Read recovery time: RD rise to WR or ROMWE fall D(15:0) output setup to WR rise 1 D(15:0) output hold from WR rise IRRCVRI (0) rise
1
(MISCAA+2)TUCLK + 2 (MISCAA+2)TUCLK + 2
ns ns ns ns ns ns ns
TRR TDSW TDHW TRD
2
µs
Notes:
1. MISCAA, MISCDA, and MISCRR are register values.
PW166B Product Specification
3-8
AC Specifications
Electrical Specifications
3.3.7
Oscillator and PLL
Table 3-10 lists the AC electrical specifications for the Oscillator and PLL.
Table 3-10 Oscillator and PLL Characteristics
Parameter PLL Frequency1 Oscillator Frequency1 Frequency, input clock DCLKEXT High Time, input clock DCLKEXT Low Time, input clock DCLKEXT Frequency, input clock MCLKEXT High Time, input clock MCLKEXT Low Time, input clock MCLKEXT Crystal Series Resistance Crystal Shunt Capacitance Crystal Load Capacitance Crystal Initial Frequency Crystal Frequency Variation with Temperature Symbol FPLL FXTAL FD TDCH TDCL FM TMCH TMCL RXTAL CXS CXL FXDI FXDT -50 -100 2.5 3.0 70 7 12 (typical) +50 +100 3.0 3.0 -10: 133 -20: 133 -30: 155 Min 275 10 Max 550 20 -10: 100 -20: 133 Units MHz MHz MHz MHz ns ns MHz ns ns Ohms pF pF ppm ppm
Notes:
1. ROMAA and ROMRR are register values.
3-9
PW166B Product Specification
Electrical Specifications
AC Specifications
3.3.8
Power-On and Power-Off States
Table 3-9 illustrates the timing diagram for the power-on and power-off states:
TV2R
2.5V
TV2R
TV23D
3.3V
TV32D TV3RD & TRST
TV2LO TV3LO
TV3R
TV3R
RESET
TV3CD TCKRD
MCLK
Figure 3-8 Power-On and Power-Off States Table 3-11 lists the AC electrical specifications for the Power-on and Power-off states.
Table 3-11 Power On and Power Off Timing
Parameter 2.5V Power On to 3.3V Power On Delay 3.3V Power Off to 2.5V Power Off Delay 2.5V Power Low Time 3.3V Power On to Reset Low Delay 3.3V Power Low Time 3.3V Power On to MCLK Active Delay MCLK to Reset Low Delay 2.5V Power On Rise Time 3.3V Power On Rise Time Reset Pulse Width Symbol TV23D TV32D TV2LO TV3RD TV3LO TV3CD TCKRD TV2R TV3R TRST 1.0 Min 0 0 1.0 1.0 1.0 0 100 5 5 Max Units ms ms sec us sec ms MCLK Cycles ms ms us Supply must reach less than 0.010V Supply must reach less than 0.010V Supply must reach less than 0.010V Supply must reach less than 0.010V Conditions
Note:
1. When in Power Off Mode, all supply voltages must be equal to OV. No voltage is allowed on these pins as leakage current is strictly prohibited.
PW166B Product Specification
3-10
4
Theory of Operations
This chapter provides the Theory of Operations for the PW166B ImageProcessor.
4.1
Functional Description
This section provides a discussion of the theory of operation for the PW166B ImageProcessor block diagram shown in Chapter 1 Functional Description.
4.2
Graphics Port
The Graphics Port (GPort) is an input interface for high speed RGB or YPbPr data (up to WUXGA) RGB. The block diagram in Figure 4-1 illustrates the functions performed in the Graphics Port. It accepts incoming data at one or two pixels per clock. The GPort can input data at rates up to 236 MPixels/second. It also has sync separator circuitry, timing signals for PLL control, and clock buffering and conditioning circuitry. The GPort can be disabled by setting bit CAPEN to 0.
GRE(7:0) GGE(7:0) GBE(7:0) GRO(7:0) GGO(7:0) GBO(7:0) Data Register and Multiplexer
YPbPr to RGB
RGB Compress
Memory Interface
GCLK
Clock Generator
GHS GVS GPENSOG VFIELD GREF GFBK GBLKSP GCOAST
Sync Decoder and Auto Image Optimization
PLL Control
Figure 4-1 Graphics Port Block Diagram
4-1
PW166B Product Specification
Theory of Operations
Graphics Port
4.2.1
Backward Compatibility Mode
The GPort operates in PW364 Compatibility Mode when bit GPMODE is 0. In this mode, the PW166B GPort behaves exactly like the PW364 GPort including the operation of the GPort registers. For full PW166B functionality, set GPMODE=1 to enable the new sync processing functions.
4.2.2
Data Register and Multiplexer
The input pixels are first registered when brought onto the chip. Data can be accepted at one or two pixels per clock in the following forms: · · Contiguous or non-contiguous (if external flow control is used) From an interlaced or progressively scanned source
The line and pixel location of each incoming pixel is tracked by an internal line and pixel counter, as shown in Figure 4-2. The line counter is reset at the leading edge of VSYNC, and the pixel counter is reset at the leading edge of HSYNC. Values in the CAPT(11:0), CAPH(11:0), CAPL(11:0), and CAPW(11:0) registers define the active region of the incoming data. Data is ignored for the first (CAPT(11:0)+1) active lines, then (CAPH(11:0) +1) lines are captured. For each line, (CAPL(11:0) + 1) valid pixels are ignored before starting image capture, then (CAPW(11:0) +1) valid pixels are captured. For all modes of image capture, an internal line advance signal, GLAVIN, is used. If LAVSRC[1:0] is 0x2, pin GFBK is used for GLAVIN. If LAVSRC[1:0] is 0x1, pin GHSYNC is used for GLAVIN.
CAPL CAPT CAPW
CAPH Active Screen Area
Total Display Area Including Blanking
Figure 4-2 Capture Window Pixels are qualified by the GPENSOG input if external flow control is enabled. To set this mode, set bit EXTFCE to 1. The polarity of GPENSOG is set by the PENPOL bit; if PENPOL is 1, GPENSOG is active high. When external flow control is enabled, each new line is marked by an edge on the GLAVIN input (pin GFBK). The polarity of GLAVIN is set by the LAVPOL bit; if LAVPOL is 1, rising edges on GLAVIN increments video capture to the next line. Furthermore, when bit LAVMOD is 1, edges on GLAVIN after VSYNC and before the first pulse of GPENSOG are ignored. If EXTFCE is 0, GLAVIN and GPENSOG are ignored. Pixels are expected to be contiguous on each line, and lines are expected to be contiguous. In this mode, if bit FBKSRC is 0, pin GFBK is used as the input HSYNC signal for the pixel counters. If bit FBKSRC is 1, pin GHS is used as the input HSYNC signal for the pixel counters. The polarity of this signal is controlled by bit LAVPOL; if LAVPOL is 1, GFBKIN is active high. The capture region is then completely specified by registers CAPT, CAPH, CAPL, and CAPW.
PW166B Product Specification
4-2
Graphics Port
Theory of Operations
For interlaced sources, the data can be written to the memory in a manner that recombines the fields to form a single non-interlaced frame. This process is described in Memory Interface on page 4-4. In addition, there are two bits that control interlaced image capture: · · If bit FLDFRZ is 1, only one field of an interlaced image is captured, the other is ignored. Bit FLDINV determines which field to capture when FLDFRZ is 1. If FLDINV is 1, the odd field is captured, if FLDINV is 0, the even field is captured.
In addition, the value in register CAPTOFF[1:0] is automatically added to register CAPT during the field specified by bit OFFFLD. If OFFFLD is 0, CAPTOFF is added during the even field. If OFFFLD is 1, CAPTOFF is added during the odd field. Data can be input one or two pixels at a time. For one pixel at a time, set bit DUALIN to 0. Then input pins GRE(7:0), GGE(7:0), and GBE(7:0) are used. For two pixels at a time, set DUALIN to 1. Then input pins GRE(7:0), GGE(7:0), and GBE(7:0) are used for the even incoming pixels, and pins GRO(7:0), GGO(7:0), and GBO(7:0) are used for the odd incoming pixels. In addition, the pixels can be received in Parallel or Alternating Mode. Figure 4-3 illustrates Parallel Mode, in which bit DUALALT is set to 0.
GCLK VGR, VGG, VGB DGR, DGG, DGB
D0 D1
D2 D3
D4 D5
Figure 4-3 Dual Pixel Input Parallel Mode Figure 4-4 illustrates Alternating Mode, in which bit DUALALT is set to 1.
GCLK VGR, VGG, VGB DGR, DGG, DGB D0 D1 D2 D3 D4 D5
Figure 4-4 Dual Pixel Input Alternating Mode The input buses can be reversed such that inputs GRE(7:0), GGE(7:0), and GBE(7:0) are used for the odd incoming pixels, and pins GRO(7:0), GGO(7:0), and GBO(7:0) are used for the even incoming pixels. To reverse these buses, set bit DUALREV to 1. The PW166B also has some status registers used to check the black and white levels of the incoming pixels. These registers are REDMIN(7:0), REDMAX(7:0), GRNMIN(7:0), GRNMAX(7:0), BLUMIN(7:0), and BLUMAX(7:0). They are updated during VSYNC with the minimum and maximum values for each color found during the entire previous field. In addition, bits REDOVR, GRNOVR, and BLUOVR are set to 1 at VSYNC if any pixel during the previous field had a value of 255. Finally, bits REDUND, GRNUND, and BLUUND are set to 1 at VSYNC if any pixel during the previous field had a value of 0.
4.2.3
Color Space Conversion
This block performs color space conversion. If bit CSCEN is 0, this function is disabled, and the input pixels are passed through unchanged. If CSCEN is 1, the data is changed according to the following formulas: Note
Color space conversion can be performed only with single pixel inputs.
4-3
PW166B Product Specification
Theory of Operations
For CHROMAOFF = 0: (4-1) (4-2) (4-3) R = Y + (Pb * COEFB / 128) + (Pr * COEFA / 128) G = Y + (Pb * COEFD / 128) + (Pr * COEFC / 128) B = Y + (Pb * COEFF / 128) + (Pr * COEFE / 128)
Graphics Port
For CHROMAOFF = 1: (4-4) (4-5) (4-6) R = Y + ((Pb-128) * COEFB / 128) + ((Pr-128) * COEFA / 128) G = Y + ((Pb-128) * COEFD / 128) + ((Pr-128) * COEFC / 128) B = Y + ((Pb-128) * COEFF / 128) + ((Pr-128) * COEFE / 128)
Typical values for common standards are shown in Table 4-1:
Table 4-1 Typical CSC Coefficients for Standard Video Modes
Standard SMPTE240 REC709 REC601 Coeff A 202 179 202 Coeff B 0 0 0 Coeff C -61 -91 -60 Coeff D -29 -44 -24 Coeff E 0 0 0 Coeff F 234 227 238
Set CHROMAOFF=1 for unsigned mid-level clamped inputs, where 0x00 represents -128 and 0xff represents +128. For sig