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PW1235
Product Specification
General
The PW1235 Video Signal Processor is a high quality, digital video signal processor that incorporates Pixelworks' patented, state-of-the-art video deinterlacer and scaler. Using sophisticated algorithms, the PW1235 is able to effectively deinterlace video input by creating motion vectors that follow frame-to-frame movement, and provide clear, progressive output in both analog and digital formats. With support for NTSC and PAL video formats, the PW1235 can be designed into any TV, monitor, or projector application. Support for 3:2 and 2:2 film mode detection enables the PW1235 to provide the best quality display for existing film and video standards. The PW1235 can dynamically enter or exit film mode (with flexible programming) to display mixed content with the best possible quality. As a single device, the PW1235 integrates many functions onto one chip. It has embedded a scaler, an advanced deinterlacer, memory controller, color space converter, and Digital-to-Analog Converter (DAC) onto one chip. There are two video input ports--a primary video port and a secondary input port--that are used to accept YUV video in the ITU-R601 and ITU-R656 formats respectively. Video content is analyzed on a single-pixel granularity to detect presence or absence of noise and compute the amount of motion. Motion video is processed using a highly intelligent algorithm that simultaneously eliminates noise and interpolates pixels along any angle to produce a noise-free picture without jagged-edge artifacts. As part of a Pixelworks solution, combining the PW1235 with a Pixelworks ImageProcessor (such as the PW113, PW166 or PW181) offers the world's best combination of deinterlacing and scaling of video or graphics. This combination of high quality deinterlacing and scaling is essential for higher resolution outputs such as XGA, SXGA, and UXGA that need to display NTSC and PAL video.
Crystal
Digital Out Video
Video Decoder
PW1235 Analog Out
PW1235 System Block Diagram
SDRAM
Features
· · · · · · · · · · · · · Motion-Adaptive Deinterlace Processor Intelligent Edge Deinterlacing Film Mode Detection (2:2 and 3:2 Pull-Down) Flexible Picture-in-Picture (PIP) Advanced Video Scaling Techniques Digital Color/Luminance Transient Improvement (DCTI/DLTI) Interlaced Video Input Options, including NTSC and PAL Frame Rate Conversion Color Space Converters Triple 10-Bit Digital-to-Analog Converter (DAC) Copy Protection Built-In Memory Controller Supports HDTV
Applications
· · · · · Flat-Panel (LCD, DLP) TVs LCD Multimedia Monitors Multimedia Projectors Progressive Scan CRT TVs Digital TVs
Device
PW1235 PW1235-L
Application
Up to XGA (720p)
Package
256-pin PQFP
NOTE: "L" denotes lead (Pb) free.
8100 SW Nyberg Road Tualatin, OR 97062 USA Telephone: 503.612.6700 FAX: 503.612.6713 www.pixelworks.com
Copyright © 2003-2005 by Pixelworks, Inc. All rights reserved.
Pixelworks owns all right, title and interest in the property and products described herein, unless otherwise indicated. No part of this document may be translated to another language or produced or transmitted in any form or by any information storage and retrieval system without written permission from Pixelworks. Pixelworks reserves the right to change products and specifications without written notice. Customers are advised to obtain the latest versions of any product specifications. PIXELWORKS MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OTHER THAN COMPLIANCE WITH THE APPLICABLE PIXELWORKS SPECIFICATION SHEET FOR THE PRODUCT AT THE TIME OF DELIVERY. IN NO EVENT SHALL PIXELWORKS BE LIABLE FOR ANY INDIRECT, INCIDENTAL OR CONSEQUENTIAL DAMAGES AS A RESULT OF THE PRODUCT'S PERFORMANCE OR FAILURE TO MEET ANY ASPECT OF SUCH SPECIFICATION. PIXELWORKS PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN LIFE SUPPORT APPLIANCES, DEVICES OR SYSTEMS WHERE A MALFUNCTION OF A PIXELWORKS DEVICE COULD RESULT IN A PERSONAL INJURY OR LOSS OF LIFE. CUSTOMERS USING OR SELLING PIXELWORKS DEVICES FOR USE IN SUCH APPLICATIONS DO SO AT THEIR OWN RISK AND AGREE TO FULLY INDEMNIFY PIXELWORKS FOR ANY DAMAGES RESULTING FROM SUCH IMPROPER USE OR SALE. Information contained herein is presented only as a guide for the applications of our products. Pixelworks does not warrant this product to be free of claims of patent infringement by any third party and disclaims any warranty or indemnification against patent infringement. No responsibility is assumed by Pixelworks for any patent infringement resulting from use of its products by themselves or in combination with any other products.
Trademarks
Pixelworks and Fail-Safe are trademarks of Pixelworks, Inc. All other brand names, product names, trademarks, and registered trademarks are the property of their respective owners.
Visit our web page at www.pixelworks.com For support requests, contact us at [email protected] For documentation suggestions, corrections, or requests, contact [email protected]
Revision History
Revision
P/N 001-0063-00 Rev A P/N 001-0063-00 Rev B P/N 001-0063-00 Rev C P/N 001-0063-00 Rev D P/N 001-0063-00 Rev E P/N 001-0063-00 Rev F
Date
October 2002 December 2002 February 2003 13 August 2003 29 August 2003 4 February 2005 Preliminary release.
Description of Changes
Updated register information and Input Unit figures. Updated to reflect addition of lead free chip. Updated information for memory clock, power-up sequence, and other changes. Added film-mode status registers 0xEE and 0xEF (read-only). Updated device addresses accessed via the 2-wire serial bus.
Contents
General ........................................................................................................................... 0-1 Features .......................................................................................................................... 0-1 Applications..................................................................................................................... 0-1
Chapter 1:
Functional Description
Features .......................................................................................................................... 1-1 Input Ports....................................................................................................................... 1-3 Video Input Ports ................................................................................................... 1-3 Digital/Graphics (DG) Input Port ............................................................................ 1-3 I-Channel, B-Channel and P-Channel............................................................................. 1-3 PLL and Oscillator.................................................................................................. 1-3 Memory Controller.................................................................................................. 1-4 Deinterlace Processor............................................................................................ 1-4 Video Scalers .................................................................................................................. 1-4 Video Enhancer............................................................................................................... 1-4 Digital Display Port.......................................................................................................... 1-4 Analog Display Port ............................................................................................... 1-5 2-Wire Bus Slave Interface .................................................................................... 1-5
Chapter 2:
Pinout Information
Pin Diagram .................................................................................................................... 2-1 Pin Descriptions .............................................................................................................. 2-1 Digital/Graphics (DG) Port Pins ............................................................................. 2-4 System Power Pins ................................................................................................ 2-5 Miscellaneous Pins ................................................................................................ 2-7 Host Interface Pins................................................................................................. 2-7 Memory Pins .......................................................................................................... 2-8 Digital Display Output Port Pins ............................................................................. 2-9 Analog Display Port Pins ..................................................................................... 2-10
Chapter 3:
Electrical Specifications
Absolute Maximum Ratings ............................................................................................ 3-1 DC Specifications............................................................................................................ 3-1 Primary Video (PV) Port AC Timing Characteristics ....................................................... 3-2 Secondary Video (SV) Port AC Timing Characteristics .................................................. 3-3 Digital Graphics (DG) Port Input AC Timing Characteristics........................................... 3-4 Display Port Output AC Timing Characteristics .............................................................. 3-5 Memory Interface Input AC Timing Characteristics......................................................... 3-6 Memory Interface Output AC Timing Characteristics...................................................... 3-7
TOC-1
PW1235 Product Specification
Contents
Chapter 4:
Theory of Operations
PLLs ................................................................................................................................ 4-1 Input Ports....................................................................................................................... 4-1 Sync Decoder ........................................................................................................ 4-2 Secondary Video (SV) Port (ITU-R BT656 Mode 2, Slave Option)........................ 4-3 Memory Controller........................................................................................................... 4-5 Frame Buffer Operations ....................................................................................... 4-5 SDRAM Interface ................................................................................................... 4-6 Memory Refresh .................................................................................................... 4-7 Deinterlace Processor..................................................................................................... 4-7 Film Mode .............................................................................................................. 4-7 Video Scalers .................................................................................................................. 4-8 Vertical Scaler ........................................................................................................ 4-9 Horizontal Scaler.................................................................................................... 4-9 Video Enhancer............................................................................................................... 4-9 Luminance Peaking Filter .................................................................................... 4-10 DLTI & DCTI ........................................................................................................ 4-10 Black Level Expansion ......................................................................................... 4-10 Brightness and Contrast ...................................................................................... 4-11 Hue and Saturation .............................................................................................. 4-11 Color Space Converters....................................................................................... 4-11 Color LUT............................................................................................................. 4-12 Blanking ............................................................................................................... 4-12 Blue Screen ......................................................................................................... 4-12 Display Timing Generator ............................................................................................. 4-12 Analog Display Port....................................................................................................... 4-14 Copy Protection ................................................................................................... 4-14 Sync Signal Insertion ........................................................................................... 4-14 CGMS .................................................................................................................. 4-14 2-Wire Serial Bus Description ....................................................................................... 4-15 2-Wire Serial Bus Protocol ................................................................................... 4-15
Chapter 5:
Register Maps
Register Map Overview................................................................................................... 5-1 Control Register Definitions ............................................................................................ 5-2 Clock Generator and Programming Unit ......................................................................... 5-2 Digital/Graphics (DG) Port Registers .............................................................................. 5-5 Primary Video (PV) Port.................................................................................................. 5-9 Secondary Video (SV) Port Registers........................................................................... 5-15 Input Control and Status Registers ............................................................................... 5-19 Memory Control and Status Registers .......................................................................... 5-21 Display Control and Status Registers ........................................................................... 5-29 Deinterlace Control Configuration Registers................................................................. 5-33 Up-Scaling Configuration Registers .............................................................................. 5-34
PW1235 Product Specification
TOC-2
Contents
Display Timing Configuration Registers ........................................................................ 5-35 Video Overlay Configuration Registers ......................................................................... 5-36 Miscellaneous Registers ............................................................................................... 5-38 2:2 Pull-Down Configuration Registers ................................................................ 5-38
Chapter 6:
Packaging
Package .......................................................................................................................... 6-1 Physical Dimensions ....................................................................................................... 6-2 Thermal Resistance ........................................................................................................ 6-2
TOC-3
PW1235 Product Specification
Contents
PW1235 Product Specification
TOC-4
1
Functional Description
This chapter provides an overview of the PW1235 Video SignalProcessor, and describes the features and modes of operation.
1.1
· · · · ·
Features
Input Unit Programming Unit Memory Unit PLL and Oscillator Display Unit
The PW1235 SignalProcessor offers the following features:
Figure 1-1 provides a detailed functional block diagram of the PW1235 SignalProcessor. The following sections describe the functional areas shown on the block diagram.
Primary Video Port Film-Mode Detection (3:2 & 2:2) Previous Video I-Channel
Input Unit
Display Timing
Memory Unit
Display Unit
ITU-R BT 601
Deinterlacer
P-Channel
Digital Output Timing Up Scaler
Secondary Video Port I-Channel
ITU-R BT 656 P-Channel Down Scaler RGB
Video Input
Motion Detect and Noise Reduction
Primary Picture (I/P)
Digital Graphics Port
24-Bit
Video Enhancements CSC
B-Channel
YUV
CSC
Video Merge (YUV)
CSC
Tw o-Wire Interface Programming Unit
PW1235 Internal Block Diagram
Color LUT
Blue Screen
VSync / HSync Timing
DACs
Analog Output Digital Output Data
Figure 1-1 Internal Block Diagram
Input Ports
Functional Description
1.2
· · · ·
Input Ports
Primary Video (PV) Port, primarily for ITU-R BT601 connections Secondary Video (SV) Port, primarily for ITU-R BT656 connections Digital/Graphics (DG) Port, primarily for connection to a graphics interface Combined PV/SV 4:4:4 YUV 24-bit input port
The PW1235 supports simultaneous acquisition on any two of the three input ports:
Each input port has its own sync decoder and automatic image optimization circuitry.
1.2.1
Video Input Ports
The Primary Video (PV) Port and Secondary Video (SV) Port are generally used to support video inputs. These ports are designed to work directly with popular digital video decoders and MPEG decoders. · · · The Primary Video (PV) Port supports standard interlaced video in the ITU-R BT601 (4:1:1, 4:2:2, and YUV) data format. The Secondary Video (SV) Port supports standard interlaced video in the ITU-R BT656 (4:2:2 YUV) data format. The Combined PV/SV Port supports the 4:4:4 YUV data format.
1.2.2
Digital/Graphics (DG) Input Port
The Digital/Graphics (DG) Port can be configured to capture computer graphics inputs through an external Analogto-Digital Converter (ADC) or digital interface receiver. The Digital/Graphics (DG) Port accepts single-pixel input at a maximum rate of 74 MPixels/second to support XGA resolution.
1.3
· · ·
I-Channel, B-Channel and P-Channel
The I-Channel performs pixel-based motion detection and noise reduction on interlaced video. The P-channel allows down-scaling on progressive (non-interlaced) video. The B-Channel bypasses the memory and internal video processing. 1080i uses the B-Channel.
The PW1235 supports processing on either the I-Channel or the P-Channel, with simultaneous processing on the B-Channel.
1.3.1
PLL and Oscillator
The PW1235 integrates several PLLs to generate the MCLK to the Memory interface and the DCLK to the Digital Display. Only an external crystal or clock oscillator is required to be connected to the XTALI pin. On power-up, these PLLs are initialized to provide an 80 MHz MCLK and a 27MHz DCLK when a 10MHz reference is used. Alternatively, the PLLs can use an external clock as a reference. The equation for the M-PLL output frequency is: Fout = Fin * ( Rm+2 ) / (Odivm * (Nm+2) * 2) The equation for the D-PLL output frequency is: Fout = Fin * ( Rd+2 ) / (Odivd * (Nd+2) * 2) where: Fout is the output frequency Fin is the input frequency
Functional Description
Rm and Rd are 9-bit register variables for the numerator Nm and Nd are a 5-bit register variables for the denominator
Video Scalers
Odivm and Odivd are output dividers derived from a 2-bit register variable MPLL_OD or DPLL_OD respectively. See Chapter 5.3 for details. Additional technical information about PLL programming is available from Pixelworks. See Application Note #87, PW12xx PLL Programming and PW12xx Technical Note #1008 Framelocking and Display Timing.
1.3.2
Memory Controller
The internal Memory Controller supports addressing and control of the external SDRAM. The external SDRAM memory buffer is used to store video fields and motion data. Generally, 2MB of storage is required for NTSC input and 8MB of storage is required for PAL inputs. The Memory Controller also supports frame rate up-conversion with different input and output refresh rates.
1.3.3
Deinterlace Processor
The Deinterlace Processor automatically determines the type of incoming video content film, static interlaced video and moving interlaced video. Different algorithms are applied for each of the content types. The PW1235 incorporates a per-pixel, motion-compensated architecture to produce artifact-free progressive scan video signals. Video content is analyzed on a single pixel granularity to detect presence or absence of noise and compute the amount of motion. Motion video is processed using a highly intelligent algorithm that simultaneously eliminates noise and interpolates pixels along any angle to produce a noise-free picture without jagged-edge artifacts. The Deinterlace Processor detects film-originated content by analyzing consecutive images and detecting a 3:2 or 2:2 pull-down pattern. Film-originated content is deinterlaced by merging the two fields from the original frame.
1.4
Video Scalers
The Video Scalers provide high quality video up scaling or down scaling. The PW1235 incorporates a flexible video scaling architecture using the latest Pixelworks processing. The vertical and horizontal scaling factors are independently programmable.
1.5
· · ·
Video Enhancer
First, by increasing the slope of large luminance transients of vertical features (DLTI) and enhancing transient details in natural scenes (luminance peaking). Second, our digital color transient improvement (DCTI) logic improves the color transitions of vertical objects and reduces color smearing introduced by the video decoder. Finally, our black level expansion logic offers the capability of giving a programmably larger weight to the black parts of the video signals.
The Video Enhancer is a high quality programmable processor that brings out details and color in the video. The PW1235 improves sharpness in three ways:
Brightness, contrast, hue, and saturation controls are also built into the video enhancer.
1.6
·
Digital Display Port
Single-pixel digital RGB or YUV (16-bit to 24-bit pixels, 1 pixel per clock) supported up to 74 MPixels/second.
The digital display port (DPort) is designed to be connected to Pixelworks ImageProcessors (such as the PW113, PW166B, or PW181) or directly to LCD panels and other display devices. The supported output format is:
PW1235 Product Specification
1-4
Digital Display Port
Functional Description
The output timing is fully programmable and is independent of the input timing. A constant optimal output refresh rate can be maintained independent of the input refresh rate.
1.6.1
Analog Display Port
The Analog Display Port generates analog RGB, or YUV, or YPbPr with triple 10-bit Digital-to-Analog Converters (DACs). The analog RGB or YUV output is generated in synchronization with timing signals.
1.6.2
2-Wire Bus Slave Interface
Access to the PW1235 registers is provided by a 2-wire serial bus interface. Only slave mode is supported in the PW1235 SignalProcessor.
Functional Description
Digital Display Port
PW1235 Product Specification
1-6
2
Pinout Information
2.1 Pin Diagram
The PW1235Video SignalProcessor is manufactured in a 256-pin PQFP package. The pin locations are shown in Figure 2-1. The remainder of this chapter provides descriptions for these pins.
2.2
· · · · · · · IU ID O I/O P NC
Pin Descriptions
input with pull-up input with pull-down output bidirectional with pull-down power no connect
Pin types include the following:
GND ground
2-1
W1235 Product Specification
Pinout Information
Pin Descriptions
PW1235 Product Specification
VB0 VB1 VB2 VB3 VDD VB4 VB5 VB6 VB7 PVSS SVHS SVVS SVCLK PVDD VG0 VG1 VG2 VG3 VSS VG4 VG5 VG6 VG7 PVSS PVCLK CREF PVVS PVHS PVDD VR0 VR1 VR2 VR3 VDD VR4 VR5 VR6 VR7 PVSS XTALI XTALO PVDD 2WA1 2WA2 2WCLK PVSS 2WDAT TDO VSS TCK TDI TMS TRSTN PVDD RESETn TEST PVSS MPDVDD MPDVSS MPAVDD MPAVSS NC NC PVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
PVSS NC NC DPAVSS DPAVDD DPDVSS DPDVDD PVDD NC PVSS MA4 MA3 VDD MA5 MA2 PVDD MA6 MA1 MA7 PVSS MA0 MA8 MA10 PVDD MA9 MA13 VSS MA11 MA12 PVSS MCLKFB PVDD MRAS MCAS MWE PVSS MCLK PVDD MD8 MD7 PVSS MD9 VDD MD6 PVDD MD10 MD5 PVSS MD11 MD4 PVDD MD12 MD3 PVSS MD13 MD2 PVDD MD14 VSS MD1 PVSS MD15 MD0 PVDD
193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256
192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
MCUCMD MCUWR MCUCS PVSS MCURDY VSS MCUD7 MCUD6 MCUD5 MCUD4 MCUD3 MCUD2 PVDD MCUD1 MCUD0 MCUA7 MCUA6 VDD MCUA5 MCUA4 MCUA3 PVSS MCUA2 MCUA1 MCUA0 ADGVSS ADGVDD PVDD ADAVSS ADAVDD VREFOUT VREFIN COMP RSET AVS33R AVD33R ADR AVS33G AVD33G ADG AVS33B AVD33B ADB ADDVDD ADDVSS PVSS CGMS DEN TESTCLK PVDD DR7 DR6 VDD DR5 DR4 PVSS DR3 DR2 VSS DR1 DR0 PVDD DG7 DG6
PW1235
DG5 DG4 PVSS DG3 DG2 VDD DG1 DG0 PVDD DB7 DB6 DB5 DB4 PVSS DB3 DB2 VSS DB1 DB0 PVDD DENR DENB DENG PVSS DHS DVS DCLK PVDD DGR7 DGR6 DGR5 DGR4 PVSS DGR3 DGR2 VDD DGR1 DGR0 PVDD DGG7 DGG6 DGG5 DGG4 PVSS DGG3 DGG2 DGG1 DGG0 PVDD DGB7 DGB6 VSS DGB5 DGB4 PVSS DGB3 DGB2 DGB1 DGB0 PVDD DGCLK DGVS DGHS PVSS
Figure 2-1 Pin Layout
2-2
Pin Descriptions
Pinout Information
2.2.1
Video Port Pins
Table 2-1 provides detailed pin descriptions for the Video Port.
Table 2-1 Video Port Pin Descriptions
Name PVHS Pin(s) 28 Type I Function Primary Video (PV) Port horizontal sync input. Indicates start of next line of input data. This signal is internally polarity corrected (PVHS_POL) so PVHS can be either activehigh or active-low. [Input, pull-down, 5V-tolerant] Primary Video (PV) Port vertical sync input. Indicates start of next field or frame of input data. This signal is internally polarity corrected (PVVS_POL) so PVVS can be either active-high or active-low. [Input, pull-down, 5V-tolerant] Video input clock reference. [Input, pull-down, 5V-tolerant] · cref_mode = 1
PVVS
27
I
P VCLK CREF
VR, VG, VB
0
1
N-1
N
sampling points
CREF
26
I
· cref_mode = 0
PVCLK CRE F
VR, VG, VB
0
1
N-1
N
sampling points
PVCLK SVVS
25 12
I I
SVHS SVCLK
11 13
I I
Primary Video (PV) Port pixel clock input. [Input, pull-down, 5V-tolerant] Secondary Video (SV) Port (ITU-R BT656 format) vertical sync input. Indicates start of next field or frame of input data. This signal is internally polarity corrected (svvs_pol) so SVVS can be either active-high or active-low. [Input, pull-down, 5V-tolerant] Secondary Video (SV) Port (ITU-R BT656 format) horizontal sync input. This signal is internally polarity corrected (svhs_pol) so SVHS can be either active-high or activelow. [Input, pull-down, 5V-tolerant] Secondary Video (SV) Port (ITU-R BT656 format) pixel clock input. [Input, pull-down, 5V-tolerant]
2-3
PW1235 Product Specification
Pinout Information Table 2-1 Video Port Pin Descriptions (continued)
Name VR0 VR1 VR2 VR3 VR4 VR5 VR6 VR7 VG0 VG1 VG2 VG3 VG4 VG5 VG6 Pin(s) 30 31 32 33 35 36 37 38 15 16 17 18 20 21 22 Type I I I I I I I I I I I I I I I
10 10
Pin Descriptions
Function Video port red data input. These pins have different functions depending on the settings of the PVmode register. [Input, pull-down, 5V-tolerant]
PV_mode 00 01 Reserved. Primary Video (PV) Port. UV[7:4]: ITU-R BT601 YUV 4:1:1 UV pixel data. Primary Video (PV) Port UV[7:0]: ITU-R BT601 YUV 4:2:2 UV pixel data. Primary Video (PV) Port. R[7:0]: red pixel data or V[7:0]: ITU-R BT601 YUV 4:4:4 pixel data. VR[7:0] Pin Function
11
Video port green data input. These pins have different functions depending on the settings of the Primary Video (PV) Port mode registers. [Input, pull-down, 5V-tolerant]
PV_mode 00 01 Reserved. Primary Video (PV) Port. Y[7:0]: ITU-R BT601 YUV 4:1:1 UV pixel data. Primary Video (PV) Port. Y[7:0]: ITU-R BT601 YUV 4:2:2 UV pixel data. Primary Video (PV) Port. G[7:0]: green pixel data or Y[7:0]: ITU-R BT601 YUV 4:4:4 pixel data. VG[7:0] Pin Function
VG7
23
I
11
VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7
1 2 3 4 6 7 8 9
I I I I I I I I
Video port blue data input. These pins have different functions depending on the settings for the Primary Video (PV) Port mode registers. [Input, pull-down, 5V-tolerant]
PV_mode 00 01 10 11 Reserved. Secondary Video (SV) Port YUV[7:0]: ITU-R BT656 format pixel data. Primary Video (PV) Port. B[7:0]: blue pixel data or U[7:0]: ITU-R BT601 YUV 4:4:4 pixel data. VB[7:0] Pin Function
2.2.2
Digital/Graphics (DG) Port Pins
Table 2-2 provides detailed pin descriptions for the Digital/Graphics (DG) Port.
Table 2-2 Digital/Graphics (DG) Port Pin Descriptions
Name DGVS DGHS DGCLK Pin(s) 67 66 68 Type I I I Function Digital/Graphics (DG) port vertical sync. [Tri-state output, 4mA drive, 5V-tolerant] Digital/Graphics (DG) port horizontal sync. [Tri-state output, 4mA drive, 5V-tolerant] Digital/Graphics (DG) port pixel clock. [Tri-state output, 8mA drive, 5V-tolerant]
PW1235 Product Specification
2-4
Pin Descriptions Table 2-2 Digital/Graphics (DG) Port Pin Descriptions (continued)
Name DGR0 DGR1 DGR2 DGR3 DGR4 DGR5 DGR6 DGR7 DGG0 DGG1 DGG2 DGG3 DGG4 DGG5 DGG6 DGG7 DGB0 DGB1 DGB2 DGB3 DGB4 DGB5 DGB6 DGB7 Pin(s) 91 92 94 95 97 98 99 100 81 82 83 84 86 87 88 89 70 71 72 73 75 76 78 79 Type I I I I I I I I I I I I I I I I I I I I I I I I Function
Pinout Information
Digital/Graphics (DG) port red data. [Bi-directional, input with pull-down, tri-state 4mA drive output, 5V-tolerant]
DGR[7:0] Pin Function Digital/Graphics (DG) Port input (single pixel mode). R[7:0]: red pixel data or V[7:0]: YUV 4:4:4 pixel data.
Digital/Graphics (DG) port green data. [Bi-directional, input with pull-down, tri-state 4mA drive output, 5V-tolerant]
DGG[7:0] Pin Function Digital/Graphics (DG) Port input (single pixel mode). G[7:0]: green pixel data or Y[7:0]: YUV 4:4:4 pixel data.
Digital/Graphics (DG) port blue data. [Bi-directional, input with pull-down, tri-state 4mA drive output, 5V-tolerant]
DGB[7:0] Pin Function Digital/Graphics (DG) Port input (single pixel mode). B[7:0]: blue pixel data or U[7:0]: YUV 4:4:4 pixel data.
2.2.3
System Power Pins
Table 2-3 provides detailed pin descriptions for System Power.
Table 2-3 System Power Pin Descriptions
Name VDD Pin(s) 5, 34, 93, 123, 140, 175, 205, 235 19, 49, 77, 112, 134, 187, 219, 251 Type P Digital core power (2.5V). Function
VSS
G
Digital core ground.
2-5
PW1235 Product Specification
Pinout Information Table 2-3 System Power Pin Descriptions (continued)
Name Pin(s) 14, 29, 42, 54, 64, 69, 80, 90, 101, 109, 120, 131, 143, 165, 180, 200, 208, 216, 224, 230, 237, 243, 249, 256 10, 24, 39, 46, 57, 65, 74, 85, 96, 105, 115, 126, 137, 147, 171, 189, 193, 202, 212, 222, 228, 233, 240, 246, 253 60 61 58 59 197 196 199 198 157 154 151 158 155 152 163 164 149 148 166 167 Type Function
Pin Descriptions
PVDD
P
Digital I/O power (3.3V).
PVSS
G
Ground.
MPAVDD MPAVSS MPDVDD MPDVSS DPAVDD DPAVSS DPDVDD DPDVSS AVD33R AVD33G AVD33B AVS33R AVS33G AVS33B ADAVDD ADAVSS ADDVDD ADDVSS ADGVDD ADGVSS
P G P G P G P G P P P G G G P G P G P G
Memory PLL analog power 1.8V. Memory PLL analog ground. Memory PLL guard ring / digital power 1.8V. Memory PLL guard ring / digital ground. Display PLL analog power 1.8V. Display PLL analog ground. Display PLL digital power 1.8V. Display PLL digital ground. Analog power (+3.3V) for R (V/Pr) channel. Analog power (+3.3V) for G (Y/Y) channel. Analog power (+3.3V) for B (U/Pb) channel. Analog ground for R (V/Pr) channel. Analog ground for G (Y/Y) channel. Analog ground for B (U/Pb) channel. Analog power supply (+1.8V) for the analog display port. Analog ground for the analog display port. Digital power supply (+1.8V) for the analog display port. Digital ground for the analog display port. Guard ring power for the analog display port. Guard ring ground for the analog display port.
PW1235 Product Specification
2-6
Pin Descriptions
Pinout Information
2.2.4
Miscellaneous Pins
Table 2-4 provides detailed descriptions for Miscellaneous Pins.
Table 2-4 Miscellaneous Pin Descriptions
Name XTALI XTALO Pin(s) 40 41 Type I O Function Crystal oscillator input. Connect to an external 10MHz crystal. Crystal oscillator output. Connect to an external 10MHz crystal. Hardware asynchronous reset. The signal is active low. Must be continuously asserted for a minimum of 100 µs after power-up to satisfy the SDRAM power-up requirement. [Input, Schmitt trigger, pull-up, 5V-tolerant] Note: The PW12xx Board Design Guide (018-0003-00 RevA) contains more information about system initialization. CGMS Enable Debug port test data clock. TCK provides the clock input for the Test Bus (also known as the Test Access Port). Debug port test data in. TDI transfers serial test data into VISTA. TDI provides the serial input necessary for JTAG specification support. Debug port test data out. TDO transfers serial test data out of VISTA. TDO provides the serial input necessary for JTAG specification support. Debug port test mode select. TMS is a JTAG specification support signal used by debug tools. Debug port test reset. TRSTn resets the Test Access Port (TAP) logic. TRSTn must be driven low during power on RESETn. Test mode. Active high. Must be low during normal operation. [Input, pull-down, 5Vtolerant] Used for testing, can be used to supply display clock. [Input, pull-down, 5V-tolerant] No connect. No connect.
RESETn
55
I
CGMS TCK TDI TDO TMS TRSTn TEST TESTCLK NC NC
146 50 51 48 52 53 56 144 201 62, 63, 194,195
I I I O I I I I -
2.2.5
Host Interface Pins
Table 2-5 provides detailed pin descriptions for the Host Interface.
Table 2-5 Host Interface Pin Descriptions
Name 2WCLK 2WDAT 2WA1 2WA2 Pin(s) 45 47 43 44 Type I I/O I I Function Clock signal of two-wire serial bus. [Input, pull-up, 5V-tolerant] Data signal of two-wire serial bus. [Bi-directional, tri-state 4mA drive output, 5Vtolerant] Programmable two-wire serial bus address bit 1. [Input, pull-down, 5V-tolerant] Programmable two-wire serial bus address bit 2. [Input, pull-down, 5V-tolerant]
2-7
PW1235 Product Specification
Pinout Information
Pin Descriptions
2.2.6
Memory Pins
Table 2-6 provides detailed pin descriptions for Memory.
Table 2-6 Memory Pin Descriptions
Name MCLK MCLKFB MRAS MCAS MWE MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 Pin(s) 229 223 225 226 227 213 210 207 204 203 206 209 211 214 217 215 220 221 218 255 252 248 245 242 239 236 232 231 234 238 241 244 247 250 254 Type O I O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SDRAM data bus. [Bi-directional, tri-state 8mA drive output, pull-up, 5V-tolerant] SDRAM address bus. Multiplexed row and column address and bank select. · Row addresses use MA[11:0] for 8MB SDRAM and MA[10:0] for 2MB SDRAM. · Column addresses use MA[7:0]. [Tri-state output, 8mA drive, 5V-tolerant] Note: MA10 is a control signal during column address charging and pre-charging. For 8MB SDRAM, the bank select pins ba0 and ba1 should be connected to MA12 and MA13, respectively. For 2MB SDRAM, connect ba0 to MA12. Function SDRAM clock. This signal is rising edge active. [Tri-state output, 8mA drive, 5V-tolerant] SDRAM clock feedback. For latching in read data. [Input, 5V-tolerant] SDRAM row address strobe. This signal is active low. [Tri-state output, 8mA drive, 5V-tolerant] SDRAM column address strobe. This signal is active low. [Tri-state output, 8mA drive, 5V-tolerant] SDRAM write enable. This signal is active low. [Tri-state output, 8mA drive, 5V-tolerant]
PW1235 Product Specification
2-8
Pin Descriptions
Pinout Information
2.2.7
Digital Display Output Port Pins
Table 2-7 provides detailed pin descriptions for the Digital Display Output Port.
Table 2-7 Digital Display Output Port Pin Descriptions
Name DVS DHS DCLK DENR DENG Pin(s) 103 104 102 108 106 Type O O O O O Function Digital display output port vertical sync. [Tri-state output, 4mA drive, 5V-tolerant] Digital display output port horizontal sync. [Tri-state output, 4mA drive, 5V-tolerant] Digital display output port pixel clock. [Tri-state output, 8mA drive, 5V-tolerant] Display pixel enable red/Vertical blanking period (VBLANK). DENR polarity is controlled by DENR_POL [reg 0x61bit 3]. Vertical blanking output select is controlled by DENR_SEL [reg 0xEB, bit 0x07]. [Tri-state output, 4mA drive, 5V-tolerant] Display pixel enable green. DENG polarity is controlled by DENG_POL [reg 0x61bit 4]. [Tri-state output, 4mA drive, 5V-tolerant] Display pixel enable blue/Horizontal blanking period (HBLANK). DENR polarity is controlled by DENB_POL [reg 0x61bit 5]. Horizontal blanking output select is controlled by DENB_SEL [reg 0xEB, bit 0x06]. [Tri-state output, 4mA drive, 5V-tolerant] Digital display output port output enable. [Input, pull-up, 5V-tolerant] Active level controlled by DEN_POL [reg 0x61 bit 2]. Note: DEN only controls the data bus [DR(7:0), DG(7:0), DB(7:0)] and not the control signals [DVS, DHS, DCLK, DENR, DENG, DENB]. Digital display output port red data. [Tri-state output, 4mA drive, 5V-tolerant]
uv_mode DR[7:0] Pin Function DPort single pixel output. R[7:0]: red pixel data or V[7:0]: YUV 4:4:4 pixel data. Note: Dport color space is selected using register 0x78 bits 2:0. 011 UV[7:0]: ITU-R BT601 YUV 4:2:2 pixel data
DENB
107
O
DEN DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DG0 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
145 132 133 135 136 138 139 141 142 121 122 124 125 127 128 129 130 110 111 113 114 116 117 118 119
I O O O O O O O O O O O O O O O O O O O O O O O O
000
Digital display output port green data. [Tri-state output, 4mA drive, 5V-tolerant]
uv_mode DG[7:0] Pin Function DPort single pixel output. G[7:0]: green pixel data or Y[7:0]: YUV 4:4:4 pixel data Note: Dport color space is selected using register 0x78 bits 2:0. 011 Y[7:0]: ITU-R BT601 YUV 4:2:2 pixel data
000
Digital display output port blue data. [Tri-state output, 4mA drive, 5V-tolerant]
uv_mode DB[7:0] Pin Function DPort single pixel output. B[7:0]: blue pixel data or U[7:0]: YUV 4:4:4 pixel data. Note: Dport color space is selected using register 0x78 bits 2:0.
000
2-9
PW1235 Product Specification
Pinout Information
Pin Descriptions
2.2.8
Analog Display Port Pins
Table 2-8 provides detailed pin descriptions for the Analog Display Port.
Table 2-8 Analog Display Port Pin Descriptions
Name ADR ADG ADB VREFIN VREFOUT Pin(s) 156 153 150 161 162 Type O O O I O Analog display port red (V/Pr) data. Analog display port green (Y/Y) data. Analog display port blue (U/Pb) data. Reference voltage input. Voltage reference output. This output nominally delivers 1.23v reference voltage from bandgap reference block. It is normally connected to VREFIN pin. Full-Scale adjust resistor. A resistor should be connected between this pin and AVS33 to control the magnitude of the full-scale video signal. RSET(ohm)=VREFIN(V)*10.66/IOFS(A), where IOFS is full-scale output current. Compensation pin. This pin should be connected through 0.1uF ceramic capacitor to AVD33 (+3.3v) externally. Function
RSET
159
I/O
COMP
160
i/O
PW1235 Product Specification
2-10
3
Electrical Specifications
This chapter describes the electrical specifications for the PW1235 Video SignalProcessor.
3.1
Absolute Maximum Ratings
Table 3-1 lists the absolute maximum ratings for the SignalProcessor.
Table 3-1 Absolute Maximum Ratings
Parameter 3.3V Digital Supply Voltage 2.5V Digital Supply Voltage Voltage on any input Storage Temperature Soldering Temperature (30 seconds) Symbol V33 V25 VI TS TSOL Min -0.3 -0.3 -0.3 -40 C Max 4.5 3.6 V33+0.3 125 C 230 Units V V V C C Conditions
3.2
DC Specifications
Table 3-2 lists the DC electrical specifications for the SignalProcessor.
Table 3-2 DC Specifications
Parameter Symbol Min 2.0 -0.3 +0.01 Typical Max V33+0.3 0.8 +1 8 2.4 0.4 3.135 2.375 3.3 2.5 0.2 0.4 3.465 2.625 0.2 0.8 A A
Typical numbers are with no scaling turned on.
Units V V
Conditions
Digital Inputs Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance Digital Outputs
Output High Voltage Output Low Voltage
VIH VIL IIL CIN VOH VOL
V33 V25 I33a I25a TA TJ
µA
PF
V V
Source current =4mA Source current =4mA
Power Requirements
3.3V Digital Power Supply 2.5V Digital Power Supply 3.3V Digital Supply Current 2.5V Digital Supply Current
Operating Temperature
Ambient Temperature Junction Temperature 0 0 70 105 C C
3-1
PW1235 Product Specification
Electrical Specifications
Primary Video (PV) Port AC Timing Characteristics
3.3
Primary Video (PV) Port AC Timing Characteristics
TPVC PVCLK (PVCLK_POL = 1)
Figure 3-1 illustrates the AC timing characteristics for the Primary Video (PV) Port on the SignalProcessor:
PVCLK (PVCLK_POL = 0)
TSUPVD VR[7:0], VG[7:0], VB[7:0]
THPVD
TSUPVC PVHS, PVVS, CREF
THPVC
Figure 3-1 Primary Video (PV) Port Timing Table 3-3 lists the electrical specifications for the Primary Video (PV) Port:
Table 3-3 Primary Video (PV) Port Electrical Specifications
Parameter PVHS, PVVS, CREF Set-up Time to PVCLK VR[7:0], VG[7:0], VB[7:0] Set-up Time to PVCLK PVHS, PVVS, CREF Hold Time to PVCLK VR[7:0], VG[7:0], VB[7:0] Hold Time to PVCLK PVCLK Frequency PVCLK Duty Cycle Symbol TSUPVC TSUPVD THPVC THPVD 1/TPVC CPVO Min 2 8 0 0 10 45 80 55 Typical Max Units ns ns ns ns MHz % Conditions
PW1235 Product Specification
3-2
Secondary Video (SV) Port AC Timing Characteristics
Electrical Specifications
3.4
Secondary Video (SV) Port AC Timing Characteristics
TSVC SVCLK (SVCLK_EDGE = 1)
Figure 3-2 illustrates the AC timing characteristics for the Secondary Video (SV) Port on the SignalProcessor:
SVCLK (SVCLK_EDGE = 0)
TSUSVD VB[7:0]
THSVD
TSUSVC SVHS, SVVS
THSVC
Figure 3-2 Secondary Video (SV) Port Timing Table 3-4 lists the electrical specifications for the Secondary Video (SV) Port:
Table 3-4 Secondary Video (SV) Port Electrical Specifications
Parameter SVHS, SVVS Set-up Time to SVCLK VB[7:0] Setup Time to SVCLK SVHS, SVVS Hold Time to SVCLK VB[7:0] Hold Time to SVCLK SVCLK Frequency SVCLK Duty Cycle Symbol TSUSVC TSUSVD THSVC THSVD 1/TSVC CSVO Min 2 7 0 0 10 45 27 80 55 Typical Max Units ns ns ns ns MHz % Conditions
3-3
PW1235 Product Specification
Electrical Specifications
Digital Graphics (DG) Port Input AC Timing
3.5
Digital Graphics (DG) Port Input AC Timing Characteristics
TDGC DGCLK (DGCLK_EDGE = 1)
Figure 3-3 illustrates the AC timing characteristics for the Digital Graphics (DG) Input Port on the SignalProcessor:
DGCLK (DGCLK_EDGE = 0)
TSUDGD DGR[7:0], DGG[7:0], DGB[7:0]
THDGD
TSUDGC DGHS, DGVS
THDGC
Figure 3-3 Digital Graphics (DG) Port Input AC Timing Table 3-5 lists the electrical specifications for the Digital Graphics (DG) Input Port:
Table 3-5 Digital Graphics (DG) Port Input Electrical Specifications
Parameter DGHS, DGVS Set- up Time to DGCLK DGR[7:0], DGG[7:0], DGB[7:0] Set-up Time to DGCLK DGHS, DGVS Hold Time to DGCLK DGR[7:0], DGG[7:0], DGB[7:0] Hold Time to DGCLK DGCLK Frequency DGCLK Duty Cycle Symbol TSUDGC TSUDGD THDGC THDGD 1/TDGC CDGO Min 2 7 0 0 10 45 80 55 Typical Max Units ns ns ns ns MHz % Conditions
PW1235 Product Specification
3-4
Display Port Output AC Timing Characteristics
Electrical Specifications
3.6
Display Port Output AC Timing Characteristics
TCYC
Figure 3-4 illustrates the AC timing characteristics for the Display Port Output on the SignalProcessor:
DCLK (DCLK_OUT_CTRL = 000) DCLK (DCLK_OUT_CTRL = 001) T DD DR[7:0], DG[7:0], DB[7:0]
Figure 3-4 Display Port Output Timing Table 3-6 lists the electrical specifications for the Display Port Output Port:
Table 3-6 Display Port Output Electrical Specifications
Parameter DR[7:0], DG[7:0], DB[7:0] Delay Time from DCLK DCLK Frequency Symbol TDD 1/TCYC Min 0 Typical Max 5 80 Units ns MHz Conditions 20PF Load 20PF Load
3-5
PW1235 Product Specification
Electrical Specifications
Memory Interface Input AC Timing Characteristics
3.7
Memory Interface Input AC Timing Characteristics
TFBC MCLKFB
Figure 3-5 illustrates the AC timing characteristics for the Memory Interface Input on the SignalProcessor:
TSUR MD[13:0]
TH R
Figure 3-5 Memory Interface Input Timing Table 3-7 lists the electrical specifications for the Memory Interface Input Port:
Table 3-7 Memory Interface Input Electrical Specifications
Parameter MD[13:0] Set-up Time to MCLKFB MD[13:0] Hold Time to MCLKFB MCLKFB Frequency Symbol TSUR THR 1/TFBC Min 2 0.5 10 80 100 Typical Max Units ns ns MHz Conditions
PW1235 Product Specification
3-6
Memory Interface Output AC Timing Characteristics
Electrical Specifications
3.8
Memory Interface Output AC Timing Characteristics
TMC MCLK (MCLK_WR_POL) = 1)
Figure 3-6 illustrates the AC timing characteristics for the Memory Interface Output on the SignalProcessor:
MCLK (MCLK_WR_POL) = 0)
TDMD MD[15:0]
TDMC MRAS, MCAS, MWE
Figure 3-6 Memory Interface Output Timing Table 3-8 lists the electrical specifications for the Memory Interface Output Port:
Table 3-8 Memory Interface Output Electrical Specifications
Parameter MRAS, MCAS, MWE Delay Time from MCLK MD[15:0] Delay Time from MCLK MCLK Frequency MA[13:0] Delay Time from MCLK Symbol TDMC TDMD 1/TMC Min 2 2 10 N/A 80 Typical Max 7.5 7.5 100 N/A Units ns ns MHz ns Conditions 20PF Load 20PF Load 20PF Load
Address asserted and held one clock before/after RAS/CAS/ WE assertion.
3-7
PW1235 Product Specification
Electrical Specifications
Memory Interface Output AC Timing Characteristics
PW1235 Product Specification
3-8
4
Theory of Operations
This chapter provides the Theory of Operations for the PW1235 Video SignalProcessor.
4.1
PLLs
Two PLLs are inside the PW1235 deinterlacer: one for the memory clock, and one for the display clock. The MPLL (memory clock PLL) is used to drive the primary picture (frame buffer) memory interface. It should be configured to 80MHz-100MHz and not adjusted again. This PLL can be driven from one of four sources: external crystal, PV port, SV port, and DG port. The DPLL (display clock PLL) can be driven by four different sources: external crystal, PV port, SV port, and DG port. Under normal conditions, the DPLL should be configured to use the source clock to drive the DPLL. For example, if the PV port is the input video source, then the DPLL should be configured to use this source to drive the DPLL. Note that the DPLL must always have a valid source. If the DPLL is configured to use an input port clock as a source and the input port clock is disabled, then the DPLL must be reconfigured to use the crystal as the clock source. Please see Application Note #87: PW12xx PLL Programming and TechNote #1008 Framelocking and Display Timing for details on PLL programming.
4.2
Input Ports
Figure 4-1 shows the input ports for the PW1235 SignalProcessor.
4-1
PW1235 Product Specification
Theory of Operations
Input Ports
Input Unit
PV Port 16-bit 4:2:2 ITU-R BT601
Primary Video Port
i-channel
Motion Detection and Noise Reduction
Prev ious Video Current Motion Current Video YUV 4:2:2 Memory Unit
PV/SV Port 24-bit 4:4:4 ITU-R BT601 Secondary Video Port
SV Port ITU -R BT656
p-channel
Dow n Scaler
Current Video YUV 4:2:2
DG Port 24-Bits
Digital Graphics Port
b-channel
Display Unit
Figure 4-1 Input Ports Both the Primary Video (PV) Port and Secondary Video (SV) Port are input interfaces for video data. The Primary Video (PV) Port accepts incoming data in the ITU-R BT601 (4:1:1 and 4:2:2 YUV) formats. The Secondary Video (SV) Port accepts incoming data in the ITU-R BT656 (4:2:2 YUV) format. The combined PV/SV input port accepts incoming data in the ITU-R BT.601 4:4:4 YUV format. The two video ports share a 24-bit video data bus and can be used to capture video inputs simultaneously. When both video ports are used, however, the Primary Video (PV) Port can accept incoming data only in the 4:1:1 or 4:2:2 YUV format. The Digital/Graphics (DG) Port is an input interface for high speed YUV or RGB data. It accepts incoming data at one pixel per clock. The Digital/Graphics (DG) Port can input data at rates up to 74Mpixels/sec. In both graphics and video mode, DGCLK is the input pixel clock. DGVS is the input vertical sync and DGHS is the input horizontal sync.
4.2.1
Sync Decoder
The Sync Decoder determines whether the input format is programmed by an external CPU or automatically detected by the PW1235 SignalProcessor. When DETECT = 1 (PV_DETECT, SV_DETECT or DG_DETECT), the Sync Decoder is able to automatically detect the input format according to the total number of lines sampled between vertical syncs. The total includes both blanking and active lines. The Sync Decoder reports the detected input format in the INPUT_FORMAT field. The PW1235 accepts NTSC, and PAL video signals as well computer graphics inputs in various resolutions (VGA, SVGA and XGA). Once the format is known, the framing of the input signal may begin. The framing parameters consist of width, height, vertical offset and horizontal offset. The vertical and horizontal offset refer to the vertical and horizontal blanking intervals and is specific to each input format. The resolution refers to the active region dimensions of the input video signal.
PW1235 Product Specification
4-2
Input Ports
Theory of Operations
Table 4-1 shows the various default resolutions and offsets for NTSC and PAL. The height of the even field is given in the case of interlaced modes; the height of the odd field is always assumed to be one line larger. The default vertical offset is identical for both the odd and even fields.
Table 4-1 Default Resolutions and Offsets of the Active Screen Area
Video Format NTSC PAL VGA SVGA XGA CAPW 720 720 640 800 1024 CAPH 240 288 480 600 768 ODD_CAPT 16 22 EVEN_CAPT 16 22 35 27 35 CAPL 122 132 144 216 296
When DETECT = 0, the Sync Decoder is programmed with a specific resolution to capture video or graphics data, as shown in Figure 4-2. CAPL(8:0), CAPT(6:0), CAPW(7:0) and CAPH(7:0) registers define the active region of the incoming data. Data is ignored for the first CAPT(8:0) active lines, then ((CAPH(7:0)+1) x 2) lines are captured for the interlaced video input and ((CAPH(7:0)+1) x 4) lines are captured for the graphics input. For each line, CAPL(8:0) valid pixels are ignored before starting image capture, then ((CAPW(7:0) + 1) x 8) valid pixels are captured.
Figure 4-2 Capture Window
4.2.2
Secondary Video (SV) Port (ITU-R BT656 Mode 2, Slave Option)
The PW1235 accepts horizontal and vertical sync signals. A coincident leading edge transition (within 30 clocks) of both SVHS and SVVS inputs indicates the start of an odd field. A SVVS leading edge transition when SVHS is deasserted indicates the start of an even field.
4-3
PW1235 Product Specification
Theory of Operations
Input Ports
Figure 4-3 shows Timing Mode 2 for NTSC formats. VSync and HSync are shown as low-true signals in this example.
Display Display Vertical Blank
522 SVHS
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
SVVS Display
Even field
Odd field Display Vertical Blank
260 SVHS
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
SVVS
Odd field
Even field
Figure 4-3 Timing Mode 2 (NTSC) Figure 4-4 shows Timing Mode 2 for PAL formats. VSync and HSync are also shown as low-true signals in this example.
Display Vertical Blank Display
622 SVHS
623
624
625
1
2
3
4
5
6
7
21
22
23
SVVS Display
Even field
Odd field Display Vertical Blank
309 SVHS
310
311
312
313
314
315
316
317
318
319
320
334
335
336
SVVS
Odd field
Even field
Figure 4-4 Timing Mode 2 (PAL)
PW1235 Product Specification
4-4
Memory Controller
Theory of Operations
4.3
Memory Controller
The integrated memory controller takes care of addressing and control of the external SDRAM. The SDRAM should have LVTTL-compatible inputs and outputs. The SDRAM types used with the PW1235 should be organized as 1Mx16, each bank having 4096 pages of 256 words of 16 bits. A typical configuration uses one 16Mb (1Mx16) or 64Mb (4Mx16) SDRAM with a 16-bit data bus, allowing for 2MB or 8MB of storage. Examples of SDRAMs that are supported include the Hyundai HY57V161610D (2MB), the Micron MT48LC4m16A2 or Hyundai HY57V641620HGT (8MB), or other compatible devices.
4.3.1
Frame Buffer Operations
The memory controller controls the flow of data between the PW1235 and either 2 or 8 MB of external 16-bit SDRAM. The essential function is to operate the SDRAM as a frame buffer between the input and display units. Figure 4-5 shows the flow of the frame buffering operations.
Input Unit Sync Decoder Regs CAP* Regs i2m_* Regs m2d_* or p2m_*
Upscaler Regs us_*
Display Unit
Memory
Figure 4-5 Frame Buffering Data arrives at the frame buffer either in video or motion formats from the input unit or in raw form from the host interface via the two-wire bus. Interlaced data arrives as separate 16-bit 4:2:2 video and 4-bit motion components stored in different regions of the SDRAM. Similarly, data exits the memory unit either in video or motion formats to the display unit or in raw form to the host interface. The video data is also fed back to the input unit. On the input side, the most recent four fields two odd and two even are stored in the frame buffer. Freeze and step functions may be employed for the rejection of all or a fixed ratio of incoming fields. When in freeze mode, the entire frame buffer or a portion thereof may be painted a solid background color or, for diagnostics, a two-dimensional color bar pattern. The active input region stored in the frame buffer is defined by the coordinates of its width i2m_hlen 0x40[6:0] and height i2m_vlen 0x41[7:0] and its top left corner i2m_left 0x44[6:0] and i2m_top 0x45[7:0]. When i2m_siz 0x40[7] = 0 and i2m_offset 0x44[7] = 0, there is no offset from the upper left origin and the size of the active input region follows Table 4-1. On the output side, a set of line buffers is presented to the display unit from the merging of the most recently stored odd and even fields. In this operation, 5 line buffers of 16-bit 4:2:2 video plus 4-bit motion are used. The merging of the odd and even fields can be either straight deinterlaced or inverse 3:2 or inverse 2:2 pulldown, depending on whether film mode has been detected. The active display region is defined by the coordinates of its width m2d_hlen 0x5C[6:0] and height m2d_vlen 0x5D[7:0] and its top left corner m2d_left 0x58[6:0] and m2d_top 0x59[7:0]. When m2d_siz 0x5C[7] = 0 and m2d_offset 0x58[7] = 0, there is no offset from the upper left origin and the size of the active display region follows Table 4-1.
4-5
PW1235 Product Specification
Theory of Operations
Memory Controller
4.3.2
SDRAM Interface
The data output from the SDRAM may be clocked into the PW1235 either using the internally generated MCLKRD or the external MCLKFB. Both MCLKRD and MCLKWR may be inverted relative to the main internal MCLK. The following SDRAM interface initialization sequence is recommended: 1. 2. 3. 4. 5. Configure the MPLL clock speed (0x11 and 0x12 registers) Configure MCLKRD and MCLKWR polarity 0x13 = 03 Configure MDFB_SEL and latency 0x57 = 34 Set SDRAM_INIT 0xF0 = 80 Clear SDRAM_INIT 0xF0 = 00
Figure 4-6 shows a block diagram of the SDRAM interface.
we# mweN mcasN mrasN
12
2MB or 8MB SDRAM
cas# ras# a[11:0]
SDRAM Interface
ma[11:0] ma[12]
all outputs registered on the positive edge of mclk
a[10:0] and ba only in the case of 2 MB SDRAM
ba0 ba1 cke cs# dqml, dqmh gnd dq[15:0]
16
vdd
ma[13]
md_oeN
md_out[15:0]
md[15:0]
D Q
mclkfb
clock path should be daisy-chained mclk -> clk -> mclkfb , so that the two segments are approximately the same length and overlap minimally
DFF
CK D
md_reg[15:0]
Q
DFF
clk
D
Q
CK
mclkrd mclkwr
DFF
CK
mclk
Figure 4-6 SDRAM Interface Block Diagram All outputs from the SDRAM interface are registered on the positive edge of MCLK. The clock path should be connected in this order: mclk-> clk -> mclkfb This ensures that the two segments are approximately the same length and overlap minimally. In the case of 2MB SDRAM, only memory address bus ma[10:0] and ma[12] bits are used to interface with the SDRAM address inputs a[10:0] and bank address input ba. For the 8MB SDRAM usage, ma[11:0] should be connected to a[11:0]; ma[12] and ma[13] should be tied to ba0 and ba1, respectively.
PW1235 Product Specification
4-6
Deinterlace Processor
Theory of Operations
4.3.3
Memory Refresh
Typically an SDRAM part requires refreshing at an average interval of every 15.625 µs. In general, it is good to set the refresh interval ref_len 0x57[1:0] to as large a number as possible to optimize bandwidth. However, a certain maximum setting is required depending on the speed of the memory clock MCLK. Table 4-2 lists the optimal (maximum) setting. The minimum MCLK frequency supported is 10 MHz. Table 4-2 Maximum Refresh Interval Settings Frequency Range mclk 10 50 MHz 51 80 MHz 81 110 MHz > 110 MHz Maximum Refresh Interval ref_len 0 1 2 3
4.4
Deinterlace Processor
The Deinterlace Processor automatically determines the type of incoming video content film, static interlaced video and moving interlaced video. Different algorithms are applied for each of the content types. The PW1235 incorporates a per-pixel, motion compensated architecture to produce artifact-free progressive scan video signals. Video content is analyzed on a single pixel granularity to detect presence or absence of noise and compute the amount of motion. When dint_sel = 0, the motion video is processed using a highly intelligent algorithm that simultaneously eliminates noise and interpolates pixels along any angle to produce a noise-free picture without jagged-edge artifacts.
4.4.1
Film Mode
The Deinterlace Processor detects film-originated content by analyzing consecutive images and detecting a 3:2 or 2:2 pull down pattern. Film-originated content is deinterlaced by merging the two fields from the original frame. Either 32pd_film_mode or 22pd_film_mode bit is normally set to 1 to enable automatic film mode detection. · · In the NTSC mode, the PW1235 detects 3:2 pull-down sequences and merges the fields into 60Hz progressive frames. In the PAL mode, the Deinterlace Processor detects 2:2 pull-down sequences and rearranges the fields into 50Hz progressive frames.
A block diagram of Film Mode is shown in Figure 4-7.
Interlaced Video Noise Reduction Filter Progressiv e Video
Memory
Deinterlacer
Film Mode Detect
Memory Controller
Figure 4-7 Film Mode Block Diagram The Film Mode Detect module detects film originated content sequences by examining the interlaced video inputs. The Memory Controller receives appropriate command to map the fields to support 60Hz progressive video in Memory, prior to deinterlacing. If no film-originated content is detected, the video stream is stored in Memory without further processing. 32pd_film_sens(1:0) and 22pd_film_sens(1:0) registers define the number of fields the PW1235 requires to detect film-originated content and enter film mode.
4-7
PW1235 Product Specification
Theory of Operations
Video Scalers
The sequence is continuously monitored and any break in the sequence caused by "bad cuts" is quickly spotted and compensated for if bad cut processing is enabled (register 0x33). Bad Cut can occur in three scenarios: · · · TV commercials sandwiched between film materials In this case, the source materials jump in and out of the film mode very abruptly. Movie preview in a DVD title. In this case, the movie preview usually consists of many improperly formatted 3:2 film materials. Shot on film, transferred to video, and edited on video.
For general information about film-mode processing, see the Pixelworks Application Note #80 PW1230-PW1235 Internal Film Mode.
4.5
Video Scalers
Figure 4-9 shows the Video Up Scaler. The upscaler remaps an incoming m-column by n-row frame into an outgoing p by q frame.
p m
n
q
Figure 4-8 nm Frame to pq Frame The incoming horizontal length m is determined according to m2d_siz 0x5C[7] and m2d_hlen 0x5C[6:0] fields. Similarly, the upscaler determines the incoming vertical length n is by examining the m2d_siz and m2d_vlen 0x5D[7:0] fields.
Up Scaler
Line n-1 4:4:4 data
24
Line n 4:4:4 data
24
Line n+1 4:4:4 data
24
Vertical Up Scaler
Line 4:4:4 data
30
Horizontal Up Scaler
30
Line 4:4:4 data
Line N+2 4:4:4 data
24
Figure 4-9 Video Up Scaler
PW1235 Product Specification
4-8
Video Enhancer
Theory of Operations
The outgoing horizontal and vertical lengths, p and q, are also programmable. Table 4-3 shows the default output resolutions based on the detected input format. Alternatively, the upscaler can resize the picture to an arbitrary size (adr_hlen by adr_vlen) when adr_us is set to 1. The upscaler can be turned off by setting adr_us to 0.
Table 4-3 Default Output Resolutions
Format NTSC/480i/480p PAL Width (hlen) 720 720 Height (vlen) 480 576
4.5.1
Vertical Scaler
The vertical scaler takes 4 lines of data provided by the deinterlacer, and outputs 1 line. Vertical scaling allows a downscale ratio of up to 2 to 1. The upscale ratio is limited by the resolution of the control registers.
4.5.2
Horizontal Scaler
The horizontal scaler takes 1 line of data provided by the vertical scaler and outputs 1 line. The horizontal scaler only supports upscaling. The upscale ration is limited by the resolution of the control registers.
4.6
Video Enhancer
The Video Enhancer block contains these key functions: Luminance Peaking, DLTI, DCTI, Brightness and Contrast, Hue and Saturation, and Black Level Expansion. Figure 4-10 illustrates the Video Enhancer.
YUV 4:4:4 Progressive Data YUV 4:4:4 Progressive Data
Luminance Peaking
DLTI
DCTI
Black Level Expansion
Brightness & Contrast
Hue & Saturation
Figure 4-10 Video Enhancer Coring is a noise reduction technique used in may areas of the PW1235. If a signal is less than a certain threshold value, it is assumed to be noise and is set to zero. Figure 4-11 shows an example of output with and without coring.
Without Coring With Coring
Output
Time
Figure 4-11 Coring Example
4-9
PW1235 Product Specification
Theory of Operations
Video Enhancer
4.6.1
Luminance Peaking Filter
The Luminance Peaking Filter improves the overall frequency response of the luminance by increasing the peakto-peak signal thus creating blacker blacks and whiter whites. There are two filters applied to the luminance: · · High-pass filter Band-pass filter
The outputs of these filters are weighted by gain factors and summed together. The gain factors are programmable through registers khpw 0xD0[4:0], kbpw 0xD1[4:0] and klp 0xD2[2:0]. Coring is used to remove low amplitudes in the (high-pass + band-pass) signal, which are considered to be noise. Coring levels can be programmed via the peak_coring 0xD3 register.
4.6.2
DLTI & DCTI
The Digital Luminance Transient Improvement (DLTI) and Digital Color Transient Improvement (DCTI) are intended to enhance video by replacing the edges of the video with edges that have steeper rise and fall times. DLTI and DCTI are different from peaking in that they do not increase the peak-to-peak video at its output; rather it turns sloped or sinusoidal waveforms into rectangular or square waveforms with the same duty cycles and peak-topeak amplitude. DCTI is especially useful for 4:1:1 video sources. The PW1235 Video SignalProcessor can perform coring in conjunction with DCTI and DLTI, in which it forces all values below a programmed threshold level to be 0. This is useful to enhance immunity against noise. Via the configuration registers (0xD4 and 0xD5) it is possible to control: DLTI gain width, DLTI coring threshold, DCTI gain width, DCTI coring threshold, and selection of simple, or improved first differentiating DCTI filter.
4.6.3
Black Level Expansion
Black level expansion (BLE) enhances the contrast of the picture. The dark regions of the picture are made darker, while bright areas remain unchanged. The advantage of this black-level expansion is that the black expansion is performed only if it will be noticeable to the viewer. Figure 4-12 shows an example of the BLE transfer function.
KEY:
BLE Transfer Function
BLE_THR
No BLE With BLE
Output Luma
Slope controlled by BLE_GAIN
Input Luma
Figure 4-12 BLE Transfer Function Example
PW1235 Product Specification
4-10
Video Enhancer
Theory of Operations
4.6.4
Brightness and Contrast
Programmable brightness and contras