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RX-A3010/RX-V3071
A B
C D
DIGITAL1 1/9
A B C D E F G
SCHEMATIC DIAGRAMS
DIGITAL1 1/9
1 HDMI
AV 7 AV 6 AV 5 AV 4
CB7 CB5 CB4
CB6
2
3
4
HDMI SWITCHER
IC2
5
RX-A3010/RX-V3071
A B
C D
DIGITAL1 1/9
G H I J K L M N
RX-A3010/RX-V3071
Page 128 J7
AV 3 AV 2 AV 1
(1 BD/DVD) to DIGITAL1 (2)_CB32
CB3 CB2 CB1
CB10
HDMI SWITCHER
IC1
6
IC4
to DIGITAL1 3/9
IC4
to DIGITAL1 4/9
HDMI RECEIVER
7
DIGITAL1 (1)
IC3
8 No replacement part av
IC3: SiI9233ACTU
HDMI receiver
CEC_A CEC CEC_D
DSDA0
DSDA1
Serial HDPC
DSDA2 HDCP Embedded
Host Engine
DSDA3 Registers HDCP Keys
Interface
9 DSCL0
DSCL1
DSCL2
(DDC)
EDID HPD0
DSCL3 SRAM Hot Plug HPD1
NVRAM HPD2
Controller
Serial HPD3
CSDA
Host
CSCL
Interface RPI
CI2CA Configuration
(Local) Registers and Status
and State INT
Machine
Registers
IC1, 2: SiI9185ACTU
Port0_DDC
Port1_DDC
Port2_DDC
R0XC+
R0XC- HDMI switcher
EPSEL1/
EPSEL0/
TX_DDC
R0X0+
R0X0- Video Processing IC4: TC7SH125FU IC5: RP130Q121D-TR-F
LSDA
LSCL
R0X1+
R0X1-
R0X2+ Video
Color
Bus buffer Voltage regulator
R0X2- HDCP Deep ODCK
Space
Unmask Color Video Q[35:0]
R0XC+ Converter
Output DE
EDID Block
R0XC-
HSYNC
G 1
Termination/
R0X0+ Format R0X0+/- Config. EDID 5 VCC
I2C Switch
VDD
Equalizer
R0X0- Up/Down VSYNC
R0X1+
R0X1- Sampling EVNODD R0X1+/- Logic RAM 4
R0X2+ R0X2+/-
R0X2-
HDMI Auto Video Configuration R0XC+/- Configuration Block
IN A 2
Receiver A/V Split HDMI Transmitter
R0XC+ Mux Decode Block
R0XC- Audio Processing GND 3 4 OUT Y
Termination/
R0X0+
Oversample
R1X0+/-
Equalizer
R0X0- Audio Output
R0X1+ Audio Clock SPDIF
R1X1+/- TX0+/-
DPLL
R0X1- S/PDIF
Regeneration TX1+/-
R0X2+ Output R1X2+/-
10 R0X2-
R0XC+
Audio
HDCP
APLL
I2S/
SCK/DCLK
WS
SD[3:0]
R1XC+/- Transmit
Drivers
TX2+/- Vref
R0XC- SCDT DSD Current Limit
R0X0+ Logic Unmask DR[3:0]
Output
CE 1
Termination/
R0X0- DR[3:0] R2X0+/-
R0X1+ Auto PLL
Equalizer
R0X1- R2X1+/- TXC+/-
Audio/ MUTEOUT
R0X2+ XTALIN
R0X2- Exception R2X2+/-
XTALOUT
MCLK R2XC+/- 5V Switch HPD
Switch CEC I/F
CEC
R0PWR5V SCDT Pin No. Symbol Description
R1PWR5V Receiver Block CE Chip Enable ("H" Active)
R2PWR5V 1
R3PWR5V
2 GND Ground Pin
RPWR0
RPWR1
RPWR2
I2CADDR/
TPWR
HPD0
HPD1
HPD2
HPDIN
CEC_A
CEC_D
Reset 3 VOUT Output Pin
RESET# Logic
4 VDD Input Pin
RX-A3010/RX-V3071
A B
C D
DIGITAL1 1/9
to DIGITAL1 5/9
RECEIVER
to DIGITAL1 6/9
IC3
ent part available.
IC6
IC5
IC7
to DIGITAL1 2/9, 3/9, 4/9
D-TR-F IC6: RP130Q501D-TR-F IC7: R1172H121D-T1-F
Voltage regulator CMOS-based positive-voltage regulator IC
3 VOUT VDD 4 3 VOUT VDD 4 5 VOUT
Vref
Components having special characteristics are marked and must be replaced
Current Limit
Vref
CE 1 2 GND with parts having specifications equal to those originally installed.
ent Limit Current Limit Schematic diagram is subject to change without notice.
2 GND CE 1 2 GND
Pin No. Symbol Description
1 CE Chip Enable Pin
Description Pin No. Symbol Description 2 GND Ground Pin
Chip Enable ("H" Active) 1 CE Chip Enable ("H" Active) NC No Connection
3
Ground Pin 2 GND Ground Pin
4 VDD Input Pin
Output Pin 3 VOUT Output Pin
5 VOUT Output Pin of Voltage Regulator
Input Pin 4 VDD Input Pin
127
RX-A3010/RX-V3071
A B
C D
DIGITAL1 1/9
RX-A3010/RX-V3071
A B
C D
DIGITAL1 2/9
A B C D E F G H
RX-A3010/RX-V3071
DIGITAL1 2/9
1 Page 144 M6
to VIDEO (1)_CB303
Page 144 M5
CB23
to VIDEO (1)_CB302
CB21
CB22
DIGITAL1 (1)
2
IC26
IC27
3
VIDEO
4 ENCODER
IC22 to D
5
to D
RX-A3010/RX-V3071
A B
C D
DIGITAL1 2/9
H I J K L M N
IC31: TMDS141RHAR
HDMI switch
VSADJ 30
OE 6
VIDEO AUX PRE 7
VCC
HDMI IN
RINT
RX2 2 9 TX2
TMDS TMDS
CB31 Receiver Driver
w/EQ
Rx2 1 VCC
10 Tx2
RINT
RX1 39 12 TX1
TMDS TMDS
Receiver Driver
w/EQ
RX1 38 13 TX1
VCC
) DIGITAL1 (2) RX0 36
RINT
15 TX0
TMDS TMDS
Receiver Driver
w/EQ
RX0 35 16 TX0
VCC
RINT
RXC 33 18 TXC
TMDS TMDS
Receiver Driver
w/EQ
RXC 32 19 TXC
RSCL 29 22 TSCL
RSDA 28 23 TSDA
I2CEN 5
OVS 25
IC32: TRS3221ECPWR
3 V to 5.5 V single channel RS-232 line driver/receiver
with