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Compal Confidential
Model Name : V5WE2/T2/C2 (EA/EG/BA50_HW)
File Name : LA-9531P
1 1




Compal Confidential
2 2




EA50_HW M/B Schematics Document
Intel Shark Bay ULT (Hasswell + Lynx Point-LP)

AMD MARS / SUN

3 2013-03-04 3




REV:0.4




4 4


ZZZ
Part Number Description

DA60000XL00 PCB 0VR LA-9531P REV0 M/B
V5WE2_PCB
Security Classification Compal Secret Data Compal Electronics, Inc.
PWZZZ 45PWR@ 2012/07/10 2013/07/10 Title
Part Number Description
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DC30100NK00 CONN SET 0VR DC-MB 2DW2024-015121F DIS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.4
V5WE2_DCIN_Cable MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, March 04, 2013 Sheet 1 of 52
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CRT Conn.
Fan Control
page 28 page 36




DP to VGA HDMI Conn. eDP Conn.
1 1
ITE IT6511FN page 26 page 25
204pin DDR3L-SO-DIMM X1
page 27
eDP
Intel Haswell ULT BANK 0, 1, 2, 3 page 15
DP x 2 lanes HDMI x 4 lanes Memory BUS
2.7GT/s 2.97GT/s Dual Channel
DDI
Haswell ULT
Processor 1.35V DDR3L 1333/1600 204pin DDR3L-SO-DIMM X1
BANK 4, 5, 6, 7 page 16


MINI Card AMD SUN/MARS OPI
WLAN with DDR3 x4 or 8
USB port 4 page 31 page 17~23

PCIe 2.0 PCIe 2.0 x4 USB 3.0 USB 2.0 CMOS Finger
5GT/s 5GT/s conn x1 conn x2 Camera Print
2

port 4 port 5
Lynx Point - LP USB port 0 USB/B (port 1,2) USB port 7 USB (port 5)
2

Flexible IO
page 33 page 33 page 25 page 26
PCH
PCIe 2.0 48MHz
5GT/s USBx8
SATA3.0 SATA3.0
port 3 6.0 Gb/s 6.0 Gb/s
port 0 port 2 HD Audio 3.3V 24MHz
Touch
LAN(GbE) SATA HDD SATA CDROM Screen
Boardcom USB (port 6)
Conn. Conn. 1168pin BGA HDA Codec
page 25
57786Xpage 29 page 32 page 32 ALC3225
page 04~14 page 36
SPI


3
Card Reader LPC BUS 3
2 in 1 SPI ROM x2
(SD) CLK=24MHz Int. Speaker Int. MIC Combo Jack
page 30 page 7
ENE page 36 page 36 page 36

KB9012
page 34

RTC CKT. Sub Board
page 6
Touch Pad Int.KBD
LS-5931P page 35 page 35

Power On/Off CKT. PWR/B
page 33
page 35

LS-5932P EC ROM x1
4
DC/DC Interface CKT. USB/B (port 1,2) (reserved) 34
4

page
page 38 page 33

Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
Power Circuit DC/DC Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 39~49 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: W ednesday, March 06, 2013 Sheet 2 of 52
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+0.675VS +0.675VS power rail for DDR3L terminator ON OFF OFF Board ID / SKU ID Table for AD channel
+1.05VS_VTT +1.05V power rail for CPU ON OFF OFF Vcc 3.3V +/- 5%
+0.95VSDGPU +0.95VSDGPU switched power rail for GPU ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.35V +1.35V power rail for DDR3L ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS +1.5V power rail for CPU ON OFF OFF 0 0 0 V 0 V 0 V
+1.5VSDGPU +1.5VSDGPU power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+1.8VSDGPU +1.8VSDGPU power rail for GPU ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW +3VALW always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VLP B+ to +3VLP power rail for suspend power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS +3VALW to +3VS power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+3VSDGPU +3VS to +3VSDGPU power rail for GPU ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VS +3VALW to +5VS power rail ON OFF OFF
+RTCVCC RTC power ON ON ON
BOARD ID Table BTO Option Table
2 2
BTO Item BOM Structure
Board ID PCB Revision Unpop @
0 0.1 Connector CONN@
1 0.2 EC 932 940@
2 0.3 EC 9012 9012@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 3 0.4 UMA Component UMA@
4 1.0 AMD GPU VGA@
EC SM Bus1 address EC SM Bus2 address 5 1 SPI ROM 1ROM@
6 2 SPI ROM 2ROM@
Device Address Device Address
Smart Battery 0001 011X On Board Thermal Senser 0100 110x
7 Assembly Level 45@
VGA Internal Thermal Senser 0100 000x
Cable for Power 45PWR@
USB Port Table KB Backlight BL@
G Senser 0011 000x
3 External Debug Only DEG@
PCH SM Bus address USB 2.0 Port
USB Port EMC Component EMC@
0 USB Port(Left 3.0) Reservec for EMC XEMC@
Device Address
ChannelA DIMM0 1001 000x JDIMM1
1 USB Port(Right 2.0) eDP to LVDS TL@
3 3
ChannelB DIMM1 1001 010x JDIMM2
2 USB Port(Right 2.0) TPM Module TPM@
3 G-Sensor GSEN@
EHCI1
4 Mini Card (WLAN+BT) V5WE2/T2/C2 EA50@
5 Reserved BA51@
6 Touch Screen TS@
7 Camera For IOAC IOAC@
For EDP panel EDP@

Mars component MARS@
SUN component SUN@
VRAM x 8pcs 128@


USB 3.0 Port VRAM Selection X76@
0 USB Port(Left 3.0) Micron 4G x 8 X7601@
1 Hynix 2G x 4 X7603@
4 XHCI 4
2 Hynix 2G x 8 X7604@
3


Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Wednesday, March 06, 2013 Sheet 3 of 52
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5 4 3 2 1

HASWELL_MCP_E
U1A




C54 C45
27 CPU_DP1_N0 DDI1_TXN0 EDP_TXN0 EDP_TXN0 25
C55 B46
27 CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 25
B58 A47
27 CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 25
C58 B47
DP to CRT 27 CPU_DP1_P1
B55 DDI1_TXP1
DDI1_TXN2
EDP_TXP1 EDP_TXP1 25
A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
D D
C51 EDP_TXP3
26 CPU_DP2_N0 DDI2_TXN0
C50 A45 EDP_AUXN 25
26 CPU_DP2_P0 DDI2_TXP0 EDP_AUXN
C53 B45 EDP_AUXP 25
26 CPU_DP2_N1 DDI2_TXN1 EDP_AUXP
B54
HDMI 26
26
CPU_DP2_P1
CPU_DP2_N2
C49 DDI2_TXP1
DDI2_TXN2 EDP_RCOMP
D20 EDP_COMP R1 1 2 24.9_0402_1% +VCCIOA_OUT
B50 A43 Trace width=20 mils,Spacing=25mil,Max length=100mils
26 CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
A53
26 CPU_DP2_N3 DDI2_TXN3
B53
26 CPU_DP2_P3 DDI2_TXP3 EDP_DISP_UTIL 25




1 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168
@

Reserved for ESD
HASWELL_MCP_E
U1B

C94 1 2 6.8P_0402_50V8C
XEMC@ T20 @ D61
T2 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#_R @ T157
+1.35V 34 H_PECI PECI PRDY K62 XDP_PREQ#_R @ T158
2 1 R68 R8 JTAG
PREQ E60 XDP_TCK_R @ T159
+1.05VS_VTT PROC_TCK
62_0402_5% 56_0402_5% E61 XDP_TMS_R @ T160
1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST#_R @ T161
34,39,40 H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI_R @ T162
PROC_TDI
1




C C95 1 2 6.8P_0402_50V8C F62 XDP_TDO_R @ T163 C
PROC_TDO
R184 Reserved for ESD XEMC@
470_0603_5% R6 1 2 10K_0402_5% H_CPUPW RGD C61
PROCPWRGD PWR
C60 1 2 6.8P_0402_50V8C J60 XDP_BPM#0_R @ T164
2




XEMC@ BPM#0 H60 XDP_BPM#1_R @ T165
DIMM_DRAMRST# 15,16 BPM#1
Reserved for ESD H61 @ T148
BPM#2 H62 @ T149
2 BPM#3
R11 1 2 200_0402_1% SM_RCOMP0 AU60 K59 @ T150
C96 Close to AV15 R13 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3 BPM#4 H63 @ T151
R41 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 @ T152
6.8P_0402_50V8C SM_RCOMP2 BPM#6
1 DIMM_DRAMRST# AV15 J61 @ T153
XEMC@ SM_DRAMRST BPM#7
DDR_PG_CTRL AV61
15 DDR_PG_CTRL SM_PG_CNTL1
DDR3 Compensation Signals
Reserved for ESD 1120 2 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168
@




B B




A A


U1 U1 U1 U1



Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
CPU_QEK2_C0 CPU_QEK4_C0 CPU_QEVG_C0 CPU_QEVE_C0
Issued Date Deciphered Date HSW MCP(1/11) DDI,MSIC,XDP
QEK2@ QEK4@ QEVG@ QEVE@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SA00006SJ40 SA00006NM50 SA00006SX30 SA00006SM30 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, February 26, 2013 Sheet 4 of 52
5 4 3 2 1
5 4 3 2 1


HASWELL_MCP_E
U1C
HASWELL_MCP_E
U1D

DDR_A_D0 AH63 AU37
SA_DQ0 SA_CLK#0 SA_CLK_DDR#0 15
DDR_A_D1 AH62 AV37
SA_DQ1 SA_CLK0 SA_CLK_DDR0 15
DDR_A_D2 AK63 AW36 DDR_B_D0 AY31 AM38
SA_DQ2 SA_CLK#1 SA_CLK_DDR#1 15 SB_DQ0 SB_CK#0 SB_CLK_DDR#0 16
DDR_A_D3 AK62 AY36 DDR_B_D1 AW31 AN38
SA_DQ3 SA_CLK1 SA_CLK_DDR1 15 SB_DQ1 SB_CK0 SB_CLK_DDR0 16
DDR_A_D4 AH61 DDR_B_D2 AY29 AK38
SA_DQ4 SB_DQ2 SB_CK#1 SB_CLK_DDR#1 16
DDR_A_D5 AH60 AU43 DDR_B_D3 AW29 AL38
SA_DQ5 SA_CKE0 DDRA_CKE0_DIMMA 15 SB_DQ3 SB_CK1 SB_CLK_DDR1 16
DDR_A_D6 AK61 AW43 DDR_B_D4 AV31
SA_DQ6 SA_CKE1 DDRA_CKE1_DIMMA 15 SB_DQ4
DDR_A_D7 AK60 AY42 DDR_B_D5 AU31 AY49
SA_DQ7 SA_CKE2 SB_DQ5 SB_CKE0 DDRB_CKE0_DIMMB 16
DDR_A_D8 AM63 AY43 DDR_B_D6 AV29 AU50
SA_DQ8 SA_CKE3 SB_DQ6 SB_CKE1 DDRB_CKE1_DIMMB 16
D DDR_A_D9 AM62 DDR_B_D7 AU29 AW49 D
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_B_D8 AY27 SB_DQ7 SB_CKE2 AV50
SA_DQ10 SA_CS#0 DDRA_CS0_DIMMA# 15 SB_DQ8 SB_CKE3
DDR_A_D11 AP62 AR32 DDR_B_D9 AW27
SA_DQ11 SA_CS#1 DDRA_CS1_DIMMA# 15 SB_DQ9
DDR_A_D12 AM61 DDR_B_D10 AY25 AM32
SA_DQ12 SB_DQ10 SB_CS#0 DDRB_CS0_DIMMB# 16
DDR_A_D13 AM60 AP32 DDRA_ODT0 @ T4 DDR_B_D11 AW25 AK32
SA_DQ13 SA_ODT0