Text preview for : quanta_zqz_r1a_schematics.pdf part of acer quanta zqz r1a schematics acer Notebook Ноутбук Acer Aspire E1-421 quanta_zqz_r1a_schematics.pdf
Back to : quanta_zqz_r1a_schematics | Home
1 2 3 4 5 6 7 8
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND
ZQZ SYSTEM DIAGRAM
LAYER 3 : IN1
DDR3- SODIMM2 DDR3- SODIMM1 DDR3 HDMI
PAGE 7 PAGE 6 HDMI PAGE 14
LAYER 4 : IN2 Channel A AMD Brazos CRT
LAYER 5 : VCC CRT PAGE 13
A
LAYER 6 : BOT FAN SCH. FT1 TDP~18W LVDS A
CPU (PROCHOT) LVDS PAGE 13
E.C. (CPUFAN#) 19mmX19mm 413pin BGA
eDP@ -----> eDP panel
32.768KHz eDP PAGE 13
lvds@ -----> lvds panel 25MHz PAGE 23
UMA only
CPU SideBand TemperatureSense I2C PAGE 3,4,5
HT3
1.8GHz
PCI-Expresss
B
P0 AMD B
LAN Hudson-M3
Atheros
AR8151 24.5mmX24.5mm, 656pin BGA
(10/100/1000) TDP~4.7W
PAGE 16
25MHz
RJ45
PAGE 16
P0 P9 P13
FFC
USB2.0 Port Blue Tooth Web-Camera
SATA - HDD SATA0 150MB
C on board x1 C
CHARGER (BQ24707A) 3 Gb/s
PAGE 18 PAGE 21 PAGE 21 PAGE 13 USB BOARD
PAGE 26
P4 P10 USB2.0 Ports x2
SATA - ODD SATA1 150MB
AMD CPU CORE (OZ8380) PAGE
CPU 3 Gb/s PAGE 8,9,10,11,12 Mini Card CardReader
PAGE 28 PAGE 18
PCLK_DEBUG WLAN & Debug AU6435
LPC Azalia & mSATA PAGE 15
1.-05V (TPS51211)
PAGE30 NB CLK_PCI_775
Winbond KBC Audio CODEC
NPCE885 Conexant PAGE 17 12MHz
DDR 1.5V(TPS51216) CPU SideBand TemperatureSense I2C CX20584-11Z
PAGE 31 PAGE 24 PAGE 19
SYSTEM 5V/3V (RT8223M)
PAGE 27
D D
Keyboard SPI ROM INT MIC AUDIO CONN Speaker CN
1.1V(TPS51211)
TouchPad (H.P./ MIC)
PAGE 29
PAGE 23 PAGE 10 PAGE 20 PAGE 20 PAGE 20
Quanta Computer Inc.
Discharge /Thermal protec PROJECT : ZQZ
PAGE 31 Size Document Number Rev
Block Diagram 1A
Date: Thursday, February 23, 2012 Sheet 1 of 32
1 2 3 4 5 6 7 8
5 4 3 2 1
INDEX
Power Sequence 02
PAGE# DESCRIPTION NOTE
AC IN
1 BLOCK DIAGRAM Hudson M1 SM BUS
3V/5VPCU
2 SYSTEM INFORMATION
SB820 SMBUS Pin NO. SMBUS Function Define
3 ONTARIO MEM & PCIE I/F(1/3) NBSWON#
D D
PCLK_SMB AD22
4 ONTATIO DISPLAY/CLK/MI(2/3) DDR / RFID
DNBSWON# PDAT_SMB AE22
5 ONTARIO POWER & DECOUP(3/3) (+3V)
S5_ON/S5
6 DDR3 SO-DIMM (STD) SB_SMBCLK1 F5
not used
SB_SMBDATA1 F4
7 DDR3 SO-DIMM (STD) RSMRST#
(+3V_S5)
8 08 -- FCH 1/5(GPIO/USB/AZ)
SB_SCLK2 D25
PCIE_WAKE# not used
9 09 -- FCH 2/5(ACPI/PCI/CLK) SB_SDATA2 F23
(+3V_S5)
10 10 -- FCH 3/5(SATA/VGA/GND/SPI) SUSC
SB_SCLK3 B26
11 11 -- FCH 4/5(POWER) not used
SUSB SB_SDATA3 E26
12 12 -- FCH 5/5(Strap/PWRGD) (+3V_S5)
SUSON
13 13-- CRT/LVDS&CCD SB_SCLK3 B26
not used
SB_SDATA3 E26
14 14 -- HDMI_CONN MAINON
(+3V_S5)
15 15 -- CardReader AU6435-GDL
VR_ON
C C
16 16 -- LAN AR8151
CPU_CORE
17 17 -- MINI PCIE
KBC(EC) SM BUS
18 18 -- SATA-HDD/ODD VRM_PWRGD
KBC SMBUS Pin NO. SMBUS Function Define
19 19--Codec(CX20584-21Z)
HWPG
20 20--AUDIO-JACK/MDC/MIC MBCLK 110
Battery
ECPWROK MBDATA 111
21 21 -- INT&EXT USB/BT
(+3VPCU)
22 22 -- LED/ EMI/ Screw Hole& Nut SB_PWRGD_IN
MBCLK_THRM 115
Thermal
23 23 -- KB/TP/FAN MBDATA_THRM 116
CPU RESET
(+3VPCU)
24 24 -- NPCE885/FLASH
CPU POWER OK
25 25 -- NPCE895L
26 26 -- Charger (BQ24707A)
27 27 -- SYSTEM 5V/3V (RT8223M)
B B
28 28 -- CPU_CORE_Brazos (OZ8380)
29 29 -- +1.1V_S5(TPS51211)
30 30 -- +1.05V(TPS51211)
31 31 -- DDR 1.5V(TPS51216)
32 32 -- +1.8V/Discharge /Thermal
33 33--CHANGE LIST
A A
Quanta Computer Inc.
PROJECT : ZQZ
Size Document Number Rev
System Information 1A
Date: Thursday, February 23, 2012 Sheet 2 of 32
5 4 3 2 1
1 2 3 4 5 6 7 8
{6,7} M_A_A[15:0]
M_A_A0
M_A_A1
R17 M_ADD0
ONTARIO (2.0)
U16E
M_DATA0 B14 M_A_DQ0
M_A_DQ1
M_A_DQ[0..63] {6,7} +1.5VSUS {4,5,6,7,10,11,23,30}
VDD_10 {5} 03
H19 M_ADD1
PART 1 OF 5
M_DATA1 A15
M_A_A2 J17 A17 M_A_DQ2
M_A_A3 H18
M_ADD2
M_ADD3
M_DATA2
M_DATA3 D18 M_A_DQ3 This page is different AMD Nile
M_A_A4 H17 M_ADD4 M_DATA4 A14 M_A_DQ4
M_A_A5 G17 M_ADD5 M_DATA5 C14 M_A_DQ5
M_A_A6 H15 M_ADD6 M_DATA6 C16 M_A_DQ6
A M_A_A7 M_A_DQ7 A
G18 M_ADD7 M_DATA7 D16
M_A_A8 F19 M_ADD8
U16A
M_A_A9 E19 M_ADD9 M_DATA8 C18 M_A_DQ8 AA6 P_GPP_RXP0 P_GPP_TXP0 AB6 PCIE_TXP0_LAN_C C361 0.1u/10V_4 PCIE_TXP0_LAN {16}
{16} PCIE_RXP0_LAN
M_A_A10 T19 M_ADD10 M_DATA9 A19 M_A_DQ9 Y6 P_GPP_RXN0 P_GPP_TXN0 AC6 PCIE_TXN0_LAN_C C362 0.1u/10V_4 PCIE_TXN0_LAN {16}
LAN
{16} PCIE_RXN0_LAN
M_A_A11 F17 M_ADD11 M_DATA10 B21 M_A_DQ10 ONTARIO (2.0)
M_A_A12 E18 M_ADD12 M_DATA11 D20 M_A_DQ11 AB4 P_GPP_RXP1
PART 2 OF 5
P_GPP_TXP1 AB3 PCIE_TXP1_C C354 0.1u/10V_4 PCIE_TXP1 {17}
{17} PCIE_RXP1 WLAN
M_A_A13 W17 M_ADD13 M_DATA12 A18 M_A_DQ12 AC4 P_GPP_RXN1 P_GPP_TXN1 AC3 PCIE_TXN1_C C355 0.1u/10V_4 PCIE_TXN1 {17}
{17} PCIE_RXN1
M_A_A14 E16 M_ADD14 M_DATA13 B18 M_A_DQ13
M_A_A15 G15 M_ADD15 M_DATA14 A21 M_A_DQ14 AA1 P_GPP_RXP2 P_GPP_TXP2 Y1
{6,7} M_A_BS[2..0]
M_DATA15 C20 M_A_DQ15 AA2 P_GPP_RXN2 P_GPP_TXN2 Y2
PCIE I/F
M_A_BS0 R18 M_BANK0
M_A_BS1 T18 M_BANK1 M_DATA16 C23 M_A_DQ16 VDD_10 Y4 P_GPP_RXP3 P_GPP_TXP3 V3
M_A_BS2 F16 M_BANK2 M_DATA17 D23 M_A_DQ17 Y3 P_GPP_RXN3 P_GPP_TXN3 V4
{6,7} M_A_DM[7..0]
M_DATA18 F23 M_A_DQ18
M_A_DM0 D15 M_DM0 M_DATA19 F22 M_A_DQ19 R335 2K/F_4 ON_ZVDD Y14 P_ZVDD_10 P_ZVSS AA14 ON_ZVSS R345 1.27K/F_4
M_A_DM1 B19 M_DM1 M_DATA20 C22 M_A_DQ20
M_A_DM2 D21 M_DM2 M_DATA21 D22 M_A_DQ21
M_A_DM3 H22 M_DM3 M_DATA22 F20 M_A_DQ22
M_A_DM4 P23 M_DM4 M_DATA23 F21 M_A_DQ23 {9} UMI_RXP0 AA12 P_UMI_RXP0 P_UMI_TXP0 AB12 UMI_TXP0_C C386 0.1u/10V_4 UMI_TXP0 {9}
M_A_DM5 V23 M_DM5 {9} UMI_RXN0 Y12 P_UMI_RXN0 P_UMI_TXN0 AC12 UMI_TXN0_C C387 0.1u/10V_4 UMI_TXN0 {9}
M_A_DM6 AB20 M_DM6 M_DATA24 H21 M_A_DQ24
M_A_DM7 AA16 M_DM7 M_DATA25 H23 M_A_DQ25 {9} UMI_RXP1 AA10 P_UMI_RXP1 P_UMI_TXP1 AC11 UMI_TXP1_C C380 0.1u/10V_4 UMI_TXP1 {9}
M_DATA26 K22 M_A_DQ26 {9} UMI_RXN1 Y10 P_UMI_RXN1 P_UMI_TXN1 AB11 UMI_TXN1_C C384 0.1u/10V_4 UMI_TXN1 {9}
UMI I/F
A16 M_DQS_H0 M_DATA27 K21 M_A_DQ27
B {6,7} M_A_DQSP0 B
B16 M_DQS_L0 M_DATA28 G23 M_A_DQ28 {9} UMI_RXP2 AB10 P_UMI_RXP2 P_UMI_TXP2 AA8 UMI_TXP2_C C373 0.1u/10V_4 UMI_TXP2 {9}
{6,7} M_A_DQSN0
B20 M_DQS_H1 M_DATA29 H20 M_A_DQ29 {9} UMI_RXN2 AC10 P_UMI_RXN2 P_UMI_TXN2 Y8 UMI_TXN2_C C376 0.1u/10V_4 UMI_TXN2 {9}
{6,7} M_A_DQSP1
A20 M_DQS_L1 M_DATA30 K20 M_A_DQ30
{6,7} M_A_DQSN1
E23 M_DQS_H2 M_DATA31 K23 M_A_DQ31 {9} UMI_RXP3 AC7 P_UMI_RXP3 P_UMI_TXP3 AB8 UMI_TXP3_C C366 0.1u/10V_4 UMI_TXP3 {9}
{6,7} M_A_DQSP2
{6,7} M_A_DQSN2 E22 M_DQS_L2 {9} UMI_RXN3 AB7 P_UMI_RXN3 P_UMI_TXN3 AC8 UMI_TXN3_C C371 0.1u/10V_4 UMI_TXN3 {9}
MEMORY I/F
J22 M_DQS_H3 M_DATA32 N23 M_A_DQ32
{6,7} M_A_DQSP3
J23 M_DQS_L3 M_DATA33 P21 M_A_DQ33 SP@FT1_ONTARIO
{6,7} M_A_DQSN3
R22 M_DQS_H4 M_DATA34 T20 M_A_DQ34
{6,7} M_A_DQSP4
P22 M_DQS_L4 M_DATA35 T23 M_A_DQ35
{6,7} M_A_DQSN4
W22 M_DQS_H5 M_DATA36 M20 M_A_DQ36
{6,7} M_A_DQSP5
V22 M_DQS_L5 M_DATA37 P20 M_A_DQ37
{6,7} M_A_DQSN5
AC20 M_DQS_H6 M_DATA38 R23 M_A_DQ38
{6,7} M_A_DQSP6
AC21 M_DQS_L6 M_DATA39 T22 M_A_DQ39
{6,7} M_A_DQSN6
{6,7} M_A_DQSP7 AB16 M_DQS_H7
AC16 M_DQS_L7 M_DATA40 V20 M_A_DQ40 +M_VREF +1.5VSUS
{6,7} M_A_DQSN7
M_DATA41 V21 M_A_DQ41
M17 M_CLK_H0 M_DATA42 Y23 M_A_DQ42
{6} M_A_CLKP0
M16 M_CLK_L0 M_DATA43 Y22 M_A_DQ43
{6} M_A_CLKN0
M19 M_CLK_H1 M_DATA44 T21 M_A_DQ44 R368 +1.5VSUS R372 *2.2K_4
{6} M_A_CLKP1
M18 M_CLK_L1 M_DATA45 U23 M_A_DQ45 1K/F_4
{6} M_A_CLKN1
N18 M_CLK_H2 M_DATA46 W23 M_A_DQ46
{7} M_A_CLKP2
2
N19 M_CLK_L2 M_DATA47 Y21 M_A_DQ47 +1.5VSUS R369 *1K/F_4 Q20
{7} M_A_CLKN2
L18 M_CLK_H3 *MMBT3904
{7} M_A_CLKP3
C {7} M_A_CLKN3 L17 M_CLK_L3 M_DATA48 Y20 M_A_DQ48 M_A_EVENT# 1 3 R370 *0_4
APU_MEMHOT# {8} C
M_DATA49 AB22 M_A_DQ49
{6,7} M_A_RST# L23 M_RESET_L M_DATA50 AC19 M_A_DQ50 R367 C404 C403
M_A_EVENT# N17 M_EVENT_L M_DATA51 AA18 M_A_DQ51 1K/F_4
{6,7} M_A_EVENT#
M_DATA52 AA23 M_A_DQ52 0.1u/10V_4 1000p/50V_4
M_DATA53 AA20 M_A_DQ53
M_A_CKE0 F15 M_CKE0 M_DATA54 AB19 M_A_DQ54
{6,7} M_A_CKE0
M_A_CKE1 E15 M_CKE1 M_DATA55 Y18 M_A_DQ55
{6,7} M_A_CKE1
M_DATA56 AC17 M_A_DQ56
M_DATA57 Y16 M_A_DQ57
{6} M_A_ODT0 W19 M0_ODT0 M_DATA58 AB14 M_A_DQ58 Brazos APU B0 CKE Race condition issue
{6} M_A_ODT1 V15 M0_ODT1 M_DATA59 AC14 M_A_DQ59 workaround : a resistor of 68 ohms between M_CKE [ 1:0 ] and ground eliminates the floating signal .
{7} M_A_ODT2 U19 M1_ODT0 M_DATA60 AC18 M_A_DQ60
{7} M_A_ODT3 W15 M1_ODT1 M_DATA61 AB18 M_A_DQ61 M_A_CKE0
M_DATA62 AB15 M_A_DQ62
{6} M_A_CS#0 T17 M0_CS_L0 M_DATA63 AC15 M_A_DQ63 M_A_CKE1
{6} M_A_CS#1 W16 M0_CS_L1
{7} M_A_CS#2 U17 M1_CS_L0
V16 M1_CS_L1 M_VREF M23 +M_VREF R113 R125
{7} M_A_CS#3
*68_4 *68_4
{6,7} M_A_RAS# U18 M_RAS_L
{6,7} M_A_CAS# V19 M_CAS_L
V17 M_WE_L M_ZVDDIO_MEM_S M22 39.2/F_4 R366 +1.5VSUS
D
{6,7} M_A_WE# D
SP@FT1_ONTARIO ?
P/N Item Description
AJ01200TT00 CPU(413P)EM1200GBB22GV 1.4G(BGA)
AJ01200TT01 CPU(413P)EM1200GBB22GV 1.4G(BGA)STN BSQ Quanta Computer Inc.
AJ01800VT00 CPU(413P)EM1800GBB22GV 1.7G(BGA)
AJ01800VT01 CPU(413P)EM1800GBB22GV 1.7G(BGA)STN BSQ PROJECT : ZQZ
Size Document Number Rev
ONTARIO MEM & PCIE I/F(1/3) 1A
Date: Thursday, February 23, 2012 Sheet 3 of 32
1 2 3 4 5 6 7 8
1
+1.8V
R208 1K/F_4 APU_SVC
+1.8V
+3V
{5,23,31}
{5,6,7,8,9,10,11,12,13,14,15,17,18,19,20,22,23,24,26,27,28,29,30,31} 04
R207 1K/F_4 APU_SVD
R199 300_4 LDT_RST#
U16B
R298 300_4 APU_PWRGD ANALOG/DISPLAY/MISC
0.1u/10V_4 C367 PEG_HDMI_TXDP2 A8 TDP1_TXP0 DP_ZVSS H3 R221 150/F_4
+3V {14} TX2_HDMI+
0.1u/10V_4 C372 PEG_HDMI_TXDN2 B8 TDP1_TXN0
{14} TX2_HDMI-
DP_BLON G2 R237 *Short_4 INT_LVDS_BLON {13}
DP MISC
0.1u/10V_4 C375 PEG_HDMI_TXDP1 B9 TDP1_TXP1 DP_DIGON H2 R204 *Short_4 INT_LVDS_DIGON {13}
{14} TX1_HDMI+
R303 1K/F_4 APU_THERMTRIP# 0.1u/10V_4 C378 PEG_HDMI_TXDN1 A9 TDP1_TXN1 DP_VARY_BL H1 R222 *Short_4
INT_LVDS_PWM {13}
DISPLAYPORT 1
{14} TX1_HDMI-
R214 1K/F_4 APU_ALERT# R205 100K_4
0.1u/10V_4 C379 PEG_HDMI_TXDP0 D10 TDP1_TXP2
{14} TX0_HDMI+
0.1u/10V_4 C381 PEG_HDMI_TXDN0 C10 TDP1_TXN2 TDP1_AUXP B2
{14} TX0_HDMI- HDMI_DDCCLK {14}
TDP1_AUXN C2 HDMI_DDCDATA {14}
0.1u/10V_4 C382 PEG_HDMI_TXCP A10 TDP1_TXP3
{14} TXC_HDMI+
0.1u/10V_4 C385 PEG_HDMI_TXCN B10 TDP1_TXN3 TDP1_HPD C1 INT_HDMI_HPD {14}
{14} TXC_HDMI-
R302 1K/F_4 H_PROCHOT#
{13} INT_TXLOUTP2 B5 LTDP0_TXP0 LTDP0_AUXP A3 INT_EDIDCLK {13}
{13} INT_TXLOUTN2 A5 LTDP0_TXN0 LTDP0_AUXN B3 INT_EDIDDATA {13}
{13} INT_TXLOUTP1 D6 LTDP0_TXP1 LTDP0_HPD D3 INT_eDPI_HPD INT_eDPI_HPD {13}
{13} INT_TXLOUTN1 C6 LTDP0_TXN1
DISPLAYPORT 0
DAC_RED C12 INT_CRT_RED {13}
{13} INT_TXLOUTP0 A6 LTDP0_TXP2 DAC_REDB D13
{13} INT_TXLOUTN0 B6 LTDP0_TXN2 DAC_GREEN A12 INT_CRT_GRE {13}
DAC_GREENB B12
INT_CRT_RED R338 150/F_4 {13} INT_TXLCLKP D8 LTDP0_TXP3 DAC_BLUE A13 INT_CRT_BLU {13}
INT_CRT_GRE R339 150/F_4 C8 LTDP0_TXN3 DAC_BLUEB B13
{13} INT_TXLCLKN
INT_CRT_BLU R343 150/F_4
{9} CLK_APU_P V2 CLKIN_H DAC_HSYNC E1 INT_CRT_HSYNC {13}
VGA DAC
{9} CLK_APU_N V1 CLKIN_L DAC_VSYNC E2 INT_CRT_VSYNC {13}
+3V
CLK
{9} CLK_DP_P D2 DISP_CLKIN_H DAC_SCL F2 INT_DDCCLK {13}
[email protected]/F_4 R314 INT_EDIDCLK D1 DISP_CLKIN_L DAC_SDA D4
{9} CLK_DP_N INT_DDCDATA {13}
[email protected]/F_4 R304 INT_EDIDDATA
APU_SVC J1 SVC DAC_ZVSS D12 DAC_RSET R75 499/F_4
APU_SVD J2 SVD
TEST4 R1 APU_THERMDA
T30
APU_SIC APU_THERMDC
SER
P3 SIC TEST5 R2 T28
+3V APU_SID P4 SID TEST6 R6 APU_TEST6_DIRECRACKMON
T2
TEST14 T5 APU_BP0_TSTCLK_USCLK0
T4
R255 *Short_4 LDT_RST#_R T3 RESET_L TEST15 E4 T16
{9,23} LDT_RST#
R297 *Short_4 APU_PWRGD_R T4 PWROK TEST16 K4 APU_BP3_SCANSHIFTEND_USDATA1
T27
{9,23} APU_PWRGD APU_BP2_SCANSHIFTEN_USDATA0
TEST17 L1 T31