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OKIPAGE4w
LED Page Printer
Troubleshooting Manual
with Component Parts List
(ODA/OEL/INT)
APPROVAL
All specifications are subject to change without notice.
CONTENTS
1. OUTLINE..................................................................................................... 1
2. TOOLS ........................................................................................................ 1
3. CIRCUIT DESCRIPTION ............................................................................ 2
4. TROUBLESHOOTING .............................................................................. 21
5. CIRCUIT DIAGRAM .................................................................................. 27
6. COMPONENT PARTS LIST
1. OUTLINE
This manual has been written to provide guidance for troubleshooting of the OKIPAGE4w Plus
Printer (primarily for its printed circuit boards), on an assumption that the reader is knowledgeable
of the printer. Read the maintenance manual for this printer P/N M-521426 if necessary.
Note:
1. High voltage power supply board and power supply unit containing a high voltage power
supply is dangerous. From the viewpoint of the safety standards, the local repairing of a
defective board is not allowed. Thus, the objects to be locally repaired as a result of
troubleshooting are switches and fuses.
2. TOOLS
For troubleshooting the printer, the tools listed below may be needed in addition to general
maintenance tools.
Tool Remarks
Oscilloscope Frequency response 100 MHz or higher
Soldering iron A slender tip type, 15-20 watts
Extension code kit P/N : 40105501
-1-
3. CIRCUIT DESCRIPTION
3.1 Outline
The circuit of OKIPAGE4w Plus consists of a main control board, a high voltage power supply
board and a power supply unit. The block diagram is shown in Fig. 3-1. The main control board
controls the reception and transmission of data with a host I/f and processes command analysis,
bit image development, raster buffer read. It also controls the engine and high voltage outputs.
(1) Reception and transmission control
The main control board has one parallel I/F port which is compliant to the IEEE 1284
specification.
An interface task stores all data received from the host into a receive buffer first, and returns
the printer status upon request of the host.
(2) Command analysis processing
The OKIPAGE4w Plus printer has the following emulation mode.
Hiper-W: OKI original
An edit task fetches data from the receive buffer, analizes commands, and sets I/O registers.
(3) Raster data processing
The decompression circuit in the CPU expands the compressed data and stores the data into
the raster buffer.
(4) Raster data transfer
The LED head control circuit in the CPU sends the data stored in the raster buffer to the LED
head.
(5) High voltage control
The high voltage control circuit in the CPU.
The high voltage power supply board generates high voltage outputs, and have sensors, LED for
display.
The power supply unit generates +24VDC output, +5DC output.
-2-
CN
10MHz A8 ~ A15 D0 ~ D7 Parallel
CPU EPROM I/F Parallel
(MSM65917) (64 KByte) I/F
LS07
EEPROM AD0 ~ AD7 A0 ~ A7
Address
Parallel latch
I/F
Figure 3-1 OKIPAGE4w Plus Block Diagram
LED head LED head
Main motor Driver M Main motor
LED head
Electromagnetic Electromagnetic
Main motor Driver
clutch clutch
Electromagnetic
clutch D0 ~ D3
-3-
LED LED Manual feed sensor
Paper sensor
D-RAM Outlet sensor
Sensors Sensors
A0 ~ A9 128 KByte Toner sensor
TEMP or Cover open switch
TR-VSEN 512 KByte
TR-ISEN TEMP Thermistor
High-voltage HIgh voltage
power power EP cartridge
Reset TR-VSEN
5V supply
circuit TR-ISEN
Driver High-voltage power I/F
5V
Heater
LED HEAT ON Driver AC output ON/OFF (Halogen lamp)
0VL HEAT ON
+24V Switching
+5V AC
0VL power supply (120 V/230 V)
0VP
3.2 CPU and Memory
(1) CPU (MSM65917)
CPU core nX-8
CPU clock 10 MHz
Data bus width External 8 bits, Internal 8 bits
(2) Program ROM
ROM capacity 64k-bytes (512-kbit EPROM)
ROM type 512 kbits (64k x 8 bits)
Access time 150 nsec
When mask ROM in the CPU is valid, the EPROM is not mounted.
(3) Resident RAM
RAM capacity 128k bytes (256k x 4 bits D-RAM one piece)
or 512k bytes (1M x 4 bits D-RAM one piece)
RAM type 1M bits (256k x 4 bits) or 4M bits (1M x 4 bits)
Access time 70 ns, 60 ns
The block diagram of CPU and memory circuit is shown in Fig. 3-2.
-4-
CPU
IC 6 AD00 to AD07 LS373 A00 to A07
IC3
ALE
A08 to A15
IC2
RDN EPROM
ROCS (64k x 8 bits)
DD00 to DD03
DA00 to DA09
IC11
DA10 DRAM
DWR 256k x 4 bits
or
CAS
1M x 4 bits
RAS0
RAS1
RAS2
Main Control Board
Figure 3-2 Block Diagram of CPU & Memory in OKIPAGE4w Plus
-5-
3.3 Reset Control
When power is turned on, RST-N signal is generated by IC5.
+5V +5V
IC5 CPU
1 63
3 RSTN
2
Power ON Power OFF
+5V
RST-N
-6-
3.4 EEPROM Control
The BR93LC46A on the main control board is an electrical erasable/programmable ROM of 64-
bit x 16-bit configuration. Data input to and output from the ROM are bidirectionally transferred
in units of 16 bits through I/O port (EEPRMDT-P) in serial transmission synchronized with a clock
signal from the CPU.
IC4
EEPRMDT-P 3
DI DO
39 4
1 EEPROM
EEPRMCS-P
CPU CS
38
SK
EEPRMCLK-P 2
37
The EEPROM operates in the following instruction modes.
Instruction Start bit Operation Address Data
code
Read (READ) 1 10 A5 to A0
Write Enabled (WEN) 1 00 11XXXX
Write (WRITE) 1 01 A5 to A0 D15 to D0
Write All Address (WRAL) 1 00 01XXXX D15 to D0
Write Disabled (WDS) 1 00 00XXXX
Erase 1 11 A5 to A0
Chip Erasable (ERAL) 1 00 10XXXX
Write cycle timing (WRITE)
Min. 450 ns
CS STATUS
SK 1 2 4 9 10 25
DI 1 0 1 A5 A4 A1 A0 D15 D14 D1 D0
Max. 500 ns
DO BUSY READY
HIGH-Z
Max. 10 ms
Read cycle timing (READ)
CS
SK 1 2 4 9 10 25 26
DI 1 1 0 A5 A4 A1 A0
DO 0 D15 D14 D1 D0 D15 D14
HIGH-Z
-7-
3.5 Parallel Interface
Parallel data is received from a host system via parallel interface which is compliant to the
IEEE1284 specification.
CN4
65 to 68, 71 to 74
DATA8-P
PDATA1-P to PDATA8-P to
DATA1-P
64 2 to 9
PSTB-N
STB-N
IC7 1
78 BUSY-P
BUSY-P
11
77 ACK-N
ACK-N
10
CPU 79 PE-P
PE-P
12
80 SEL-P
SEL-P
13
81 FAULT-N
FAULT-N
32
82 IPRIME-N
IPRIME-N
31
83 SELIN-N
SELIN-N
36
84 AUTOFD-N
AUTOFEED-N
14
+5V +5V
18
Compatible mode
The CPU sets a BUSY-P signal to ON at the same time when it reads the parallel data (PDATA1-
P to PDATA 8-P) from the parallel port at the fall of PSTB-N signal. Furthermore, it makes the
store processing of received data into a receive buffer terminate within a certain fixed time and
outputs an ACK-N signal, setting the BUSY-P signal to OFF.
PARALLEL DATA
(DATA BITs 1 to 8)
0.5