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1 1




Compal Confidential
2 2




JAL90 M/B Schematics Document
Intel Penryn Processor with Cantiga + DDRII + ICH9M




3 2008-07-04 3




REV:1.0




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401551 I
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 21, 2008 Sheet 1 of 50
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A B C D E




Compal Confidential
Intel Penryn Processor Thermal Sensor Clock Generator
Fan Control
Model Name : JAL90 page 36
EMC1402-1-ACZL ICS9LPRS387
uPGA-478 Package page 4 page 16
File Name : LA-4201P
(Socket P) page 4,5,6
1 1
FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)

HDMI Conn. LCD Conn. CRT Conn.
page 20 page 18 page 19
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel Cantiga
LVDS Dual Channel BANK 0, 1, 2, 3 page 14,15

1.8V DDRII 533/667
TMDS LVDS uFCBGA-1329
PCI-Express page 7,8,9,10,11,12,13
Card Reader LS-4201P
16X
JMB385 MXM II VGA/B USB conn x2 Bluetooth CMOS Finger Print
page 26 DMI C-Link
page 17
USB port 0, 2 Conn Camera AES1610
page 30 page 30 page 18 page 30

PCI-Express
2
Intel ICH9-M 3.3V 48MHz USB
2




3.3V 24.576MHz/48Mhz HD Audio
S-ATA
BGA-676
New Card MINI Card x2 LAN(GbE) page 21,22,23,24
Socket WLAN, Robson2 Realtek RTL8111C port 0 port 1
page 30 page 29 page 27 GMCH HDA MDC 1.5 HDA Codec MXM HDA
Conn 33 ALC888S-VC
page 08 page page 34 page 17
SATA HDD CDROM
Conn.
page 25
Conn.
page 25
DOCKING RJ45
page 28
(DVI/LAN/ Audio AMP
CRT/USB/AUDIO) LS-4208P LPC BUS page 35
page 38
3
Media/B Conn. 3
page 32
ENE KB926 Phone Jack x3
RTC CKT. LS-4202P page 35
page 31
page 22 BTN/B Conn.
page 32

LS-4204P
Power On/Off CKT. Touch Pad Int.KBD
PWR/B Conn. page 32 page 32
page 33
page 32

EC I/O Buffer BIOS
DC/DC Interface CKT. LS-4205P page 32 page 32
USB/B Conn.
page 37 USB port 4
page 29
CIR
Power Circuit DC/DC LS-4206P page 33
page 39,40,41,42
4
43,44,45,46
UMA HDMI/B 4




LS-4205P
Security Classification Compal Secret Data Compal Electronics, Inc.
COVER LIGHT Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

Conn THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
page 36 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 2 of 50
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A B C D E



SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5V 1.5V power rail for HDA ON ON OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+2.5VS 2.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0.155 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V
+3V 3.3V power rail for SB ON ON X 2 18K +/- 5% 0.375 V 0.503 V 0.621 V
+3V_LAN 3.3V power rail for LAN ON ON X 3 33K +/- 5% 0.634 V 0.819 V 0.945 V
+3VS 3.3V switched power rail ON OFF OFF 4 56K +/- 5% 0.958 V 1.185 V 1.359 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.372 V 1.650 V 1.838 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.851 V 2.200 V 2.420 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.433 V 3.300 V 3.300 V
2 2
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 JAL90 JAL90@
1 0.2 JAW50/KAW00 JAW50@
2 0.3 UMA GM@
3 1.0 JAL90-UMA JAL90GM@
4 1A JAW50/KAW00
GLPM@
5 Discrete
6 Discrete PM@
7 ALC888VC 888VC@
ALC888VB 888VB@
8111C 8111C@
EC SM Bus1 address EC SM Bus2 address 8102E 8102E@
3
Device Address Device Address
ALC268 268@ 3


Smart Battery 0001 011X b ADI ADT7421 1001 100X b
JAL90/JAW50 ABO@
EEPROM(24C16/02) 1010 000X b
KAW00 EM@
GMT G781-1 1001 101X b
JAL90/JAW50
JAL9050@
KAW00
JAL90-DIS JAL90PM@
JAW50-DIS JAW50PM@
JAW50-UMA JAW50GL@
ICH9M SM Bus address
Device Address BOM Configuration Table
Clock Generator 1101 001Xb Project BOM Configuration
(ICS9LPRS387, SLG8SP556V)
DDR DIMM0 1001 000Xb
JAL90-UMA 431551BOL01:JAL90GM@/JAL9050@/JAL90@/GM@/888VC@/8111C@/ABO@
DDR DIMM2 1001 010Xb
JAL90-Dis 431551BOL02:PM@/JAL90PM@/JAL9050@/JAL90@/GLPM@/888VC@/8111C@/ABO@
JAW50-UMA 431551BOL11:JAW50@/JAW50GL@/JAL9050@/GM@/GLPM@/8111C@/268@/ABO@
JAW50-DIS 431551BOL12:PM@/JAW50@/JAW50PM@/JAL9050@/GLPM@/8111C@/268@/ABO@
4 KAW00 431551BOL31:JAW50@/JAW50GL@/JAL9050@/GM@/GLPM@/8111C@/268@/EM@ 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 3 of 50
A B C D E
5 4 3 2 1




H_A#[3..35]
7 H_A#[3..35]
H_REQ#[0..4]
7 H_REQ#[0..4]
H_RS#[0..2]
7 H_RS#[0..2]
JCPU1A
H_A#3 J4 H1 H_ADS# 7
A[3]# ADS#




ADDR GROUP_0
H_A#4 L5 E2 H_BNR# 7
H_A#5 A[4]# BNR#
D L4 A[5]# BPRI# G5 H_BPRI# 7 D
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# 7
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 7
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 A[12]#




CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# 22
H_A#15 P1
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# 7
7 H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET# H_RESET# 7
H_REQ#0 RESET# H_RS#0
K3 REQ[0]# RS[0]# F3
H_REQ#1 H2 F4 H_RS#1
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3
H_REQ#3 J3 G2 H_TRDY# 7
H_REQ#4 REQ[3]# TRDY#
L1 REQ[4]#
HIT# G6 H_HIT# 7
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 7
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4

ADDR GROUP_1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#
XDP/ITP SIGNALS
H_A#23 U1 AC2
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
C H_A#26 A[25]# TCK XDP_TDI C
T3 A[26]# TDI AA6
H_A#27 W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# 23
H_A#31 V4
H_A#32 A[31]# +1.05VS
W3 A[32]#
H_A#33 AA4 THERMAL
H_A#34 A[33]#
AB2 A[34]#
H_A#35 AA3 D21 H_PROCHOT#
A[35]# PROCHOT# H_THERMDA
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC XDP_TDI R17 1 2 54.9_0402_1%
THERMDC
22 H_A20M# A6 A20M#
ICH
ICH




22 H_FERR# A5 FERR# THERMTRIP# C7 H_THERMTRIP# 8,22 left NC if no ITP
22 H_IGNNE# C4 IGNNE# XDP_TMS R16 1 2 54.9_0402_1% 39Ohm
22 H_STPCLK# D5 STPCLK#
C6 H CLK XDP_BPM#5 R8 1 2 54.9_0402_1%
22 H_INTR LINT0
B4 A22 @
22 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 16
22 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 16
M4 H_PROCHOT# R32 2 1 56_0402_5%
RSVD[01]
N5 RSVD[02]
T2 H_IERR# R31 2 1 56_0402_5%
RSVD[03]
V3 RSVD[04]
RESERVED




B2 RSVD[05] Layout Note:
D2 RSVD[06]
D22 H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
RSVD[07]
D3 RSVD[08]
B XDP_TRST# R13 54.9_0402_1% B
F6 RSVD[09] 2 1

XDP_TCK R7 1 2 54.9_0402_1%


Penryn
CONN@


+3VS
C95
0.1U_0402_16V4Z
1 2

+1.05VS U8
BSEL2 BSEL1 BSEL0 BCLK H_THERMDA

0 0 0 266 1 VDD SMCLK 8 EC_SMB_CK2 31,32
1




1
R39 C94 2 7
DP SMDATA EC_SMB_DA2 31,32
0 1 0 200 56_0402_5%
2200P_0402_50V7K
@ 3 DN ALERT# 6 1 2 +3VS
2 R541
2




0 1 1 166 4 5 10K_0402_5%
H_THERMDC THERM# GND
2
B
E




H_PROCHOT# 3 1 OCP# 23 EMC1402-1-ACZL-TR_MSOP8
A A
C




Q2
MMBT3904_SOT23-3
@

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,LA-4201P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B I
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401551
Date: Monday, July 21, 2008 Sheet 4 of 50
5 4 3 2 1
5 4 3 2 1




H_D#[0..63] JCPU1C
H_D#[0..63] 7
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JCPU1B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12




DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13




DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VCC[006] VCC[073]
F23 D[4]# D[36]# V23 A17 VCC[007] VCC[074] AC15
H_D#5 G25 T22 H_D#37 A18 AC17
H_D#6 D[5]# D[37]# H_D#38 VCC[008] VCC[075]
E25 D[6]# D[38]# U25 A20 VCC[009] VCC[076] AC18
H_D#7 E23 U23 H_D#39 B7 AD7
H_D#8 D[7]# D[39]# H_D#40 VCC[010] VCC[077]
K24 D[8]# D[40]# Y25 B9 VCC[011] VCC[078] AD9
H_D#9 G24 W22 H_D#41 B10 AD10
H_D#10 D[9]# D[41]# H_D#42 VCC[012] VCC[079]
J24 D[10]# D[42]# Y23 B12 VCC[013] VCC[080] AD12
H_D#11 J23 W24 H_D#43 B14 AD14
H_D#12 D[11]# D[43]# H_D#44 VCC[014] VCC[081]
H22 D[12]# D[44]# W25 B15 VCC[015] VCC[082] AD15
H_D#13 F26 AA23 H_D#45 B17 AD17
H_D#14 D[13]# D[45]# H_D#46 VCC[016] VCC[083]
K22 D[14]# D[46]# AA24 B18 VCC[017] VCC[084] AD18
H_D#15 H23 AB25 H_D#47 B20 AE9
D[15]# D[47]# VCC[018] VCC[085]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26