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Block diagram 1 (ver.0.0 ed.4)
2
AFC VBAT VBAT
1 RF
0
TXPWRDET IPA1 IPA1
SYS
schematic TXC IPA2 IPA2
VrefRF01 VR1 VR1A
RFAUXCONV_O(2:0) VrefRF02 VR2 VR2
RFCONV_O(9:0) TXIP VR3 VR3
GENIO_O(31:0) 5
9
GENIO_O(31:0) TXIM VR4 VR4
9 7 6 8
1 VR5
RFAUX_O(1:0) TXQP VR5
3
4
RFICCTRL_O(2:0) TXQM VR6 VR6
5
6
RFCLKGND_I RXQ VR7 VR7
7
2
RFCLK_I RXI
0
SLOWAD(6:0)
SLOWAD_O(6:0) TXP
6
PUSL_O(3:0) Reset
LPRFCLK_I TXA
RFCONV_ANA_O(16:0) Mode
2
RFCONV_DIGI_O(16:0) RFBusEna1
1
0
RFBusData
RFBusClk
VCTCXOGnd
VCTCXO
RFTEMP
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