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A B C D E
SYSTEM DC/DC
Tahoe Block Diagram
MAX8744 38
Project code: 91.4T901.001 INPUTS OUTPUTS
PCB P/N : 48.4T901.0SA
REVISION : 06252-SA 5V_S5(6A)
Mobile CPU DCBATOUT
3D3V_S5(7A)
4 CLK GEN. Merom 479 G792 4
ICS 9LPRS502
(RTM875T-605) 3
2G/2.33G 20
PCB STACKUP SYSTEM DC/DC
2.0G : 71.MEROM.A0U Max8717 39
71.09502.00W 2.33G : 71.MEROM.B0U
4, 5 TV Out
15 TOP INPUTS OUTPUTS
VCC 1D05V_S0(9.5A)
HOST BUS 667/[email protected] CRT DCBATOUT
15 1D8V_S3(8.5A)
DDR2 533/667MHz
S
533/667 MHz Crestline
AGTL+ CPU I/F
LCD
14
S
TPS51100
DDR_VREF_S0
41
12,13 GND 1D8V_S3 (1.5A)
DDR Memory I/F
DDR_VREF_S3
INTEGRATED GRAHPICS BOTTOM
DDR2 533/667MHz LVDS, CRT I/F APL5915 41
533/667 MHz 71.CREST.00U 6,7,8,9,10,11 VGA Borad 1D8V_S3 1D25V_S0
12,13 X4 DMI 27 (2A)
3 C-Link0 3
400MHz APL531230
Line In
3D3V_S0 2D5V_S0
Codec AZALIA
(300mA)
ALC268 ICH8M APW5912 40
29 6 PCIe ports OZ129 Cardreader 3D3V_S5 1D5V_S3
MIC In PCI/PCI BRIDGE 1394 (7.5A)
PCI BUS 1394
30 ACPI 1.1 CardReader CONN 26 MS/MS Pro/xD/ CHARGER
MAX8731 41
3 SATA 25 MMC/SD
1 PATA 66/100 5 in 1 INPUTS OUTPUTS
26
10 USB 2.0/1.1 ports
30 OP AMP CHG_PWR
ETHERNET (10/100/1000MbE)
G1431Q 30 18V 4.0A
High Definition Audio DCBATOUT
Giga LAN 23 TXFM RJ45 UP+5V
INT.SPKR LPC I/F BCM5787MKMLG 24 24 5V 100mA
2 Serial Peripheral I/F 2
OP AMP Matrix Storage Technology(DO) CPU DC/DC
G1412 PCIex1 Mini Card MAX8770
Active Managemnet Technology(DO) 35,36
30 Kedron a/b/g/n 28
Line Out INPUTS OUTPUTS
(SPDIF)
MODEM DCBATOUT
VCC_CORE_S0
71.0ICH8.A0U
LPC BUS 0~1.3V
RJ11 MDC Card 16,17,18,19 47A
22
SATA
PATA
USB
MINI USB KBC SPI I/F BIOS LPC
PCI Express Winbond W25X80-VSS
New card BlueTooth DEBUG
28 22 WPC8768L 33 CONN. 33
31
1 Touch INT.
1
P2231NFC1 CDROM MEDIA BD CIR 31
28 HDD 21 21 32 Pad 32 KB 32 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
USB Title
4 Port 22 CAMERA BLOCK DIAGRAM
Size Document Number Rev
14 A3
Tahoe -1
Date: Friday, April 27, 2007 Sheet 1 of 44
A B C D E
ICH8M Functional Strap Definitions
ICH8-M EDS 21762 2.0V1 page 16
ICH8M Integrated Pull-up Crestline Strapping Signals and
Signal Usage/When Sampled Comment and Pull-down Resistors Configuration Crestline EDS 20954
page 7
1.0
ICH8-M EDS 21762 2.0V1
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: SIGNAL Resistor Type/Value CFG[2:0] FSB Frequency Select 001 = FSB533
offset 224h) HDA_BIT_CLK PULL-DOWN 20K 011 = FSB667
010 = FSB800
HDA_RST# NONE others = Reserved
4 HDA_SYNC PCIE config1 bit0, This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h) CFG[4:3] Reserved
4
Rising Edge of PWROK. HDA_SDIN[3:0] PULL-DOWN 20K
GNT2# PCIE config2 bit0, This signal has a weak internal pull-up. HDA_SDOUT PULL-DOWN 20K CFG5 DMI x2 Select 0 = DMI x2
Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) 1 = DMI x4 (Default)
HDA_SYNC PULL-DOWN 20K CFG[8:6] Reserved
GPIO20 Reserved This signal should not be pulled high.
GNT[3:0] PULL-UP 20K 0 = Normal mode
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. Low Power PCI Express 1 = Low Power mode (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop GPIO[20] PULL-DOWN 20K
and mobile. 0 = Reverse Lanes,15->0,14->1 ect..
LDA[3:0]#/FHW[3:0]# PULL-UP 20K CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
Lane Reversal Numbered in order
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for LAN_RXD[2:0] PULL-UP 10K
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the LDRQ[0] PULL-UP 20K CFG[11:10] Reserved
Top-Swap bit until the system is rebooted XOR/ALL Z test 00 = Reserved
without GNT3# being pulled down. LDRQ[1]/GPIO23 PULL-UP 20K
CFG[13:12] straps 01 = XOR mode enabled
PME# PULL-UP 20K 10 = All Z mode enabled
GNT0#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit 11 = Normal Operation (Default)
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). PWRBTN# PULL-UP 20K
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. CFG[15:14] Reserved Reserved
SATALED# PULL-UP 15K
Integrated VccSus1_05, Enables integrated VccSus1_05, VccSus1_5 and CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
INTVRMEN VccSus1_5 and VccCL1_5 VccCL1_5 VRM's when sampled high SPI_CS1# PULL-UP 20K 1 = Dynamic ODT Enabled (Default)
VRM Enable/Disable.
Always sampled. SPI_CLK PULL-UP 20K
CFG[18:17] Reserved
3 Integrated VccLAN1_05 Enables integrated VccLAN1_05 and VccCL1_05 VRM's
SPI_MOSI PULL-UP 20K
0 = Normal operation (Default):lane 3
LAN100_SLP and VccCL1_05 VRM when sampled high SPI_MISO PULL-UP 20K CFG19 DMI Lane Reversal Numbered in order
Enable/Disable.
Always sampled. TACH_[3:0] PULL-UP 20K 1 =Reverse Lane,4->0,3->1 ect...
SPKR PULL-DOWN 20K 0 = Only SDVO or PCIE x1 is
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 CFG20 SDVO/PCIE operational (Default)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) TP[3] PULL-UP 20K Concurrent 1 =SDVO and PCIE x1 are operating
of PWROK. simultaneously via the PEG port
USB[9:0][P,N] PULL-DOWN 15K
SPKR No Reboot. If sampled high, the system is strapped to the SDVOCRTL SDVO Present 0 = No SDVO Card present (Default)
Rising Edge of PWROK. "No Reboot" mode(ICH8 will disable the TCO Timer CL_RST# PULL-UP 13K _DATA
system reboot feature). The status is readable 1= SDVO Card present
via the NO REBOOT bit.
NOTE: All strap signals are sampled with respect to the leading
TP3 XOR Chain Entrance. This signal should not be pull low unless using edge of the Crestline GMCH PWORK in signal.
Rising Edge of PWROK. XOR Chain testing.
GPIO33/ Flash Descriptor This signal has a weak internal pull-up.
History
HDA_DOCK Security Override Strap Sampled low:the Flash Descriptor Security will be
_EN# Rising Edge of PWROK overridden. If high,the security measures will be
in effect.This should only be used in manufacturing
environments.
2 2
ICH8M IDE Integrated Series
Termination Resistors
DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
DDACK#, IORDY, DA[2:0], DCS1#,
DCS3#, IDEIRQ
page 17
USB Table
PCI Routing USB
IDSEL INT REQ GNT Pair Device
G:CARDBUS 0 0 0 USB1
TI7412 AD22 B:1394
F:Flash Media 1 USB4
G:SD Host 2 USB2
3 FT
1 UMA
1
4 USB3
PCIE Routing 5 BLUETOOTH Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
LANE1 LAN BCM5787M 6 NC Taipei Hsien 221, Taiwan, R.O.C.
LANE2 MiniCard WLAN 7 MINICARD Title
LANE3 NewCard WLAN 8 WEBCAM Reference
Size Document Number Rev
9 NEW1 A3
Tahoe -1
Date: Friday, April 27, 2007 Sheet 2 of 44
A B C D E
3D3V_S0
-1 3D3V_S0 -1 R119
3D3V_S0 -1 R89 0R0603-PAD
0R0603-PAD 0R0603-PAD 3D3V_CLKGEN_S0 1 2
1 2 3D3V_48MPWR_S0 3D3V_CLKPLL_S0 1 2
1
1
1
1
1
R337 C217 C483 C462 C488 C479
SC4D7U6D3V3KX-GP
1
1
1
1
1
1
1
1
C487 C484 C480 C162 C456 C473 C472 SCD1U16V2ZY-2GP
DY C464 SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
2
2
2
SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
SC1U16V3ZY-GP
4 4
3D3V_S0
U11
3D3V_CLKGEN_S0 2 63
VDDPCI SDATA SMBD_ICH 12,19
2
2
2
2
3D3V_48MPWR_S0 9 64
DY DY DY 16
VDD48 SCLK SMBC_ICH 12,19
R334 R330 R326 R322 VDDPLL3
61 VDDREF
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 13 DREFCLK_1 4 1 RN47 DREFCLK 7
SRCT0/DOTT_96 DREFCLK#_1
39 14 3 UMA 2 SRN33J-5-GP-U DREFCLK# 7
1
1
1
1
VDDSRC SRCC0/DOTC_96
55 VDDCPU
PCLKCLK2 17 CLK_PCIE_NEW_R 2 3 CLK_PCIE_NEW 28
27MHZ_NONSS/SRCT1/SE1
PCLKCLK3 3D3V_CLKPLL_S0 12 VDD96_IO 27MHZ_SS/SRCC1/SE2 18 CLK_PCIE_NEW#_R 1 4 SRN0J-6-GP CLK_PCIE_NEW# 28
PCLKCLK4 20 RN46
PCLKCLK5 VDDPLL3_IO CLK_PCIE_SATA_1
26 VDDSRC_IO SRCT2/SATAT 21 2 3 CLK_PCIE_SATA 16
36 22 CLK_PCIE_SATA_1# 1 4 SRN0J-6-GP
VDDSRC_IO SRCC2/SATAC RN45 CLK_PCIE_SATA# 16
45 VDDSRC_IO
2
2
2
2
49 24 CLK_MCH_3GPLL_1 2 3
DY TPAD30 TP27 PCLKCLK0 1
VDDCPU_IO SRCT3/CR#_C
25 CLK_MCH_3GPLL_1# 1 4 SRN0J-6-GP CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
R332 R327 R323 R324 PCI0/CR#_A SRCC3/CR#_D RN44
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP TPAD30 TP26 PCLKCLK1 3 27 CLK_PCIE_MINI_12 2 3 CLK_PCIE_MINI1 28
PCI1/CR#_B SRCT4 CLK_PCIE_MINI_12# SRN0J-6-GP
28 1 4 CLK_PCIE_MINI1# 28
1
1
1
1
R338 2 SRCC4 RN43
25 PCLK_PCM 1 22R2J-2-GP PCLKCLK2 4 PCI2/TME
PCI_STOP# 38 PM_STPPCI# 17
PCLKCLK3
-1 5 PCI3 CPU_STOP# 37 PM_STPCPU# 17
31 PCLK_KBC R329 2 1 22R2J-2-GP PCLKCLK4 6 41 CLK_PCIE_ICH_1 1 4 RN14 CLK_PCIE_ICH 17
PCI4/27_SELECT SRCT6 CLK_PCIE_ICH_1# SRN0J-6-GP
CL=20pF