Text preview for : compal_la-6221p_r1_schematics.pdf part of acer compal la-6221p r1 schematics acer Netbook Нетбук Acer Aspire One AOD260 compal_la-6221p_r1_schematics.pdf



Back to : compal_la-6221p_r1_schema | Home

A B C D E




1 1




Compal Confidential
2 2




PAV70 Schematics Document
Intel Pineview Processor with Tigerpoint + DDRII



3
2010-07-01 3




REV: 1.0




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6221P
Date: Friday, July 02, 2010 Sheet 1 of 39
A B C D E
A B C D E




Clock Generator
Compal Confidential CK505 page 8

Model Name :
File Name : LA-6221P CRT Conn
page 10
1 1
ZZZ
RGB
Memory BUS(DDRII) DDRII-SO-DIMM
Pineview page 7
PCB PAV70@

DAZ0F300201 LCD Conn. LVDS FCBGA 559 1.8V DDRII 667

page 9 22x22mm
Thermal Sensor page 4,5,6
ZZZ
EMC1402
page 5
DMI
PCB PAV50@
X2 mode
GEN1
DAZ0F000300




USB USB Port X3
2
PCI-Express Tigerpoint HDA page 15
2




PCBGA360 BlueTooth
page 23
17x17mm SATA
page 11,12,13,14
CMOS CAM
page 9
MINI Card x1 MINI Card x1
3G WLAN 10/100 Ethernet HDD
AR8152L page 15 3G
page 17 page 18 page 16
page 17

LPC BUS
Transfermer WLAN
3 3
page 18

Aralia Codec
ALC272 page 19
Card Reader
RJ45
Power ON/OFF DC/DC Interface
page 27
ENE6252
page 26
3VALW/5VALW
page 27
ENE KBC SPI page 22

DC IN
page 27
KB926
page 24
0.89VP/1.5VP
AMP & INT INT MIC HeadPhone & SD/MMC/MS
BATT IN 0.9VSP/2.5VSP MIC Jack
page 29 page 32 33 Speaker CONN
Int.KBD SPI ROM
page 25 page 25
CHARGER 1.8V/VCCP Touch Pad I/O Board
page 30
4
page 32 page 25 4




CPU_CORE
page 34
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6221P
Date: Thursday, July 01, 2010 Sheet 2 of 39
A B C D E
A B C D E




Voltage Rails
Power Plane Description S1 S3 S5 External PCI Devices
1
VIN Adapter power supply (19V) ON ON ON DEVICE IDSEL # REQ/GNT # PIRQ 1

B+ AC or battery power rail for power circuit. ON ON ON
+CPU_CORE Core voltage for CPU ON OFF OFF No PCI Device
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+0.89V Graphic core power rail ON OFF OFF
EC SM Bus1 address EC SM Bus2 address
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF Device Address Device Address
+5VALW 5V always on power rail ON ON ON* Smart Battery 0001 011X b EMC1402 100_1100
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON


Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Tiger Point SM Bus address
2 2

SIGNAL Device Address
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Clock Generator 1101 001Xb
Full ON HIGH HIGH HIGH ON ON ON ON (SLG8SP556VTR)
DDR DIMMA 1010 000Xb
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF

USB table PCIE table
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
Port0 MB USB Conn1.
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF UHCI1 PCIE port1 LAN
Port1 MB USB Conn2.
Port2 MB USB Conn3. PCIE port2 Wireless Card
EHCI1 UHCI2
Port3 CMOS
PCIE port3 3G
BOARD ID Table(Page 17) Port4 Card Reader
UHCI3
Port5 WWAN PCIE port4
Vcc 3.3V +/- 5% Port6 BT
UHCI4 PCIE port5
Ra/Rc/Re 100K +/- 5% Port7 WLAN
3 Board ID 3
Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max EHCI2 Port8 PCIE port6
UHCI5
0(EVT) 0 0 V 0 V 0 V Port9
1(DVT) 8.2K +/- 5% 0.216 V 0.250 V 0.289 V Port10
UHCI6
2(PVT) 18K +/- 5% 0.436 V 0.503 V 0.538 V Port11
3(MP) 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V SATA table
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
SATA port0 HDD
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V SATA port1
SATA port2
BOARD ID Table
SATA port3
Board ID PCB Revision
SATA port4
0 0.1
1 0.2 SATA port5
2
4 4
3
4
5
6
7
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6221P
Date: Thursday, July 01, 2010 Sheet 3 of 39
A B C D E
5 4 3 2 1


(7) DDR_A_DQS#[0..7]
PINEVIEW_M
PINEVIEW_M (7) DDR_A_D[0..63]
U71A U71B
REV = 1.1
(7) DDR_A_DM[0..7]
REV = 1.1 DDR_A_MA0 AH19 AD3 DDR_A_DQS0
DMI_RX0_C (7) DDR_A_DQS[0..7] DDR_A_MA1 DDR_A_MA_0 DDR_A_DQS_0 DDR_A_DQS#0
F3 DMI_RXP_0 DMI_TXP_0 G2 DMI_TX0 (12) AJ18 DDR_A_MA_1 DDR_A_DQS#_0 AD2
DMI_RX#0_C F2 G1 DDR_A_MA2 AK18 AD4 DDR_A_DM0
DMI_RXN_0 DMI_TXN_0 DMI_TX#0 (12) (7) DDR_A_MA[0..14] DDR_A_MA_2 DDR_A_DM_0
DMI_RX1_C H4 H3 DMI_TX1 (12) DDR_A_MA3 AK16
DMI_RX#1_C DMI_RXP_1 DMI_TXP_1 DDR_A_MA4 DDR_A_MA_3 DDR_A_D0
G3 DMI_RXN_1 DMI_TXN_1 J2 DMI_TX#1 (12) AJ14 DDR_A_MA_4 DDR_A_DQ_0 AC4
DDR_A_MA5 AH14 AC1 DDR_A_D1




DMI
DDR_A_MA6 DDR_A_MA_5 DDR_A_DQ_1 DDR_A_D2
AK14 DDR_A_MA_6 DDR_A_DQ_2 AF4
DDR_A_MA7 AJ12 AG2 DDR_A_D3
DDR_A_MA8 DDR_A_MA_7 DDR_A_DQ_3 DDR_A_D4
AH13 DDR_A_MA_8 DDR_A_DQ_4 AB2
D DDR_A_MA9 DDR_A_D5 D
AK12 DDR_A_MA_9 DDR_A_DQ_5 AB3
N7 L10 DDR_A_MA10 AK20 AE2 DDR_A_D6
(8) CLK_CPU_EXP# EXP_CLKINN EXP_RCOMPO DDR_A_MA_10 DDR_A_DQ_6
N6 L9 R162 DDR_A_MA11 AH12 AE3 DDR_A_D7
(8) CLK_CPU_EXP EXP_CLKINP EXP_ICOMPI DDR_A_MA_11 DDR_A_DQ_7
L8 R203 49.9_0402_1% DDR_A_MA12 AJ11
EXP_RBIAS 750_0402_1% DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
R10 AJ24 AB8
EXP_TCLKINN DDR_A_MA14 DDR_A_MA_13 DDR_A_DQS_1 DDR_A_DQS#1
R9 EXP_TCLKINP RSVD_TP N11 T38 AJ10 DDR_A_MA_14 DDR_A_DQS#_1 AD7
N10 P11 AA9 DDR_A_DM1
RSVD RSVD_TP T39 Must be placed within 500 mils from Pineview-M pins DDR_A_DM_1
N9 RSVD DDR_A_WE# AK22 AB6 DDR_A_D8
(7) DDR_A_WE# DDR_A_WE# DDR_A_DQ_8
DDR_A_CAS# AJ22 AB7 DDR_A_D9
(7) DDR_A_CAS# DDR_A_RAS# DDR_A_CAS# DDR_A_DQ_9 DDR_A_D10
(7) DDR_A_RAS# AK21 DDR_A_RAS# DDR_A_DQ_10 AE5
K2 K3 AG5 DDR_A_D11
RSVD RSVD DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
J1 RSVD RSVD L2 (7) DDR_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
M4 M2 DDR_A_BS1 AH20 AB5 DDR_A_D13
RSVD RSVD (7) DDR_A_BS1 DDR_A_BS2 DDR_A_BS_1 DDR_A_DQ_13 DDR_A_D14
L3 N2 (7) DDR_A_BS2 AK11 AB9
RSVD RSVD DDR_A_BS_2 DDR_A_DQ_14 DDR_A_D15
AD6
DDR_A_DQ_15
1 OF 6 DDR_A_DQS2
PINEVIEW-M_FCBGA8559 AD8
DDR_CS#0 DDR_A_DQS_2 DDR_A_DQS#2
(7) DDR_CS#0 AH22 DDR_A_CS#_0 DDR_A_DQS#_2 AD10
DDR_CS#1 AK25 AE8 DDR_A_DM2
(7) DDR_CS#1 DDR_A_CS#_1 DDR_A_DM_2
JP16 AJ21
XDP_PREQ# CONN@ DDR_A_CS#_2 DDR_A_D16
(5) XDP_PREQ# 1 AJ25 AG8
XDP_PRDY# 1 DDR_A_CS#_3 DDR_A_DQ_16 DDR_A_D17
(5) XDP_PRDY# 2 2 DDR_A_DQ_17 AG7
3 DDR_CKE0 AH10 AF10 DDR_A_D18
XDP_BPM#3 3 (7) DDR_CKE0 DDR_CKE1 DDR_A_CKE_0 DDR_A_DQ_18 DDR_A_D19
(5) XDP_BPM#3 4 (7) DDR_CKE1 AH9 AG11
XDP_BPM#2 4 DDR_A_CKE_1 DDR_A_DQ_19 DDR_A_D20
(5) XDP_BPM#2 5 5 AK10 DDR_A_CKE_2 DDR_A_DQ_20 AF7
6 AJ8 AF8 DDR_A_D21
C435 XDP_BPM#1 6 DDR_A_CKE_3 DDR_A_DQ_21 DDR_A_D22
1 2 DMI_RX0_C (5) XDP_BPM#1 7 AD11
(12) DMI_RX0 7 DDR_A_DQ_22
(5) XDP_BPM#0 XDP_BPM#0 8 M_ODT0 AK24 AE10 DDR_A_D23
0.1U_0402_10V7K 8 (7) M_ODT0 DDR_A_ODT_0 DDR_A_DQ_23
9 M_ODT1 AH26
C436 9 (7) M_ODT1 DDR_A_ODT_1 DDR_A_DQS3
1 2 DMI_RX#0_C (5,13) H_PWRGD R354 1 2 1K_0402_5% 10 AH24 AK5
(12) DMI_RX#0 10 DDR_A_ODT_2 DDR_A_DQS_3 DDR_A_DQS#3
0.1U_0402_10V7K R347 1 2 1K_0402_5% 11 AK27 AK3
C (13) SLPIOVR# 11 DDR_A_ODT_3 DDR_A_DQS#_3 DDR_A_DM3 C
(8) CPU_ITP 12 12 DDR_A_DM_3 AJ3
C437 DMI_RX1_C 13
(12) DMI_RX1 1 2 (8) CPU_ITP# 13
14