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A B C D E F G H I J K L M N
RX-A3010/RX-V3071
SCHEMATIC DIAGRAMS
DIGITAL1 1/9
1 HDMI
Page 128 J7
AV 7 AV 6 AV 5 AV 4 AV 3 AV 2 AV 1
(1 BD/DVD) to DIGITAL1 (2)_CB32

CB7 CB5 CB4 CB3 CB2 CB1
CB6

CB10




2




3




4
HDMI SWITCHER HDMI SWITCHER
IC2 IC1




5




6



to DIGITAL1 5/9
IC4
to DIGITAL1 3/9


IC4




to DIGITAL1 4/9
HDMI RECEIVER
7

to DIGITAL1 6/9




DIGITAL1 (1)
IC3

8 No replacement part available.




IC3: SiI9233ACTU
HDMI receiver




IC6
IC5
IC7

CEC_A CEC CEC_D

DSDA0
DSDA1
Serial HDPC
DSDA2 HDCP Embedded
Host Engine
DSDA3 Registers HDCP Keys
9 DSCL0
DSCL1
DSCL2
Interface
(DDC)

EDID HPD0
DSCL3 SRAM Hot Plug HPD1
NVRAM HPD2
Controller
Serial HPD3
CSDA
Host
CSCL
Interface RPI Configuration
CI2CA (Local) Registers
and State
and Status
INT
to DIGITAL1 2/9, 3/9, 4/9
Machine
Registers
IC1, 2: SiI9185ACTU
Port0_DDC
Port1_DDC
Port2_DDC




R0XC+
HDMI switcher
EPSEL1/

EPSEL0/




TX_DDC




R0XC-
R0X0+
R0X0- Video Processing IC4: TC7SH125FU IC5: RP130Q121D-TR-F IC6: RP130Q501D-TR-F IC7: R1172H121D-T1-F
LSDA
LSCL




R0X1+
R0X1-
R0X2+ Video
Color
Bus buffer Voltage regulator Voltage regulator CMOS-based positive-voltage regulator IC
R0X2- HDCP Deep ODCK
Space
Unmask Color Video Q[35:0]
R0XC+ Converter
Output DE
EDID Block
R0XC-
Termination/




HSYNC
R0X0+ Format R0X0+/- Config. EDID G 1 5 VCC
Equalizer




R0X0- Up/Down VSYNC I2C Switch VDD 3 VOUT
R0X1+
R0X1- Sampling EVNODD R0X1+/- Logic RAM VDD 4 3 VOUT 4 VDD 4 5 VOUT
R0X2+ R0X2+/-
R0X2-
HDMI Auto Video Configuration R0XC+/- Configuration Block
IN A 2
Receiver A/V Split HDMI Transmitter
R0XC+ Mux Decode Block
R0XC- Audio Processing GND 3 4 OUT Y
Termination/




Oversample




R0X0+
Equalizer




R0X0- Audio Output R1X0+/-
R0X1+ SPDIF TX0+/-
DPLL




Components having special characteristics are marked
Audio Clock R1X1+/- Vref
R0X1-
R0X2+ Regeneration S/PDIF
R1X2+/- TX1+/- and must be replaced
10 R0X2-

R0XC+
Audio APLL
Output
I2S/
SCK/DCLK
WS R1XC+/- Transmit
Drivers
TX2+/- Vref Vref
CE 1
Current Limit
2 GND with parts having specifications equal to those originally installed.
Schematic diagram is subject to change without notice.
SCDT HDCP SD[3:0]
R0XC- Unmask
DSD
DR[3:0] Current Limit Current Limit
R0X0+ Logic Output
CE 1 2 GND
Termination/




R0X0- DR[3:0] R2X0+/- CE 1 2 GND
Equalizer




R0X1+ Auto PLL TXC+/-
R0X1- Audio/ MUTEOUT R2X1+/-
R0X2+
R0X2- Exception XTALIN R2X2+/- Pin No. Symbol Description
XTALOUT
MCLK R2XC+/- 5V Switch HPD 1 CE Chip Enable Pin
CEC




Switch CEC I/F
R0PWR5V SCDT Pin No. Symbol Description Pin No. Symbol Description 2 GND Ground Pin
R1PWR5V Receiver Block CE Chip Enable ("H" Active)
R2PWR5V 1 1 CE Chip Enable ("H" Active) 3 NC No Connection
R3PWR5V
RPWR0
RPWR1
RPWR2




HPDIN
I2CADDR/
TPWR
HPD0
HPD1
HPD2




CEC_A

CEC_D




2 GND Ground Pin 2 GND Ground Pin
4 VDD Input Pin
Reset 3 VOUT Output Pin 3 VOUT Output Pin
RESET# Logic 5 VOUT Output Pin of Voltage Regulator
4 VDD Input Pin 4 VDD Input Pin
127
A B C D E F G H I J K L M N
RX-A3010/RX-V3071
IC31: TMDS141RHAR
HDMI switch
DIGITAL1 2/9
1 Page 144 M6 VSADJ 30
OE 6
to VIDEO (1)_CB303 VIDEO AUX PRE 7
VCC
HDMI IN
RINT
Page 144 M5 RX2 2
TMDS TMDS
9 TX2
CB23




CB31 Receiver Driver
to VIDEO (1)_CB302 Rx2 1
w/EQ
10 Tx2




CB21
VCC

RINT
RX1 39 12 TX1
CB22 TMDS TMDS
Receiver Driver
w/EQ
RX1 38 13 TX1
VCC


DIGITAL1 (1) DIGITAL1 (2) RX0 36
RINT
15 TX0
TMDS TMDS
Receiver Driver
w/EQ
RX0 35 16 TX0
VCC

RINT

2 RXC 33
TMDS
Receiver
TMDS
Driver
18 TXC

w/EQ
RXC 32 19 TXC



RSCL 29 22 TSCL




RSDA 28 23 TSDA




IC26
IC27 I2CEN 5
OVS 25




3 IC32: TRS3221ECPWR
3 V to 5.5 V single channel RS-232 line driver/receiver
with