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4.1.2 J6: LVDS Connector
Pin # Signal Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TXO3M TXO3P TXOCKM TXOCKP TXO1M TXO2P TXO1M TXO1P TXO0M TXO0P GND GND GND GND GND GND TXE3P TXE3M TXECKP TXECKM TXE2P TXE2M TXE1P TXE1M TXE0P TXE0M LCD VCC LCD VCC LCD VCC LCD VCC Function Negative LVDS differential data input. Channel O3 (odd) Positive LVDS differential data input. Channel O3 (odd) Negative LVDS differential clock input. (odd) Positive LVDS differential clock input. (odd) Negative LVDS differential data input. Channel O1 (odd) Positive LVDS differential data input. Channel O1 (odd) Negative LVDS differential data input. Channel O1 (odd) Positive LVDS differential data input. Channel O1 (odd) Negative LVDS differential data input. Channel O0 (odd) Positive LVDS differential data input. Channel O0 (odd) Ground Ground Ground Ground Ground Ground Positive LVDS differential data input. Channel E3 (even) Negative LVDS differential data input. Channel E3 (even) Positive LVDS differential data input. (even) Negative LVDS differential data input. (even) Positive LVDS differential data input. Channel E2(even) Negative LVDS differential data input. Channel E2(even) Positive LVDS differential data input. Channel E1(even) Negative LVDS differential data input. Channel E1(even) Positive LVDS differential data input. Channel E0(even) Negative LVDS differential data input. Channel E0(even) +5.0V power supply +5.0V power supply +5.0V power supply +5.0V power supply Ground Ground Page 24 CONFIDENTIAL DO NOT COPY VE170m/VE170mb/VA700
31 GND 32 GND ViewSonic Corporation
4.1.3 J1: Inverter Connector
Pin # Signal Name 1 2 3 4 5 6 7 VIN VIN GND +19V +19V Ground Function
GND Ground On/Off control On/Off Control GND Brightness Ground Brightness control Vadj = 5V~0V
4.1.4 J2 Power
Pin # Signal Name 1 2 +12V GND +12V Power Input Ground Function
4.1.5 W1: D-SUB
Pin # Signal Name 1 RIN 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GIN BIN GND GND RRET GRET BRET DCCVCCC GND GND V SDA HSYIN VSYIN V SCL Function Red Video Green Video Blue Video Ground Ground Red Video Ground Green Video Ground Blue Video Ground DDCVCC Ground Ground V SDA H-Sync V-Sync Clock Line (SCL)
ViewSonic Corporation
Page 25 CONFIDENTIAL DO NOT COPY
VE170m/VE170mb/VA700
4.1.6 J9 Switch Board Connector
Pin # Signal Name 1 2 3 4 5 6 7 8 9 10 11 12 GND +5V ON/OFF SUB ADD DOWN NC SELECT OSD LED GRN LED ORG LED MUTE GROUND +5V POWRE SUPPLY ON/OFF SUBTRACTION Key ADDITION Key DOWN Key NO CONNECT SELECT KEY OSD KEY LED GREEN LED ORANGE (AMBER) LED MUTE Function
4.1.7 J11: Audio Board Connector
Pin # Signal Name 1 2 3 +5V GND VOLUME +5V POWRE SUPPLY GROUND VOLUME CONTROL Function
ViewSonic Corporation
Page 26 CONFIDENTIAL DO NOT COPY
VE170m/VE170mb/VA700
SECTION 6 THEORY OF OPERATION
6.1 System Block Diagram
LCD Panel CMO:M170E1
DS90C383
DS90C383
MOSFET 9443
ROM 29LV400
DC/DC LM2596-5 7585-3.3 7585-2.5
SD1210 SCALER IC
ICS512 ICS501 PLL
D
AUDIO BOARD
EEPROM 24LC16 POWER BOARD 19V 3.2V ADC9883 74LVC126
A
SWITCH BOARD VGA CONNECTOR
C
ViewSonic Corporation
Page 35 CONFIDENTIAL DO NOT COPY
VE170m/VE170mb/VA700
6.2 System Circuitry Description BLOCK A.
In reference of the block diagram of the monitor's circuitry shown on the previous page, the analog RGB inputs are amplified and sent through an analog-to-digital converter (ADC) to a digital signal processor (DSP) that generates digital RGB signals for controlling LCA panel.
BLOCK B.
A second power supply converts a single 19V supply to the various voltages needed to run the LCD panel and the inverter driving the display's backlights.
BLOCK C.
SYNC SIGNAL PROCESSOR. This processor determines the polarity of the horizontal and vertical sync signals, generates a fixed-polarity synchronized clock signal and provides data for use by the microprocessor in selecting circuit control parameters from EEPROM tables.
BLOCK D.
PLL CONTROLLER. The ADC digitizes the analog input in step with a trigger signal. The trigger signal must be synchronized to the personal computer's horizontal dot clock or screen noise will appear. While a phase- locked loop (PLL) reliably determines the correct frequency, manual adjustment available via the on-screen display enables the user to compensate for the phase differences occasionally seen among computer video adapters.
ViewSonic Corporation
Page 36 CONFIDENTIAL DO NOT COPY
VE170m/VE170mb/VA700
SECTION 9 CIRCUIT DIAGRAM S
9.1 Power Regulator
12V L1 453215-900A
J1
1 2 3 4 5 6 7 INVETER L41 453215-900A C3 0.1u 5V C4 0.1u R2 4 L2 2012-260 1 5V
C157 0.1u
C1 470uF/16V
C2 0.1u
U19A 8 LM358 3 2
+ -
PWM
J2
12V +12V POWER L40 R6H6x10x085 1 C5 C155 33p C156 330p C154 0.1u C153 470uF/16V 100p 0.1u C6 SHDN GND 5 SW 2 33UH D1 1N5822 C9 330uF/16V C10 100p 0.1u 330uF/16V 2 C7 C8 Q1 MMBT3904L
U1
VIN
LM2596-5.0
FB 4 L4 5V L5 453215-900A 3
1K
R3 1
1K BL_ON_OFF
J3
1 2 3 12V L22 121L1-2601 5V 1 2 3 USB_POWER C176 C177
5V
J12 J11
1 2 3 AUDIO POWER C158 1u 0.1u 330p 1 L3 15K
3 U20A 8 LM358 3 2
Pannel select
U2
VOLUME 12V 5V JP2 JP1 LCD+12V LCD+5V 3 2 S S S G
J4
LCD_VCC
SI9433DY
D D D D 8 7 6 5 C11 330uF/16V
+ 4
1 R4 24K C12 0.1u
1 2 3 4 5 6 7 8 LCDPOWER
4
3V3A
5V 3
U3
INPUT
AIC1084
3V3A OUTPUT 2 C13 330uF/16V 1 C14 0.1u 3 2 1
U4
S S S
SI9433DY
D D D D G 8 L6 7 6 C15 5 0.1u 0.1u C16 R7 330 C17 330uF/16V Q2 MMBT3904L 2 3 1 3 453215-900A R5 470 R6 2K 3V3B
GND
R8 24K
C18 0.1u
R9 2K 1 PSC1 R10 2K
PSC0A R11 470
Q3 MMBT3904L 2
R12 2K R1 1 1K 2 R13 2K PSC0 1 R14 2K 2 3 3
4 Q4 MMBT3904L
LCD_VCC 9 8 7 9 8 7 9 8 7 9 8 7 6 5 4 1 2 3 Z4 MHOLE 1 2 3 6 5 4
Q5 MMBT3904L Z1 MHOLE
6 5 4 1 2 3
Z2 MHOLE 1 2 3
6 5 4
Z3 MHOLE
C187 0.1u
C186 C185 C184 0.1u 0.1u 0.1u
C183 C182 0.1u 0.1u
C181 C180 C179 0.1u 0.1u 0.1u
C178 0.1u
Size
Document Number
ViewSonic17"
Sheet 1 of 8
POWER REGULATER
Date: Tuesday, October 16, 2001
Rev A
Page 44
9.2 ADC
VSYNC_IN R15 22 HSYNC_IN C19 33p 5V C20 3.9n C22 39n 5V 2 1 VD_33 D4 BAV99 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ASIC_V C23 0.1u 2 1 2 1 2 D20 BAV99 3 D2 BAV99 D3 BAV99 3 3 1 VDD_33 P3_3V R16 3.3K
W1
15 14 13 12 15 14 13 12 11 DB-15 C30 5p L10 160808-300T C33 5p R22 75 NC R20 75 R21 75 C32 10 5 9 4 8 3 7 2 6 1 10 5 9 4 8 3 7 2 6 1
V_SCL V_VSYNC V_HSYNC V_SDA 3
GND VD CLAMP MIDSCV GND PVD PVD FILT GND VSYNC HSYNC COAST GND VD VD GND GND VDD VDD GND
U5
CA13 22p CA2 CA1 22p GND B0 B1 B2 B3 B4 B5 B6 B7 VDD GND G0 G1 G2 G3 G4 G5 G6 G7 GND 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RP1 33*4 5 4 6 3 7 2 8 1 5 4 6 3 7 2 8 1 RP2 33*4 RP3 33*4 5 4 6 3 7 2 8 1 5 4 6 3 7 2 8 1 RP4 33*4 CA11 22p CA3 22p CA12 22p CA14 22p CA15 22p CA16 22p CA4 22p CA5 22p CA6 CA7 CA8 CA9 22p 22p 22p 22p R_IN00 R_IN01 R_IN02 R_IN03 R_IN04 R_IN05 R_IN06 R_IN07 R_IN0[0..7] CA10 22p 22p B_IN00 B_IN01 B_IN02 B_IN03 B_IN04 B_IN05 B_IN06 B_IN07 G_IN00 G_IN00 G_IN01 G_IN02 G_IN02 G_IN03 G_IN03 G_IN04 G_IN04 G_IN05 G_IN05 G_IN06 G_IN06 G_IN07 B_IN0[0..7]
DDCVCC L8 C26 5p L9 160808-300T R18 75 R19 75 C29 NC C31 47n C28 1u NC C27 47n 160808-300T R17 75 C24 47n C25 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
3
11
D21 BAV99 2 5V 1
C34 MCU_SCL MCU_SDA 0.1u
3V3A
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
GND VD GND VSOUT SOGOUT HSOUT DATACLK GND VDD R7 R6 R5 R4 R3 R2 R1 R0 VDD VDD GND
GND VD BAIN GND VD VD GND GAIN SOGIN GND VD VD GND RAIN A0 SCL SDA REF BYPASS VD GND
G_IN0[0..7]
AD9883
U6
R23 33 V_HSYNC D6 5.6V R86 3.3K C36 3 33p 4 5 HSYNC_IN 6 PLL_A PLL_B R25 0 7 R26 0 1 2 A1 B1 A2 B2 A3 B3 GND VCC A6 B6 A5 B5 A4 B4 14 13 12 11 10 9 8
C35 0.1u R24 33 V_VSYNC C37 D7 100p R77 3.3K VSYNC_IN 5.6V
RP5 5 6 7 8 5 6 7 8 RP6
33*4 4 3 2 1 4 3 2 1 33*4
CA23 CA17 15p CA18 15p CA19 15p CA24 15p CA20 15p CA21 15p CA22 15p 15p
74LV14
C38 5V D8 1N4148 C40 0.1u D9 DDCVCC C159 1N4148 0.1uF 47p
L11 160808-300T VCLK00 C39 NC
ASIC_H SOG VSYNC_A
R81 2.2K
R82 2.2K P3_3V L43 16080-102 1 2 3 4 C43 22uF/16V C44 0.1u C165 0.1u C21 0.1u C46 22uF/16V C47 0.1u 3V3B L12 121L1-2601 C48 0.1u C49 0.1u C50 0.1u C51 0.1u C52 0.1u C53 0.1u VDD_33
U7
V_VSYNC V_SCL V_SDA DDC_SCL DDC_SDA C41 33p C42 33p 3V3B L44 121L1-2601 C45 100p R27 NC R28 100 SCL SDA 8 7 6 5 VCC NC VSYNC NC SCL NC SDA GND
24LC21
VD_33
C166 0.1u
C54 22uF/16V
C56 0.1u
C57 0.1u
C58 0.1u
C59 0.1u
C60 0.1u
C61 0.1u
C62 0.1u
C63 0.1u
C64 0.1u
C65 0.1u Size Date: Document Number Tuesday, October 16, 2001
ViewSonie17"
AD _ CONTROL
Sheet 2 of 8
Rev A
Page 45
9.3 Scaling Controller
R_IN0[0..7]
R_IN00 R_IN01 R_IN02 R_IN03 R_IN04 R_IN05 R_IN06 R_IN07 R_IN10 R_IN11 R_IN12 R_IN13 R_IN14
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
8 RP7 7 6 5 8 RP8 7 6 5 8 RP9 7 6 5 8 RP10 7 6 5
33*4
33*4
BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0
BB[0..7]
33*4
BA[0..7]
R_IN1[0..7]
33*4
3_3VS
120
119 VDD 118 R_IN13 117 R_IN12 116 GND 115 R_IN11 114 R_IN10 113 R_IN07 112 R_IN06 111 R_IN05 110 R_IN04 109 VDD 108 R_IN03 107 R_IN02 106 R_IN01 105 R_IN00 104 GND 103 B_OUT7_O 102 B_OUT6_O 101 B_OUT5_O 100 B_OUT4_O
R_IN14
U8
94 GND 93 B_OUT7_E 92 VDD 91 VDD 90 B_OUT6_E 89 B_OUT5_E 88 B_OUT4_E 87 B_OUT3_E 86 B_OUT2_E 85 B_OUT1_E 84 B_OUT0_E 83 GND 82 GND 81 G_OUT7_O
99 VDD 98 B_OUT3_O 97 B_OUT2_O 96 B_OUT1_O 95 B_OUT0_O
CA25 33p
CA26 33p
CA27 33p
CA28 33p
CA29 33p
CA30 33p
CA31 33p
CA32 33p
CA33 33p
CA34 33p
CA40 33p
CA35 33p
CA36 33p
CA37 33p
CA38 33p
CA39 33p
R_IN15 R_IN16 R_IN17 G_IN0[0..7] G_IN00 G_IN01 G_IN02 G_IN03 G_IN04 G_IN05 G_IN06 G_IN07 G_IN1[0..7] G_IN10 G_IN11 G_IN12 G_IN13 G_IN14 G_IN15 G_IN16 G_IN17 B_IN0[0..7] B_IN00 B_IN01 B_IN02 B_IN03 B_IN04 B_IN05 B_IN06 B_IN07 ASIC_H ASIC_V DE_IN R30 0
B_IN13 DATA_SEL B_IN14
VSYNC_O DCLK_OUT
CPU_SDA PWM_CTL CLK_1M
SCAN_EN TEST_EN VCLK01
FCLK1 VCLK1 HSYNC_O
B_IN17 ROM_SCL ROM_SDA
VDD CLK_1M_O
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 C66 N P
GND CPU_SCL
R_OUT0_E R_OUT1_E
R_OUT2_E R_OUT3_E
RESET_B R_OSD G_OSD
R_IN15 R_IN16 R_IN17 GD N G_IN00 G_IN01 G_IN02 G_IN03 VD D G_IN04 G_IN05 ADC_CLK0 G_IN06 G_IN07 GD N G_IN10 G_IN11 ADC_CLK1 G_IN12 G_IN13 VD D G_IN14 G_IN15 G_IN16 G_IN17 GD N B_IN00 B_IN01 B_IN02 VD D B_IN03 B_IN04 B_IN05 B_IN06 B_IN07 GD N HSYNC_I VSYNC_I DE_IN VD D B_IN10 B_IN11 B_IN12
SD1210-2
G_OUT6_O G_OUT5_O G_OUT4_O VD D G_OUT3_O G_OUT2_O G_OUT1_O G_OUT0_O GD N GD N G_OUT7_E G_OUT6_E G_OUT5_E VD D G_OUT4_E G_OUT3_E G_OUT2_E G_OUT1_E G_OUT0_E GD N R_OUT7_O R_OUT6_O R_OUT5_O R_OUT4_O VD D R_OUT3_O R_OUT2_O R_OUT1_O R_OUT0_O GD N R_OUT7_E R_OUT6_E GD N R_OUT5_E VD D VD D R_OUT4_E GD N V Y CX S N _ H Y CX SN _
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 5 6 7 8 CA55 33p CA41 33p CA43 33p CA42 33p CA44 33p CA45 CA46 CA48 33p 33p 33p CA47 33p CA49 33p CA72 33p CA51 33p CA52 33p CA53 33p CA54 33p CA56 33p CA57 CA58 33p 33p CA59 33p CA60 33p CA62 33p CA61 33p
8 RP11 7 6 5 8 RP12 7 6 5 8 RP13 7 6 5 8 RP14 7 6 5 8 RP15 7 6 5 8 RP16 7 6 5 8 RP17 7 6 5 4 RP18 3 2 1
33*4
G 7 B G 6 B G 5 B G 4 B G 3 B G 2 B G 1 B G 0 B G 7 A G 6 A G 5 A G 4 A G 3 A G 2 A G 1 A G 0 A RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
GB[0..7]
33*4
33*4
GA[0..7]
33*4
33*4
RB[0..7]
33*4
33*4
RA[0..7]
33*4
H Y CX SN _ CA68 33p CA67 CA64 33p 33p CA63 CA65 CA66 33p 33p 33p CA71 33p CA69 33p CA70 33p
CA137 22p CA138 22p B_IN1[0..7] B_IN10 B_IN11 B_IN12 B_IN13 B_IN14 B_IN15 B_IN16 B_IN17
CA139 22p CA140 22p
CA141 22p CA142 22p CA143 22p 22p CA144
10 11
12 13 14
15 16
17 18 19
20 21
22 23 24
25 26
27 28 29
30 31
32 33 34
35 36
37 38 39
DE_OUT GND VDD
B_OSD EN_OSD
FCLK0 VCLK00
B_IN15 B_IN16
40
1
2 3 4
5 6
7 8 9
CA50 33p
L14 800M1-1001 LCD_CLK C67 180p R31 R33 R35 R37 R38 33 33 33 33 22 C69 C71 47p R41 N C 5V R42 C74 0.1u R45 R46 33 33 100 47p C72 47p C70 47p C73 47p R32 R34 R36 R39 R40 33 33 33 33 33 C68 22p
R MS L O _C R MS A O _ D A I _ C SC S L ASIC_SDA ASIC_RESET
O DH S _ S O DV S _S LCD_DE LCD_VS LCD_HS VCLK1 FCLK1 VCLK00 VCLK01 FBLK O DB S _ OSD_G OSD_R 14.318M
1 2 3 4
U9
A0 A1 A2 V S S 24LC08 VD D W P SL C S A D
8 7 6 5
R43 4.7K
R44 4.7K
3V3B
3_3VS
C75 330uF/16V
C76 0.1u
C77 0.1u
C78 0.1u
C79 0.1u
C80 0.1u
C81 0.1u
C82 0.1u
C83 0.1u
C84 0.1u
C85 0.1u
C86 0.1u
C87 0.1u
C88 0.1u
C89 0.1u
Size Date:
Document Number
ViewSonie17"
Sheet 3 of 8
SCALING CONTROLLER
Tuesday, October 16, 2001
Rev A
Page 46
9.4 SI151
R_IN1[0..7] R_IN10 R_IN11 R_IN12 R_IN13 R_IN14 R_IN15 R_IN16 R_IN17 1 2 3 4 1 2 3 4 8 RP19 33*4 7 6 5 8 RP21 33*4 7 6 5 O3_3V 5V CA121 22p 2 1 2 1 CA122 22p CA123 22p CA124 22p CA125 22p CA126 22p CA127 22p CA128 22p 5V 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 D3_3V RP24 33*4 RP20 33*4 RP22 33*4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 CA129 22p CA130 22p CA131 22p R48 R49 R50 R51 O3_3V D3_3V C90 68p 1 2 3 4 1 2 3 4 O3_3V 47 47 47 47 C91 10p 8 RP25 33*4 7 6 5 8 RP26 33*4 7 6 5 R_IN07 R_IN06 R_IN05 R_IN04 R_IN03 R_IN02 R_IN01 R_IN00 R_IN0[0..7] CA132 22p CA133 22p CA134 22p CA135 22p G_IN17 G_IN16 G_IN15 G_IN14 G_IN13 G_IN12 G_IN11 G_IN10 B_IN17 B_IN16 B_IN15 B_IN14 B_IN13 B_IN12 B_IN11 B_IN10 CA136 22p G_IN1[0..7]
RP23 33*4
B_IN1[0..7]
U10
QO22 QO21 QO20 QO19 QO18 QO17 QO16 GND VCC QO15 QO14 QO13 QO12 QO11 QO10 QO9 QO8 OGND OVCC QO7 QO6 QO5 QO4 QO3 QO2 OGND QO23 OVCC AGND RX2+ RX2AVCC AGND AVCC RX1+ RX1AGND AVCC AGND RX0+ RX0AGND RXC+ RXCAVCC EXT_RES PVCC PGND RESERVED OCK_INV 50 QO1 49 Q O 0 48 HSYNC 47 VSYNC 46 DE 45 OGND 44 ODCK_O_CLK 43 OVCC 42 CTL3 41 CTL2 40 CTL1 39 GND 38 VCC 37 QE23 36 QE22 35 QE21 34 QE20 33 QE19 32 QE18 31 QE17 30 QE16 29 OVCC 28 OGND 27 QE15 26 QE14 2 1 2 1 O3_3V BAV99 D12 3 BAV99 D13 Rx2+ Rx2A3_3V 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Rx1+ Rx1R87 1K Rx0+ Rx0RxC+ RxCA3_3V PD3_3V 3 3 3 D16 BAV99 D17 BAV99 D14 BAV99 3 D15 BAV99
BAV99 D10 3
BAV99 D11 3
J5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 DVI_5V TMDS D2TMDS D2+ TMDS D2/4 SH TMDS D4TMDS D4+ DDC CLK DDC DATA A_V_SYNC TMDS D1TMDS D1+ TMDS D1/3 SH TMDS D3TMDS D3+ +5V
DVI-I connector GND H_P_DETECT TMDS D0TMDS D0+ TMDS D0/5 SH TMDS D5TMDS D5+ TMDS CLK SH TMDS CLK+ TMDS CLKC1 C2 C3 C4
DVI_5V
R80
4.7K 2 1 2 1 2 1 2 1 D3_3V
5V C92 0.1u R53 4.7K R54 4.7K SCDT PDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DFO PD ST PIXS GND VCC STAG_OUT SCDT PDO QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 OVCC OGND QE8 QE9 QE10 QE11 QE12 QE13
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 R52 510 96 97 98 99 100
HSYNC_D VSYNC_D DE_IN VCLK01
3
SI151
O3_3V
3
1 2 3 4
U11
A0 A1 A2 VSS 24LC08 VDD WP SCL SDA
D18 BAV99
3
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
8 RP27 33*4 7 6 5 8 RP28 33*4 7 6 5 8 RP29 33*4 7 6 5 8 RP30 33*4 7 6 5
G_IN07 G_IN06 G_IN05 G_IN04 G_IN03 G_IN02 G_IN01 G_IN00 B_IN07 B_IN06 B_IN05 B_IN04 B_IN03 B_IN02 B_IN01 B_IN00
G_IN0[0..7]
D19 BAV99
8 7 2 1 2 6 3V3B 5 5V L17 121L1-2601 C93 47uF/16V C94 0.1u C95 0.1u C96 0.1u C97 0.1u D3_3V 1
B_IN0[0..7]
3V3B L20 121L1-2601 C160 100P C98 47uF/16V
O3_3V
3V3B L21 121L1-2601
PD3_3V
3V3B L22 121L1-2601
A3_3V
C99 0.1u
C100 0.1u
C101 0.1u
C102 0.1u
C103 0.1u
C104 0.1u
C161 100P
C105 10uF/16V
C106 0.1u
C107 0.1u
C162 100P
C108 22uF/16V
C109 0.1u
C110 0.1u
C111 0.1u
C112 0.1u Size Date: Document Number
ViewSonie17"
SI151
Sheet 4 of 8
Rev A
Tuesday, October 16, 2001
Page 47
9.5 PLL
3V3A
C113 0.1u
U12
HSYNC_D SOG VSYNC_D VSYNC_A 12 13 2 1 1Y0 1Z 1Y1 2Y0 2Y1 FCLK1 HSYNC_D HSYNC_X 5 3 3Z 3Y0 3Y1 E_ VEE S1 S2 S3 GND 74HC4053 R55 6 7 8 PLL_PD NC 4 4 PLL_A PLL_B 2Z 15 MCU_VS_IN 1 2 3 C114 C115 0.1u C116 10uF/16V OSD_CLK L24 160808-121 6 5 C117 180p C118 33p VCLK1 VCC
16
14
MCU_HS_IN
5V L23 2012-260
U13
FBIN IN GND FSO MK9173 CLK2 VDD CLK1 OE
8 7
0.01u
11
10
INPUT_SEL
9
Size Date:
Document Number
ViewSonie17"
PLL
Sheet 5 of 8
Rev A
Tuesday, October 16, 2001
Page 48
9.6 LVDS
3V3LVDSD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
U14
VCC D5 D6 D7 GND D8 D9 D10 VCC D11 D12 D13 GND D14 D15 D16 CLKSEL D17 D18 D19 GND D20 D21 D22 D23 VCC D24 D25 D4 D3 D2 GND D1 D0 D27 LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP Y3M Y3P LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D26 GND 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RB4 RB3 RB2 RB1 RB0 RB6 TXO0M TXO0P TXO1M TXO1P 3V3LVDSA TXO2M TXO2P TXOCKM TXOCKP TXO3M TXO3P 3V3LVDSP 3V3LVDSP LCD_CLK LCD_DE
J6
TXO3P TXOCKP TXO2P TXO1P TXO0P 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 TXO3M TXOCKM TXO2M TXO1M TXO0M LCD_VCC TXE3P TXECKP TXE2P TXE1P TXE0P LCD_VCC LCD_VCC R84 0
RB7 RB5 GB0 GB1 GB2 GB6 GB7 GB3 GB4 GB5 BB0 BB6 BB7 BB1 BB2 BB3 BB4 BB5 LCD_HS LCD_VS LCD_HS LCD_VS
3V3LVDSA
R56 NC
TXE3M TXECKM TXE2M TXE1M TXE0M LCD_VCC LCD_VCC
R83 NC
LVDS O/P
R57 0
LCD_CLK LCD_DE
SN75LVDS83
3V3LVDSD
U15
RA7 RA5 GA0 GA1 GA2 GA6 GA7 GA3 GA4 GA5 BA0 BA6 BA7 BA1 BA2 BA3 BA4 BA5 LCD_HS LCD_VS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC D5 D6 D7 GND D8 D9 D10 VCC D11 D12 D13 GND D14 D15 D16 CLKSEL D17 D18 D19 GND D20 D21 D22 D23 VCC D24 D25 D4 D3 D2 GND D1 D0 D27 LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP Y3M Y3P LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D26 GND 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RA4 RA3 RA2 RA1 RA0 RA6 TXE0M TXE0P TXE1M TXE1P 3V3LVDSA TXE2M TXE2P TXECKM TXECKP TXE3M TXE3P L27 3V3LVDSP 2012-260 C132 LCD_CLK LCD_DE 22uF/16V C133 0.1u C134 0.1u 3V3B L25 2012-260 C119 47uF/16V C120 22uF/16V C121 0.1u C122 0.1u C123 0.1u C124 0.1u C125 0.1u C126 0.1u C127 0.1u C128 0.1u 3V3LVDSD
3V3LVDSA L26 2012-260 C129 22uF/16V C130 0.1u C131 0.1u
R58 NC
R59 0
3V3LVDSP
SN75LVDS83
Size
Document Number
ViewSonie17"
LVDS
Sheet 6 of 8
Rev A
Page 49
Date:
Tuesday, October 16, 2001
9.7 TTL
C135 BA[0..7] C136 BA0 BA1 BA2 BA3 CA73 CA74 CA75 CA76 22p 22p 22p 22p C137 C138
10p 22P 22P 22P
LCD_CLK LCD_DE LCD_VS LCD_HS
LCD_CLK LCD_DE LCD_VS LCD_HS
BA4 BA5 BA6 BA7
CA77 CA78 CA79 CA80
22p 22p 22p 22p
GA[0..7]
GA0 GA1 GA2 GA3
CA81 CA82 CA83 CA84
22p 22p 22p 22p
J7
GA1 GA3 GA4 GA6 BA1 BA3 BA4 BA6 LCD_CLK 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GA0 GA2 GA5 GA7 BA0 BA2 BA5 BA7 RB1 RB3 RB4 RB6 GB1 GB3 GB4 GB6 BB1 BB3 BB4 BB6 RA1 RA3 RA4 RA6
J8
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 RB0 RB2 RB5 RB7 GB0 GB2 GB5 GB7 BB0 BB2 BB5 BB7 RA0 RA2 RA5 RA7
GA4 GA5 GA6 GA7
CA85 CA86 CA87 CA88
22p 22p 22p 22p
RA[0..7]
RA0 RA1 RA2 RA3
CA89 CA90 CA91 CA92
22p 22p 22p 22p
LCD_DE LCD_VCC LCD_VCC LCD_HS
LCD_VCC LCD_VCC LCD_VCC LCD_VS
RA4 RA5 RA6 RA7
CA93 CA94 CA95 CA96
22p 22p 22p 22p
TTL_OUT TTL_OUT
BB[0..7]
BB0 BB1 BB2 BB3
CA97 CA98 CA99 CA100
22p 22p 22p 22p
BB4 BB5 BB6 BB7
CA101 CA102 CA103 CA104
22p 22p 22p 22p
GB[0..7]
GB0 GB1 GB2 GB3
CA105 CA106 CA107 CA108
22p 22p 22p 22p
GB4 GB5 GB6 GB7
CA109 CA110 CA111 CA112
22p 22p 22p 22p
RB[0..7]
RB0 RB1 RB2 RB3
CA113 CA114 CA115 CA116
22p 22p 22p 22p
RB4 RB5 RB6 RB7
CA117 CA118 CA119 CA120
22p 22p 22p 22p
Size Date:
Document Number
ViewSonie17"
TTL
Sheet 7 of 8
Rev A
Tuesday, October 16, 2001
Page 50
9.8 MCU
5V C164 0.1u
J9
FBLK OSD_B OSD_G OSD_R OSD_CLK OSD_HS OSD_VS ON/OFF ADD R60 R61 R62 33 33 100 C139 NC C140 22p C141 220p 3V3A 4 3 2 1 4.7K 4.7K RP31 4.7K*4 5 6 7 8 OSD LED_ORG R63 1K 5V C167 C172 0.1u R64 510 C173 0.1u C174 0.1u C175 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u C168 C169 C170 C171 L28 L30 L33 L35 160808-121 160808-121 160808-121 160808-121 1 3 5 7 9 11 CON12 2 4 6 8 10 12 L29 L31 L32 L34 L42 160808-121 160808-121 160808-121 160808-121 160808-121 SUB DOWN SELECT LED_GRN LED_MUTE
4 3 2 1
C142 RP32 4.7K*4 0.1u
R65
R66
R67 1K 3V3A 44 43 42 41 C143 1u 4 3 2 1 RP33 4.7K*4 39 38 37 36 35 34 33 32 31 30 29 3V3A P1.0 P1.1 P1.2 P1.3 ON/OFF ADD SUB OSD M_SCL M_SDA DOWN SELECT 5 6 7 8 5 6 7 8 4 3 2 1
5 6 7 8
PSC1 PWM
5V
ASIC_V 6 5 4 3 2 1 C144 3V3A R85 NC C145 NC C146 16p 1 R69 0 R70 X1 14.318M 2 1M 7 8 PLL_PD PSC0 ASIC_RESET PDO MCU_VS_IN MCU_HS_IN DDC_SCL DDC_SDA SCDT 4 3 2 1 RP35 4.7K*4 VDD VSS RST 5 6 7 8 D_SCL D_SDA 9 10 11 12 13 14 15 16 17 X1 X2 P4.5 P4.4 P4.3 P4.2 P4.1/VSYNC P4.0/HSYNC P3.0/Rxd/HSCL P3.1/Txd/HSDA P3.2/INT0 P6.1/ISDA P6.0/ISCL 16p 40 P4.7/VBLANK P4.6/HBLANK OSDVS
P5.7/DA3
OSDHS
FBKG
GOUT
ROUT
BOUT
U16
XIN
INT/P6.2
GRN RP34 4.7K*4 R78 1K GRN AMBER C163 1u MUTE_LED 2 3
1 Q6 2N3904 R68 2 330 LED_GRN R71 330 LED_ORG 3 1 Q8 2N3904 2
AMBER VOLUME
1 Q7 2N3904
X2
P5.6/DA2 P5.5/DA1 P5.4/DA0 P5.3/AD3 P5.2/AD2 P5.1/AD1 P5.0/AD0 P1.7 P1.6 P1.5 P1.4
3
R79
120 LED_MUTE
MCU_SCL MCU_SDA 3V3A L36 2012-260 C147 0.1u PSC0A X2 1 2 R72 100 3 C148 NC PDO V_SCL DDC_SCL 4 5 6 7
U17
1OE_ 1A 1Y 2OE_ 2A 2Y GND VCC 4OE_ 4A 4Y 3OE_ 3A 3Y 14 13 12 R73 100 11 10 9 8 C149 NC VCLK00 SD_MODE
P3.4/T0
P3.5/T1
4 3 2 1
4 3 2 1
18
19
20
21
22
23
24
25
26
27
3V3A C150 0.1u U21 RST VCC GND DS1813 1 2 3 D5 1N4148 R74 10K C151 0.1u A_SCL A_SDA 5 6 7 8 5 6 7 8
28
3V3A
SM0230
RP36 4.7K*4
RP37 4.7K*4
14.318M
ROM_SCL ROM_SDA ASIC_SCL ASIC_SDA INPUT_SEL MUTE_LED SD_MODE BL_ON_OFF MUTE_LED
SN74LVC125A
5V
J10
1 2 3 4 5 6 7 8 CON8 M_SCL M_SDA A_SCL A_SDA D_SCL D_SDA
3V3A C152
1 2 3 4
U18
A0 A1 A2 VSS VDD WP SCL SDA
0.1u 8 7 6 5 SCL SDA R75 33 R76 33
24LC16
Size Date: Document Number
ViewSonie17"
Sheet 8 of 8
MICRO _ CONTROLLER
Tuesday, October 16, 2001
Rev A
Page 51