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9.
9-1. External Graphic
9 - 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION D
PCI Devices Voltage Rails
Devices IDSEL# REQ/GNT# Interrupts
Cardbus AD25 0 A,B,C VDC Primary DC system power supply (7 to 21V)
AD21 3 VCC_CORE Core voltage for DOTHAN (1.308~1.068V)
MiniPCI SLOT1 AD23 2 D,E VTT DOTHAN/ALVISO Processor System Bus(PSB) Termination (1.05V)
USB AD29(internal) - USB2.0 #0 : A MCH-M Core Voltage
USB2.0 #1 : D
USB2.0 #2 : C P0.9V 0.9V switched power rail (off in S3-S5)
Hub to PCI AD30(internal) - - P1.2V 1.2V switched power rail (off in S3-S5)
LPC bridge/IDE/AC97/SMBUS AD31(internal) - B P1.5V 1.5V switched power rail (off in S3-S5)
- A,B P1.5V_AUX 1.5V power rail (off in S4-S5)
Internal MAC AD24(internal) - E P1.8V 1.8V switched power rail (off in S3-S5)
AC Link - - B P1.8V_AUX 1.8V power rail(off in S4-S5)
P2.5V 2.5V switched power rail (off in S3-S5)
MICOM_P3V 3.3V always on power rail for MICOM
P3.3V 3.3V switched power rail (off in S3-S5)
P3.3V_AUX 3.3V power rail (off in S4-S5)
C P5V 5.0V switched power rail (off in S3-S5) C
P5V_AUX 5.0V power rail (off in S4-S5)
CPU Core Voltage Table
2
VID5 VID4 VID3 VID2 VID1 VID0 Voltage VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0 0 0 0 0 0 1.708 V 1 0 0 0 0 0 1.196 V Northwood-B
I C / SMB Address
0 0 0 0 0 1 1.692 V 1 0 0 0 0 1 1.180 V (Interposer B'd) Devices Address Hex Bus
0 0 0 0 1 0 1.676 V 1 0 0 0 1 0 1.164 V
0 0 0 0 1 1 1.660 V 1 0 0 0 1 1 1.148 V ICH6 Master - SMBUS Master
0 0 0 1 0 0 1.644 V 1 0 0 1 0 0 1.132 V EMC6N300(CPU Thermal Sensor) 1001 110X 9Ch Thermal Sensor
0 0 0 1 0 1 1.628 V 1 0 0 1 0 1 1.116 V SODIMM0 1010 0000 A0h -
0 0 0 1 1 0 1.612 V 1 0 0 1 1 0 1.100 V SODIMM1 1010 001X A2h -
-
0 0
- 0 1 1 1 1.596 V 1 0
- 0 1 1 1 1.084 V CK-408 (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable
0 0 1 0 0 0 1.580 V 1 0 1 0 0 0 1.068 V
0 0 1 0 0 1 1.564 V 1 0 1 0 0 1 1.052 V
0 0 1 0 1 0 1.548 V 1 0 1 0 1 0 1.036 V
0 0 1 0 1 1 1.532 V 1 0 1 0 1 1 1.020 V
0 0 1 1 0 0 1.516 V 1 0 1 1 0 0 1.004 V
0
0
0
0
1
1
1
1
0
1
1
0
1.500 V
1.484 V
1
1
0
0
1
1
1
1
0
1
1
0
0.988 V
0.972 V USB PORT Assign
0 0 1 1 1 1 1.468 V 1 0 1 1 1 1 0.956 V
0 1 0 0 0 0 1.452 V 1 1 0 0 0 0 0.940 V PORT NUMBER ASSIGNED TO
0 1 0 0 0 1 1.436 V 1 1 0 0 0 1 0.924 V
0 1 0 0 1 0 1.420 V 1 1 0 0 1 0 0.908 V 0 SYSTEM PORT A
0 1 0 0 1 1 1.404 V 1 1 0 0 1 1 0.892 V 1,2 SYSTEM PORT B
B 0 1 0 1 0 0 1.388 V 1 1 0 1 0 0 0.876 V 3 BLUETOOTH OPTION B
0 1 0 1 0 1 1.372 V 1 1 0 1 0 1 0.860 V 4 FINGER PRINT OPTION
Highest Freq. 0 1 0 1 1 0 1.356 V 1 1 0 1 1 0 0.844 V Lowest Freq.
-
0 1 0 1 1 1 1.340 V 1 1 0 1 1 1 0.828 V
0 1 1 0 0 0 1.324 V 1 1 1 0 0 0 0.812 V
0 1 1 0 0 1 1.308 V 1 1 1 0 0 1 0.796 V
0 1 1 0 1 0 1.292 V 1 1 1 0 1 0 0.780 V
0
0
1
1
1
1
0
1
1
0
1
0
1.276 V
1.260 V
1
1
1
1
1
1
0
1
1
0
1
0
0.764 V
0.748 V Deeper Sleep System Power States
0 1 1 1 0 1 1.244 V 1 1 1 1 0 1 0.732 V CHP3_SLPS1* S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped.
0 1 1 1 1 0 1.228 V 1 1 1 1 1 0 0.716 V The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems.
0 1 1 1 1 1 1.212 V 1 1 1 1 1 1 0.700 V Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected
for either Deep Sleep or Deeper Sleep.
In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power.
CHP3_SLPS3* S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits.
Memory is retained, and refreshes continue. All clocks stop except RTC clock.
CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.
Externally appears same as S5, but may have different wake events.
CHP3_SLPS5* S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.
REVISION HISTORY
A A
See rev notes in the changes file for more information.
SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D D
MMZ1608S121AT P3.3V
B524
TP10380
1000nF
100nF
100nF
100nF
10nF
10nF
47nF
47nF
47nF
C679
10000nF
C274
C268
C678
C279
C278
C273
C269
C276
C275
6.3V
FSA FSB FSC
HOST CLK CK-410M
BSEL2 BSEL1 BSEL0
ICS954201
0 0 0 266 MHz CY28411ZC TP10388
U504
10K
0 0 1 333 MHz CY28411ZXCT MMZ1608S121AT
100nF
100nF
21 48
47nF
B15
0 1 0 200 MHz 28
VDD_SRC0 VDD_REF
11 C271
VDD_SRC1 VDD_48 10000nF
0 1 1 400 MHz 34
VDD_SRC2 6.3V
R655
1 37
C270
C272
C277
1 0 0 133 MHz 7
VDD_PCI0 VDD_A
VDD_PCI1
1 0 1 100 MHz 42
VDD_CPU VSS_A
38
1 1 0 166 MHz 18-A? 48-C3 R654 TP10381
33 1% 12
CLK3_USB48 FSA_USB48
41 TP10389
1 1 1 RSVD CLK3_BSEL1
16
FSB_TESTMODE CPU1
R610 33 1% 10-C2
CLK0_HCLK1
7-C3 7-D1 11-?4 48-D3 53 40 TP10390 R611 33 1% 10-C2
C CLK3_BSEL2 7-C3 7-D1 11-?4 48-D3
FSC_TESTSEL CPU1* CLK0_HCLK1* C
55 44 TP10391 R606 33 1% 7-D3
CHP3_PCISTP* PCI_STOP* CPU0
43 TP10392
CLK0_HCLK0
18-C? 48-B4 54 R608 33 1% 7-D3
CHP3_CPUSTP* 18-C? 42-C4 48-B4
CPU_STOP* CPU0* CLK0_HCLK0*
R653 100 1% TP10382 10 36
CLK3_PWRGD* 9-B4 24-B4 34-B1 48-C3
VTT_PWRGD*_PD CPU2_ITP_SRC7
35
TP10383 CPU2*_ITP_SRC7*
CLK3_PCLKSIO R649 12.1 1% 5
PCI5
37-D1 48-C3 R650 12.1 1% 33
CLK3_TPMLPC 45-B4 48-C3 R647 12.1 1% TP10384 4
SRC6
32
CLK3_PCLKMIN PCI4 SRC6*
29-C3 48-C3 R648 12.1 1%
CLK3_SIOPCI_DS 37-D1 48-C3 R645 12.1 1% TP10385 3 31 TP10393 R618 33 1%
CLK3_PCLKCB R646 PCI3 SRC5
30 TP10394
CLK1_MCH3GPLL
CLK3_PCLKLAN
27-A4 48-C3 12.1 1%
SRC5* R620 33 1% 11-D?
CLK1_MCH3GPLL*
35-B4 48-C3 R602 33 1% TP11291 56 11-D?
CLK3_PCLKFWH PCI2
26 TP10395
21-C4 48-C3
SRC4 R665 33 1%
CLK1_SATA
R652 33 1% TP10386 9 27 TP10396 R667 33 1% 17-B3
CLK3_PCLKMICOM 34-C2 48-C3
PCIF1 SRC4* 17-B3
CLK1_SATA*
R651 33 1% TP10580 8 24 TP10397 R660 33 1%
CLK3_PCLKICH 18-C? 48-C3
PCIF0_ITPEN SRC3
25 TP10398 R663 33 1% 18-B?
CLK1_PCIEICH
5-A3 15-B2 15-B4 48-C3 46
SRC3* 18-B?
CLK1_PCIEICH*
CLK3_SMBCLK SCLK
22 TP10399
5-A3 15-B2 15-B4 48-C3 47 R656 33 1%
CLK3_SMBDATA SDATA SRC2
23 TP10400
CLK1_PCIELAN
SRC2* R659 33 1% 37-B4
CLK1_PCIELAN*
TP10387 50 37-B4
TP10581 XTAL_IN
49 19 TP11259 R874 33 1%
XTAL_OUT SRC1
20 TP11260
CLK1_DOTCLK
R875 33 1% 24-B3
TP10578 39
SRC1* 24-B3
CLK1_DOTCLK*
IREF
17
Y500 SRC0
13 18
14.31818MHz VSS_48 SRC0*
R613 29
VSS_SRC
B Place 14.318MHz within 475 45 14 TP10401 R851 33 1% B
1
2
1% 2
VSS_CPU DOT96
15 TP10402 R852 33 1% 11-?2
CLK1_DREFCLK
500mils of CK-410M VSS_PCI0 DOT96* CLK1_DREFCLK*
6 11-?2
TP10579 VSS_PCI1
51 52 TP10577 R603 12.1 1%
VSS_REF REF CLK3_ICH14
C677 C676 R604 12.1 1% 48-D3 18-B?
CLK3_SIO14
0.033nF 0.033nF R850 12.1 1% 48-C3 37-D1
48-C3 24-C4
CLK3_SSCIN
NO STUFF
1%
1%
1%
1%
49.9 1%
49.9 1%
49.9 1%
49.9 1%
49.9 1%
49.9 1%
1%
1%
1%
1%
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
Place Termination close to CK-410M