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AP-479
APPLICATION
NOTE




Pentium
Processor
Clock Design




November 1995



Order Number 241574-002
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Intel Corporation
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COPYRIGHT INTEL CORPORATION 1996
Pentium Processor Clock Design
CONTENTS PAGE CONTENTS PAGE

1 0 INTRODUCTION 1 FIGURES
1 1 General Clocking Issues 1 Figure 1 Common Termination
Techniques 2
2 0 Pentium PROCESSOR 82496 AND Figure 2 Clock Requirements for the
82491 SYSTEM CLOCK Pentium Processor and CPU-
SPECIFICATIONS 2
Cache Chip Set 4
3 0 AVAILABLE CLOCK DRIVERS 7 Figure 3 An Example of an Acceptable
Clock Waveform (Diodes Are
4 0 CLOCK GENERATION FOR THE Absent from the Input
Pentium PROCESSOR AND THE Model) 5
CPU-CACHE CHIP SET 11 Figure 4 An Example of an Acceptable
4 1 Clock Generation for Fully Clock Waveform (Diodes Are
Synchronous Systems 12 Present in the Input Model) 6
4 2 Clock Generation for Divided Figure 5 An Example of an
Synchronous Systems 12 Unacceptable Clock Waveform
(Diodes Are Absent from the
4 3 Clock Generation for Input Model) 7
Asynchronous Systems 16
Figure 6 A CPU Module with the
5 0 Pentium PROCESSOR WITH 256K Pentium Processor 82496
82496 82491 SECOND LEVEL and 82491 CPU-Cache Chip
CACHE CLOCK DISTRIBUTION Set 11
DESIGN EXAMPLES 16 Figure 7 Examples of Clock
5 1 Clock Routing for the 256K CPU- Generation 12
Cache Chip Set 16 Figure 8 Clock Generation Using Clock
5 2 Analysis of Drivers Used in Doubler 13
Examples 22 Figure 9 Clock Generation Using Clock
Doubler 13
6 0 Pentium PROCESSOR WITH 512K
82496 82491 SECOND LEVEL Figure 10 Clock Generation Using Clock
CACHE CLOCK DISTRIBUTION Divider 14
ISSUES 32 Figure 11 Clock Generation Using Two
PLLs 14
7 0 CLOCK DISTRIBUTION FOR THE
Pentium PROCESSOR WITH Figure 12 Clock Generation Using Two
OTHER SECOND LEVEL CACHES 32 PLLs 15
Figure 13 Pentium Processor 82496
8 0 SUMMARY 32 and 82491 Clock Input
Models 17
9 0 REFERENCES 32
Figure 14 CLK0 Layout for 256K Chip Set
APPENDIX A CLOCK DRIVER with Parity 18
MANUFACTURERS A-1 Figure 15 CLK1 Layout for 256K Chip Set
with Parity 19
Figure 16 CLK2 Layout for 256K Chip Set
with Parity 20
CONTENTS PAGE CONTENTS PAGE

FIGURES TABLES
Figure 17 CLK3 Layout for 256K Chip Set Table 1 Clock Signal Quality
with Parity 21 Specifications 3
Figure 18 Motorola Waveform 25 Table 2 Clock Signal Quality
Figure 19 National Waveform 26
Guidelines 3

Figure 20 Vitesse (Slow) Waveform 27
Table 3 Clock Driver Options 8

Figure 21 Vitesse (Slow) Waveform Table 4 List of Clock Doubler Parts 15
(Continued) 28 Table 5 List of Clock Divider Parts 15
Figure 22 Vitesse (Fast) Waveform 29 Table 6 Interconnect Characteristics 22
Figure 23 Triquint Waveform 30 Table 7 Compilation of Simulation
Figure 24 Triquint Waveform (Contd ) 31
Data 23
Table 8 Series Termination Resistor
Values for Each Line 24
AP-479


10 INTRODUCTION 1 1 General Clocking Issues
Today's high speed microprocessors place a heavy de- There are two major problems with distributing clock
mand on clock generation and distribution To main- signals at 66 MHz clock signal quality and clock skew
tain a synchronous system well-controlled and precise At high speed one set of effects which has been minor
clocking solutions are required Pentium processor in slower designs is now significant the effects of
with operating frequencies of 60 MHz and 66 MHz has transmission line At high frequencies and fast edge
tight system clock specifications In order to bring rates long traces behave like transmission lines The
clock signals of acceptable quality and minimal skew to ``lumped'' circuit assumption which assumes instanta-
the Pentium processor and the rest of the system sys- neous signal transmission is no longer valid Instead
tem designers have to contend with high speed issues signals travel in a finite time When a transmission line
for clock distribution and limited number of precise is not properly terminated one can observe severe over-
clock driver devices In this application note the key shoot undershoot and ringback all of which degrade
issues in the design of a 60 MHz or 66 MHz clock for a logical signals Bad signal quality can cause false
Pentium processor-based system will be discussed switching or multiple switching and can in extreme
available clock drivers will be listed and discussed and cases damage the devices To maintain a clean clock
detailed design examples of a clock solution for the signal designers must consider clock driver characteris-
Pentium processor with 256K second-level cache sub- tics signal routing load characteristics and transmis-
system using the 82496 Cache Controller and the sion line termination
82491 Cache SRAMs are provided
There are four basic ways to terminate a transmission
The Pentium processor 82496 Cache Controller and line series parallel Thevenin and AC terminations
82491 Cache SRAM form a CPU-Cache core or chip (Figure 1) Series termination is recommended when
set Along with a memory bus controller (MBC) the driver output impedance is less than the transmission
chip set provides a CPU-like interface for many types line characteristic impedance (true for most TTL driv-
of memory buses ers) and the line is driving a small number of devices
Series termination consumes low power and uses only
This application note is intended for system designers one device however the termination method increases
concerned with clock generation and distribution for signal rise and fall times Series termination ensures
the Pentium processor and CPU-Cache chip set based good signal quality by eliminating secondary reflection
systems It reflects data collected from several quarters off the driver end The rest of the termination methods
of characterization of the Pentium processor and expe- eliminate reflection at the load end All of the termina-
rience with some of the clock driver devices as well tion methods can provide good clean clock signals at
This application note gives readers a good understand- the load Both parallel and Thevenin terminations con-
ing of the issues and solutions of high speed clocking sume a large amount of power Thevenin termination
particularly that for the Pentium processor The reader consumes less power than parallel but requires one
should be familiar with the Pentium processor and more device AC termination consumes low power but
CPU-Cache chip set electrical and mechanical specifi- adds capacitive load to the driver and delay due to RC
cations Clock Design in 50 MHz Intel486 TM Systems time constant Design examples provided with this ap-
and transmission line theory If not please read materi- plication note use series termination For more infor-
als listed in Section 9 0 before proceeding mation on transmission line effects and design issues
please refer to ref 3 ref 4 ref 5




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AP-479




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