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1 1




Compal Confidential
2 2




KAL90 M/B Schematics Document
Intel Penryn Processor with Cantiga + DDRII + ICH9M




3 2008-10-30 3




REV:1.0




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/28 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,A4491
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401597
Date: Thursday, October 30, 2008 Sheet 1 of 52
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A B C D E




Compal Confidential
Intel Penryn Processor Thermal Sensor Clock Generator
Fan Control
Model Name : KAL90 page 40
EMC 1402 ICS9LPRS387
uPGA-478 Package page 4 page 16
File Name : LA-4491P
(Socket P) page 4,5,6
1 1
FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)

HDMI Conn. LCD Conn. CRT Conn.
page 24 page 22 page 23
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel Cantiga
LVDS Dual Channel BANK 0, 1, 2, 3 page 14,15

1.8V DDRII 533/667
TMDS LVDS uFCBGA-1329
PCI-Express page 7,8,9,10,11,12,13
Card Reader 16X
JMB385 VGA USB conn x3 Bluetooth CMOS LS-4494P
page 30 DMI C-Link Finger Print
page 17,18,19,20,21
USB port 0, 2, 5 Conn Camera
page 33 page 34 page 22 AES1610

PCI-Express
2
Intel ICH9-M 3.3V 48MHz USB
2




3.3V 24.576MHz/48Mhz HD Audio
S-ATA
BGA-676
LAN(GbE) MINI Card x2 New Card page 25,26,27,28
ATHEROS AR8121 WLAN, Robson2 Socket
page 31 page 33 page 34 GMCH HDA MDC 1.5 HDA Codec VGA HDA
Conn 37 ALC888S-VC
port 2 port 1 port 0 page 08 page page 38 page 18


RJ45 ESATA CDROM SATA HDD
page 32
Conn.
page 34
Conn.
page 29
Conn.
page 29 Audio AMP
page 39
LPC BUS
3 3


ENE KB926 Phone Jack x3
page 35 page 39

RTC CKT.
page 37
LS-4493P Touch Pad Int.KBD
page 36 page 36
Power On/Off CKT. Media/B Conn.
page 37 LS-4498P EC I/O Buffer BIOS
FUN Conn. page 36 page 36
DC/DC Interface CKT.
page 44
LS-4492P
E_KEY/B Conn. CIR
Power Circuit DC/DC LS-4495P page 37
4
page 44,45,46,47,48 ,49,50,51 USB/B Conn. 4

USB port 1

POWER SW
Page 42
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/28 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,A4491
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401597
Date: Thursday, October 30, 2008 Sheet 2 of 52
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5V 1.5V power rail for HDA ON ON OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.1VS 1.1V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V 3.3V power rail for SB ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN 3.3V power rail for LAN ON ON X 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VS 3.3V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2 2
+RTCVCC RTC power ON ON ON
+VGA_CORE Core voltage for GPU ON OFF OFF
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision BTO Item BOM Structure
External PCI Devices 0 0.1 JAL90 JAL90@
Device IDSEL# REQ#/GNT# Interrupts
1 0.2 JAW50 JAW50@
2 0.3 UMA GM@
3 1.0 JAL90-UMA JAL90GM@
4 1A JAW50
GLPM@
5 Discrete
6 Discrete PM@
7 ALC888VC 888VC@
ALC888VB 888VB@
AR8121 8121@
EC SM Bus1 address EC SM Bus2 address AR8112 8112@
3
Device Address Device Address
ALC268 268@ 3


Smart Battery 0001 011X b ADI ADT7421 1001 100X b
MEDIA CONSOLE 1010 000X b NB9M THERMAL SENSOR




BOM Configuration Table
ICH9M SM Bus address Project BOM Configuration
KAL90-UMA XXXXXXXXXX:JAL90GM@/JAL90@/GM@/888VC@/8121@/ESATA@
Device Address KAL90-Dis XXXXXXXXXX:PM@/JAL90@/GLPM@/888VC@/8121@/ESATA@
Clock Generator 1101 001Xb
(ICS9LPRS387, SLG8SP556V)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/28 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,A4491
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401597
Date: Thursday, October 30, 2008 Sheet 3 of 52
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5 4 3 2 1




H_A#[3..35]
<7> H_A#[3..35]
H_REQ#[0..4]
<7> H_REQ#[0..4]
H_RS#[0..2]
<7> H_RS#[0..2]
JCPU1A
H_A#3 J4 H1 H_ADS# <7>
A[3]# ADS#




ADDR GROUP_0
H_A#4 L5 E2 H_BNR# <7>
H_A#5 A[4]# BNR#
D L4 A[5]# BPRI# G5 H_BPRI# <7> D
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# <7>
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# <7>
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# <7>
H_A#12 P2 A[12]#




CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# <26>
H_A#15 P1
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# <7>
<7> H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET# H_RESET# <7>
H_REQ#0 RESET# H_RS#0
K3 REQ[0]# RS[0]# F3
H_REQ#1 H2 F4 H_RS#1
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3
H_REQ#3 J3 G2 H_TRDY# <7>
H_REQ#4 REQ[3]# TRDY#
L1 REQ[4]#
HIT# G6 H_HIT# <7>
H_A#17 Y2 E4
A[17]# HITM# H_HITM# <7>
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4

ADDR GROUP_1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#
XDP/ITP SIGNALS
H_A#23 U1 AC2
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
C H_A#26 A[25]# TCK XDP_TDI C
T3 A[26]# TDI AA6
H_A#27 W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# <27>
H_A#31 V4
H_A#32 A[31]# +1.05VS
W3 A[32]#
H_A#33 AA4 THERMAL
H_A#34 A[33]#
AB2 A[34]#
H_A#35 AA3 D21 H_PROCHOT#
A[35]# PROCHOT# H_THERMDA
<7> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC XDP_TDI R2 1 2 54.9_0402_1%
THERMDC
<26> H_A20M# A6 A20M#
ICH
ICH




<26> H_FERR# A5 FERR# THERMTRIP# C7 H_THERMTRIP# <8,26> left NC if no ITP
<26> H_IGNNE# C4 IGNNE# XDP_TMS R3 1 2 54.9_0402_1% 39Ohm
<26> H_STPCLK# D5 STPCLK#
C6 H CLK XDP_BPM#5 R5 1 2 54.9_0402_1%
<26> H_INTR LINT0
<26> H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK <16>
<26> H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# <16> @

M4 H_PROCHOT# R13 2 1 56_0402_5%
RSVD[01]
N5 RSVD[02]
T2 H_IERR# R18 2 1 56_0402_5%
RSVD[03]
V3 RSVD[04]
RESERVED




B2 RSVD[05] Layout Note:
D2 RSVD[06]
D22 H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
RSVD[07]
D3 RSVD[08]
B XDP_TRST# R7 54.9_0402_1% B
F6 RSVD[09] 2 1

XDP_TCK R8 1 2 54.9_0402_1%


Penryn

CONN@
+3VS
C2
0.1U_0402_16V4Z
1 2

+1.05VS U1
BSEL2 BSEL1 BSEL0 BCLK H_THERMDA

0 0 0 266 1 VDD SMCLK 8 EC_SMB_CK2 <18,35>
1




1
R17 C3 2 7
DP SMDATA EC_SMB_DA2 <18,35>
0 1 0 200 56_0402_5%
2200P_0402_50V7K 3 DN ALERT# 6 1 2 +3VS
2 R1133
2




0 1 1 166 4 5 10K_0402_5%
H_THERMDC THERM# GND
2
B




@
E




H_PROCHOT# 3 1 OCP# <27> EMC1402-1-ACZL-TR_MSOP8
A A
C




Q1
MMBT3904_SOT23-3


@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/28 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,A4491
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401597
Date: Thursday, October 30, 2008 Sheet 4 of 52
5 4 3 2 1
5 4 3 2 1




H_D#[0..63] JCPU1C
H_D#[0..63] <7>
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JCPU1B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12




DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13




DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VCC[006] VCC[073]
F23 D[4]# D[36]# V23 A17 VCC[007] VCC[074] AC15
H_D#5 G25 T22 H_D#37 A18 AC17
H_D#6 D[5]# D[37]# H_D#38 VCC[008] VCC[075]
E25 D[6]# D[38]# U25 A20 VCC[009] VCC[076] AC18
H_D#7 E23 U23 H_D#39 B7 AD7
H_D#8 D[7]# D[39]# H_D#40 VCC[010] VCC[077]
K24 D[8]# D[40]# Y25 B9 VCC[011] VCC[078] AD9
H_D#9 G24 W22 H_D#41 B10 AD10
H_D#10 D[9]# D[41]# H_D#42 VCC[012] VCC[079]
J24 D[10]# D[42]# Y23 B12 VCC[013] VCC[080] AD12
H_D#11 J23 W24 H_D#43 B14 AD14
H_D#12 D[11]# D[43]# H_D#44 VCC[014] VCC[081]
H22 D[12]# D[44]# W25 B15 VCC[015] VCC[082] AD15
H_D#13 F26 AA23 H_D#45 B17 AD17
H_D#14 D[13]# D[45]# H_D#46 VCC[016] VCC[083]
K22 D[14]# D[46]# AA24 B18 VCC[017] VCC[084] AD18
H_D#15 H23 AB25 H_D#47 B20 AE9
D[15]# D[47]# VCC[018] VCC[085]
<7> H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 <7> C9 VCC[019] VCC[086] AE10
<7> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <7> C10 VCC[020] VCC[087] AE12
<7> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <7> C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49