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5 4 3 2 1
D D
Quanta Project Name: GM7B
C
Dell Project Name: Shatner C
A00(QT) Stage
BOARD REV : F
2010-08
B B
A A
Quanta Computer Inc.
Project Name: GM7B
Title
CoverPage
Size Document Number Rev
GM7B_MB F3A
Date: Monday, September 13, 2010 Sheet 1 of 54
5 4 3 2 1
1 2 3 4 5 6 7 8
System Block Diagram of GM7B REGULATOR
+1.5V_SUS/+0.75V_DDR_VTT
+1.05V_RUN
PG 44
CPU CORE
DC/DC
PG 43
+3.3V_ALW/+5V_ALW/
PG 46 +15V_ALW PG 47
A +1.1V_RUN_VTT VGA / Nivida A
FAN & THERMAL PG 45 PG 48
SMSC1422
PG 31
VGA / Intel
PG 49
CLOCK POWER
SLG8SP585VTR
(QFN-32) +1.8V_RUN
PG 50
PG 3
LVDS
CPU/NB LCD Panel
PCIEx16 NVIDIA N11E-GE
DDR3-SODIMM_A0 PG 28
4 Core 35*35mm HDMI
DDR3-SODIMM_A1
1067/1333 MHz DDR III (Clarksfield) PCI EXPRESS GFX
PG 14,15
DP
[DDR3 x 12 PG 19,20,21,22,23,24
B
DDR3-SODIMM_B1 B
(3G 192bits)]
1067/1333 MHz DDR III
PG 25,26,27
PG 16,17
(989 PGA)
DDR3-SODIMM_B0
PG 4,5,6,7
DP DP Redriver DP conn.
SN75DP120
FDI(ARD) DMI X 4
E-Module Bay HDMI Redriver
SATA[1] HDMI HDMI conn.
ODD PG 35 TMDS141
SATA[0]
SATA - HDD0 PG 35
SATA[5]
SATA - HDD1 PCH LAN
RJ45 conn.
PCIE[6] PCIE[6] RTL8111EL
Bluetooth BTB Conn USB[8] (HM57)
C C
PG 37
SATA[4] DB SATA[4]
eSATA Redriver E-SATA Combo
Conn.
JMicron PCIE[5] USB[1] USB[1] SN75LVCP412 with USB CONN
Card Reader
JMB389
conn USB[1,2,3] PCIE[1,3] PCIE[1]
PG 29
PG 8,9,10,11,12,13 MINI-CARD
PCIE[4] USB[4,5] USB[4]
WLAN
SPI PCIE[3]
USB 2.0 conn USB[1] LPC MINI-CARD Main SPK Amp Main SPK
USB[5]
X1 DB SPI ROM WWAN MAX9736AETJ+ 1.5W*2
Conn. 4M bytes
KBC PG 32
USB 2.0 conn ITE8502 Azalia I/F Azalia I/F AUDIO Codec Subwoofer Amp
19X8 ALC665 SPK 2.5W*1
X1 MAX9736AETJ+
PG 30 Keyboard
PG 36
D
PG 36 D
SPI PS/2 PG 33
Audio Quanta Computer Inc.
USB 2.0 conn FLASH Touchpad Jacks X3 Project Name: GM7B
X1 1Mbyts Title
USER MB Block Diagram
PG 32 PG 33 INTERFACE Size Document Number Rev
GM7B_MB F3A
PG 34
Date: Monday, September 13, 2010 Sheet 2 of 54
1 2 3 4 5 6 7 8
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D D
U25
805 40mil
+3.3V_RUN L26 +3.3V_CLK_VDD 1
BLM21PG600SN1D VDD_USB
5 VDD_LCD CPU-0 23 CLK_BUF_BCLKP 10
17 VDD_SRC CPU-0# 22 CLK_BUF_BCLKN 10
C560 C538 C558 C555 C566 C526 +VDDIO_CLK 24
805 VDD_CPU
29 20
+1.5V_RUN L29
*BLM21PG600SN1D_NC
10U/10V_8 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4
Y5V Y5V Y5V Y5V Y5V Y5V
15
18
VDD_REF
VDD_SRC_IO
VDD_CPU_IO
CK505 CPU-1
CPU-1# 19
9 VSS_SATA
QFN32 DOT96T_LPR 3 CLK_BUF_DREFCLKP 10
Reserve for SLG8SP595VTR 0.1uF near the 2 VSS_USB DOT96C_LPR 4 CLK_BUF_DREFCLKN 10
every power pin. 8 VSS_LCD
12 VSS_SRC SRC-1 13 CLK_BUF_PCIE_3GPLLP 10
21 VSS_CPU SRC-1# 14 CLK_BUF_PCIE_3GPLLN 10
26 VSS_REF
+3.3V_RUN 10
SATA CLK_BUF_DREFSSCLKP 10
SATA# 11 CLK_BUF_DREFSSCLKN 10
C C
R349 10K 16 6 CLK_VGA_27M_R R358 33
CPU_STOP# 27MHz_nonSS CLK_VGA_27M 23
25 7 CLK_VGA_27M_SS_R R357 *33_NC
38 CK_PWRGD_R CK_PWRGD/PD#_3.3 27MHz_SS CLK_VGA_27M_SS 23
CLK_PCH_14M R366 33 CPU_SEL 30
10 CLK_PCH_14M REF_0/CPU_SEL
Place within 0.5" of CLKGEN
Place the 33 ohm XTAL_OUT 27
XTAL_IN XOUT
resistors close to the CK 505 28 XIN
EC_SMBDAT2 31 33
31,37 EC_SMBDAT2 SDATA GND
EC_SMBCLK2 32
31,37 EC_SMBCLK2 SCLK
SLG8SP585VTR
Realtek: 0.1uFx3pcs, 22uFx1pcs
IDT: 0.1uFx2pcs, 10uFx1pcs
Add capacitor pads for improving WWAN.
C568
+3.3V_RUN +VDDIO_CLK
CLK_PCH_14M
L27 BLM21PG600SN1D
*27P/50V_NC R346 *0/J_8_NC 40mil
NPO 805
B
+1.05V_RUN C486 C534 C503 B
10U/10V_8 0.1U/16V_4 0.1U/16V_4
Y2 R344 *0_8_short
XTAL_IN 1 2 XTAL_OUT
Y5V Y5V Y5V
14.318MHZ HP: 10u x2pcs
2
EC_SMBDAT2 EC_SMBCLK2 C573
C574 33P/50V_4 SLG,IDT: +1.05V Place each 0.1uF cap as close as
1
1
C569 C570 33P/50V_4 COH possible to each VDD IO pin. Place
1
*10P_NC *10P_NC COH Realtek: +3.3V the 10uF caps on the VDD_IO plane.
NPO NPO
2
2
50 50
+3.3V_RUN +VDDIO_CLK:
EMI SLG date sheet (V0.2) P15: Min 1.05V,Max3.465V.
Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.
2
R365 IDT date sheet(V0.7) P10: Min 0.9975V,Max 3.465V.
*4.7K_NC
1
CPU_SEL CPU_SEL:
PIN 30 CPU_0 CPU_1 SLG date sheet (V0.2) P15:
2
R364 High Voltage: Min 0.7V, Max 1.5V.
A 4.7K C567 0(default) 133MHz 133MHz Low Voltage: Min Vss-0.3V, Max 0.35V. A
*10P/50V_NC Realtek date sheet(V1.2) P11:
COG
High Voltage: Min 0.7V, Max 1.5V. Quanta Computer Inc.
1
1(0.7V-1.5V) 100MHz 100MHz
EMI Capacitor Low Voltage: Min Vss-0.3V, Max 0.35V.
IDT date sheet(V0.7) P10:
Project Name: GM7B
High Voltage: Min 0.7V, Max 1.5V. Title
CoverPage
Low Voltage: Min Vss-0.3V, Max 0.35V.
Size Document Number Rev
GM7B_MB F3A
Date: Monday, September 13, 2010 Sheet 3 of 54
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5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
U33A
B26 PEG_COMP R411 49.9/F%
1 U33B
PEG_ICOMPI H_COMP3
A26 AT23
PEG_ICOMPO COMP3
8 DMI_TXN0 A24 B27 A16 CLK_CPU_BCLK 11
DMI_RX#[0] PEG_RCOMPO BCLK
MISC
MISC
C23 A25 R410 750/F1% H_COMP2 AT24 B16 CLK_CPU_BCLK# 11
8 DMI_TXN1 DMI_RX#[1] PEG_RBIAS COMP2 BCLK#
8 DMI_TXN2 B22 PCIE_MRX_GTX_N[15..0] 19
D DMI_RX#[2] D
CLOCKS
A21 K35 PCIE_MRX_GTX_N0 H_COMP1 G16 AR30 TP26
8 DMI_TXN3 DMI_RX#[3] PEG_RX#[0] COMP1 BCLK_ITP
J34 PCIE_MRX_GTX_N1 AT30 TP28
PEG_RX#[1] PCIE_MRX_GTX_N2 H_COMP0 BCLK_ITP#
8 DMI_TXP0 B24 J33 AT26
DMI_RX[0] PEG_RX#[2] PCIE_MRX_GTX_N3 COMP0 DPLL_REF_SSCLK and DPLL_REF_SSCLK#
8 DMI_TXP1 D23 G35 E16 CLK_PCIE_3GPLL 10
DMI_RX[1] PEG_RX#[3] PEG_CLK
DMI
B23 G32 PCIE_MRX_GTX_N4 D16 can be GND when discrete.
8 DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_CLK# CLK_PCIE_3GPLL# 10
A22 F34 PCIE_MRX_GTX_N5 30 H_CPUDET# R128 *0_short AH24
8 DMI_TXP3 DMI_RX[3] PEG_RX#[5] SKTOCC#
F31 PCIE_MRX_GTX_N6 A18 CLK_DREFSSCLKP_R R402 0_SW CLK_DREFSSCLKP 10
PEG_RX#[6] PCIE_MRX_GTX_N7 DPLL_REF_SSCLK CLK_DREFSSCLKN_R R405 0_SW
8 DMI_RXN0 D24 DMI_TX#[0] PEG_RX#[7] D35 DPLL_REF_SSCLK# A17 CLK_DREFSSCLKN 10
G24 E33 PCIE_MRX_GTX_N8 31. Change FP H_CATERR# AK14 R409 0_DIS
8 DMI_RXN1 DMI_TX#[1] PEG_RX#[8] CATERR#
THERMAL
THERMAL
F23 C33 PCIE_MRX_GTX_N9 R408 0_DIS
8 DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
H23 D32 PCIE_MRX_GTX_N10
8 DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
B32 PCIE_MRX_GTX_N11 F6 DDR3_DRAMRST#_R S3 Power reduce
PEG_RX#[11] PCIE_MRX_GTX_N12 SM_DRAMRST#
8 DMI_RXP0 D25 C31 11 H_PECI AT15
DMI_TX[0] PEG_RX#[12] PCIE_MRX_GTX_N13 PECI SM_RCOMP_0
8 DMI_RXP1 F24 DMI_TX[1] PEG_RX#[13] B28 SM_RCOMP[0] AL1
E23 B30 PCIE_MRX_GTX_N14 AM1 SM_RCOMP_1 +1.1V_RUN_VTT
8 DMI_RXP2 DMI_TX[2] PEG_RX#[14] SM_RCOMP[1]
G23 A31 PCIE_MRX_GTX_N15 AN1 SM_RCOMP_2
8 DMI_RXP3 DMI_TX[3] PEG_RX#[15] SM_RCOMP[2]
PCIE_MRX_GTX_P[15..0] 19 H_PROCHOT# AN26
PCIE_MRX_GTX_P0 PROCHOT# R140 10K
J35 AN15
PEG_RX[0] PM_EXT_TS#[0]
DDR3
MISC
PCIE_MRX_GTX_P1 R139 10K
PEG_RX[1]
H34
H33 PCIE_MRX_GTX_P2
Set constraint PM_EXT_TS#[1]
AP15
R141 *0_short
PEG_RX[2] PM_EXTTS#0 14,15
E22 F35 PCIE_MRX_GTX_P3 11 H_THERM# H_THERM# AK15 PM_EXTTS#1 16,17
8 FDI_TXN0 FDI_TX#[0] PEG_RX[3] THERMTRIP#
D21 G33 PCIE_MRX_GTX_P4
8 FDI_TXN1 FDI_TX#[1] PEG_RX[4]
D19 E34 PCIE_MRX_GTX_P5
8 FDI_TXN2 FDI_TX#[2] PEG_RX[5]
D18 F32 PCIE_MRX_GTX_P6 AT28 TP31 61 CRB(v0.71) P.11
8 FDI_TXN3 FDI_TX#[3] PEG_RX[6] PRDY#
G21 D34 PCIE_MRX_GTX_P7 AP27 TP6
8 FDI_TXN4 FDI_TX#[4] PEG_RX[7] PREQ#
E19 F33 PCIE_MRX_GTX_P8 R137
PCI EXPRESS -- GRAPHICS
8 FDI_TXN5 FDI_TX#[5] PEG_RX[8]
F21 B33 PCIE_MRX_GTX_P9 AN28 TP25 *12.4K/F_NC
8 FDI_TXN6 FDI_TX#[6] PEG_RX[9] TCK
Intel(R) FDI
G18 D31 PCIE_MRX_GTX_P10 H_CPURST# AP26 AP28 TP29
8 FDI_TXN7 FDI_TX#[7] PEG_RX[10] RESET_OBS# TMS
PWR MANAGEMENT
PWR MANAGEMENT
A32 PCIE_MRX_GTX_P11 AT27 XDP_TRST# R423 51
PEG_RX[11] TRST#