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5 4 3 2 1
D Main Board Power D
030. KBC_IT8512 060. DC_DC & BAT IN 080. PWR_VCORE
001. Page Ref. 031. KBC_KB CON 061. BT_BLUETOOTH 081. PWR_SYSTEM
002. Block Diagram 032. KBC_RESET MAP 062. TPM_****** 082. POWER_I/O_+1.05VO
003. Schematic Information 033. LAN_RTL8111C 063. FP_****** 083. PWR_I/O_DDR & VTT
004. CPU_Silverthorne (1) 034. LAN_RJ45 064. TUN_****** 084. PWR_I/O_POWER_I/O_ +1.5V_+2.5VS
005. CPU_Silverthorne (2) 035. LAN_****** 065. ME_NUT & SCREW HOLE 085. POWER_+1.05VO & +1.5VO
006. CPU_****** 036. AUD_IC CON 066. ESA_SATA JMB360 086. POWER_+MCP_VDD_CORE(Empty)
007. DIM_SO-DIMM 0 037. AUD_****** 067. SDVO_CH7317 087. PWR_SHUTDOWN# (Empty))
008. DIM_****** 038. AUD_****** 068. OTH_POWER ON CIRCUIT 088. PWR_CHARGER
C
009. DIM_DDR2 Terminatin 039. AUD_****** 069. OTH_****** 089. PWR_PIC(Empty) C
010. SCH_Poulsbo_HOST 040. CB_****** 070. VGA_****** 090. PWR_DETECT
011. SCH_Poulsbo_DDR2 041. CB_****** 071. VGA_****** 091. PWR_LOAD SWITCH
012. SCH_Poulsbo_LVDS/SDVO 042. CB_AU6371 072. VGA_****** 092. PWR_PROTECT
013. SCH_Poulsbo_PM/USB/AZ 043. CB_****** 073. VGA_****** 093. PWR_SIGNAL
014. SCH_Poulsbo_POWER 044. BUG_LPC DEBUG 074. VGA_****** 094. POWER_FLOWCHART
015. SCH_Poulsbo_GND 045. CRT_LVDS 075. VGA_****** 095. PWR_LED_VCC_BOOST
016. SCH_****** 046. CRT_D-SUB 076. VGA_****** 096. HISTORY
017. SCH_****** 047. CRT_****** 077. VGA_****** 097. POWER ON SEQUENCE
018. SCH_****** 048. CRT_****** 078. VGA_******
B 019. SCH_****** 049. TV_****** 079. VGA_****** B
020. SCH_****** 050. FAN_SENSOR & FAN
021. SCH_****** 051. XDD_HDD CON
022. SCH_****** 052. USB_USB Port *2
023. SCH_****** 053. PCI_MINICARD
024. SCH_****** 054. BAR_******
025. SCH_****** 055. SIO_****** Revision History
026. SCH_****** 056. LED_LED & SW
027. SCH_****** 057. DSG_DISCHARGE
028. SCH_****** 058. SUB_******
A 029. CLK_ICS9LPRS427 059. SEQ_****** A
Title : Page Ref.
ASUSTeK COMPUTER INC. NB1 Engineer:
Size Project Name Rev
Custom S121 2.0
Date: Friday, December 05, 2008 Sheet 1 of 97
5 4 3 2 1
5 4 3 2 1
UX20 Block Diagram
(Silverthorne / Poulsbo) CPU
Clock Generator
Silverthorne
ICS ICS9LPRS427
D D
Page 4~5 Page 29
FSB 533MHz
LVDS
Page 45
DDR2
CRT DDR-II So-DIMM
Page 7~9
Page 46
SCH
POULSBO
Small-Board GigaLAN
RJ-45
Realtek RTL8111C
Azalia Codec Azalia Page 33 Page 34
Realterk ALC663
LPC PCIE X1 SATA Controller SATA
C
Page 98
HDD/SSD POWER C
JMB360
Page 10~15
Page 66 Page 51 VCORE Page 80
INT MIC Audio Amp. Jack
Page 100 Page 99 Page 99
SYSTEM Page 81
Small-Board Cardreader Switch LED
Alcor AU6371 Page 56 Page 56 1.5VS,1.05VS 82
Page 42 Page
Touch-Pad PS2
Bluetooth DDR&VTT Page 83
EC
SPI Page 61
BIOS ROM +1.25VS&2.5VS
ITE IT8512E Page 84
Page 30
USB 2.0 CMOS Camera
B Keyboard Page 30
CHARGER Page 88 B
Page 45
Page 31
DETECT Page 90
Debug port USB Port *2
Page 44 Page 52 LOAD SWITCH 91
Page
USB Port *1 PROTECT Page 92
Small-Board
POWER SIGNAL 93
Page
FLOWCHART Page 94
PWM FAN Power on circuit Screw Holes
Page 50 Page 68 Page 65 TFT-LED DRIVE
Page 95
A A
Thermal Sensor Battery Conn.
Page 50 Page 60
Discharge DC Conn. Title : Block Diagram
ASUSTeK COMPUTER INC. NB1 Engineer:
Page 57 Page 60
Size Project Name Rev
Custom S121 2.0
Date: Friday, December 05, 2008 Sheet 2 of 97
5 4 3 2 1
5 4 3 2 1
Poulsbo GPIO SETTING EC IT8512E GPIO SETTING
Name Signal Name Type Name Signal Name Type Name Signal Name Type
GPIOSUS0 RTLAN_DSM# GPI A0 PWR_LED# GPO G0 PM_THERM# GPO
GPIOSUS1 RTLAN_DSM_EN GPO A1 CHG_LED# GPO G1 PM_SUSB# GPI
GPIOSUS2 PM_PWRBTN# GPI A2 **** NC G2 **** NC
D D
GPIOSUS3 **** TP A3 MARATHON_LED# GPO G6 **** NC
GPIO0 WLAN_LED_ON GPO A4 LCD_BL_PWM GPO H0 PM_CLKRUN# GPIO
GPIO1 PCB_ID0 GPI A5 FAN0_PWM GPO H1 WLAN_ON# GPO
GPIO2 PCB_ID1 GPI A6 EC_RSTWRN GPO H2 **** NC
GPIO3 CLK_OC GPO A7 PM_RSTRDY# GPI H3 BAT_LEARN GPO
GPIO4 VCORE_CNT GPO B0 RST# GPO H4 DDR2_VOL_1 GPO
GPIO5 OC_CTL# GPO B1 SCH_RST#_R GPO H5 NUM_LED# GPO
GPIO6 DDR_MEM_CONFIG GPI B2 PM_SLPMODE GPI H6 CAP_LED# GPO
GPIO7 SLPIOVR# GPO B3 SMB0_CLK GPIO I0 **** NC
GPIO8 H_PROCHOT# GPO B4 SMB0_DAT GPIO I1 SUS_PWRGD GPI
GPIO9 **** TP B5 A20GATE GPO I2 ALL_SYSTEM_PWRGD GPI
B6 RC_IN# GPO I3 VRM_PWRGD GPI
B7 PM_RSMRST# GPO I4 **** NC
C0 VOL_SEL GPO I5 **** NC
C1 SMB1_CLK GPIO I6 **** NC
C C
C2 SMB1_DAT GPIO I7 **** NC
C3 PM_PWRBTN# GPO J0 EC_CLK_EN GPO
C4 AC_IN_OC# GPI J1 PM_PWROK GPO
C5 OP_SD# GPO J2 VSET_EC GPO
C6 BAT1_IN_OC# GPI J3 ISET_EC GPO
C7 RFON_SW# GPI J4 EXTTSO# GPO
D0 **** NC J5 FB GPO
D1 PM_SUSC# GPI
D2 BUF_RST# GPI
D3 EXT_SCI# GPO
D4 EXT_SMI# GPO
D5 LCD_BACKOFF# GPO
D6 FAN0_TACH GPI
D7 SD_CD_EC# GPO
E0 VSUS_ON GPO
B E1 SUSC_EC# GPO B
E2 SUSB_EC# GPO
E3 CPU_VRON GPO
E4 PWR_SW# GPI
E5 DDR2_VOL_0 GPO
E6 LID_SW# GPI
E7 MARATHON# GPO
F0 CRT_2.5V_PWR# GPO
F1 CRT_RST GPO
F2 CRT_IN# GPI
F3 SATA_RST# GPO
F4 TP_CLK GPIO
F5 TP_DAT GPIO
F6 THRO_CPU GPO
F7 BT_ON# GPO
A A
Title : Schematic Information
ASUSTeK COMPUTER INC. NB1 Engineer:
Size Project Name Rev
Custom S121 2.0
Date: Friday, December 05, 2008 Sheet 3 of 97
5 4 3 2 1
5 4 3 2 1
H_D#[63:0]
Place on TOP side T0415 TPC26T 1 H_TDI Jesse H_D#[63:0] 10
H_TDI 13
T0416 TPC26T 1 H_TDO
H_TDO 13
T0417 TPC26T 1 H_TMS U0401B
H_TMS 13
T0402 TPC26T 1 H_ADS# T0418 TPC26T 1 H_TRST# H_D#0 Y27 AE8 H_D#32
H_TRST# 13 D[0]# D[32]#
H_D#1 AH27 AD7 H_D#33
T0403 TPC26T H_CPURST_R# H_D#2 D[1]# D[33]# H_D#34
1 Y31 D[2]# D[34]# AH15
T0419 TPC26T 1 XDP_TCK_1 H_D#3 AC30 AF9 H_D#35
XDP_TCK_1 13 D[3]# D[35]#
T0420 TPC26T 1 H_TCK H_D#4 AE30 AH9 H_D#36
H_D#5 D[4]# D[36]# H_D#37
AF29 D[5]# D[37]# AE10
DATA GRP 0
H_D#6 H_D#38
DATA GRP 2
Intel Update need PU 0625 AA26 D[6]# D[38]# AJ16
U0401A H_D#7 AB31 AF13 H_D#39
10 H_A#[31..3] D[7]# D[39]#
H_A#3 E22 C26 H_D#8 W30 AF7 H_D#40
A[3]# ADS# H_ADS# 10 D[8]# D[40]#
D H_A#4 A22 H25 H_D#9 AC28 AF15 H_D#41 D
A[4]# BNR# H_BNR# 10 +VCCP1.05_CPU_C6_OFF D[9]# D[41]#
H_A#5 D21 G24 H_D#10 AD31 AH13 H_D#42
A[5]# BPRI# H_BPRI# 10 D[10]# D[42]#
H_A#6 E24 H_D#11 AF27 AJ14 H_D#43
H_A#7 A[6]# R0402 H_D#12 D[11]# D[43]# H_D#44
B17 A[7]# DEFER# B27 H_DEFER# 10 AD27 D[12]# D[44]# AJ12
H_A#8 A18 W28 H_INIT# 1 1KOhm 2 1% H_D#13 AG28 AH7 H_D#45
A[8]# DRDY# H_DRDY# 10 D[13]# D[45]#
H_A#9 B23 D29 H_D#14 AB25 AJ8 H_D#46
A[9]# DBSY# H_DBSY# 10 D[14]# D[46]#
0
0
ADDR GROUP
H_A#10 A16 H_D#15 AC26 AJ10 H_D#47
H_A#11 A[10]# D[15]# D[47]#
E18 A[11]# BR0# C28 H_BR0# 10 10 H_DSTBN#0 AA28 DSTBN[0]# DSTBN[2]# AH11 H_DSTBN#2 10
H_A#12 D15 AA30 AF11
A[12]# 10 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 10
H_A#13 H_IERR#
CONTROL
B19 H1 R0403 1 1KOhm 2 1% AE28 AE12
A[13]# IERR# +V1.05S_VTT_CPU 10 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 10
H_A#14 A20 F31
A[14]# INIT# H_INIT# 10,30
H_A#15
H_A#16
D17
B15
A[15]#
D25
Johnny H_D#16 AE24 AH5 H_D#48
A[16]# LOCK# H_LOCK# 10 D[16]# D[48]#
D19 H_D#17 AC24 AB5 H_D#49
10 H_ADSTB#0 ADSTB[0]# +V1.05S_VTT_CPU D[17]# D[49]#
M5 H_CPURST_R# R0404 1 56OHM 2 H_D#18 AJ20 AJ6 H_D#50
10 H_REQ#[4..0] RESET# H_CPURST# 10 D[18]# D[50]#
H_REQ#0 B25 D27 H_RS#0 H_RS#0 10 H_D#19 AE20 Y1 H_D#51
H_REQ#1 REQ[0]# RS[0]# H_RS#1 R0437 @ H_D#20 D[19]# D[51]# H_D#52
D23 REQ[1]# RS[1]# E28 H_RS#1 10 AJ22 D[20]# D[52]# AF5
H_REQ#2 E20 E26 H_RS#2 H_RS#2 10 H_CPURST# 1 56OHM 2 H_D#21 AF25 AG4 H_D#53
H_REQ#3 REQ[2]# RS[2]# H_D#22 D[21]# D[53]# H_D#54
A24 REQ[3]# TRDY# F25 H_TRDY# 10 AH25 D[22]# D[54]# AF3
H_REQ#4 B21 PR 0409 H_D#23 AH23 AC6 H_D#55
REQ[4]# D[23]# D[55]#
DATA GRP 1
H_D#24 H_D#56
DATA GRP 3
HIT# E30 H_HIT# 10 1 TPC26T T0428 AH19 D[24]# D[56]# AE6
H_A#17 B5 F29 H_HITM# 10 H_D#25 AF23 AE4 H_D#57
H_A#18 A[17]# HITM# +3VS H_D#26 D[25]# D[57]# H_D#58
A12 A[18]# AE18 D[26]# D[58]# W4
H_A#19 D5 F1 BPM#0 T0404 R0438 H_D#27 AH17 AC2 H_D#59
H_A#20 A[19]# BPM[0]# BPM#1 T0406 1KOhm @ H_D#28 D[27]# D[59]# H_D#60
E12 A[20]# BPM[1]# E2 AD19 D[28]# D[60]# AE2
H_A#21 B9 F5 BPM#2 T0405 XDP_DBRESET# 2 1 H_D#29 AJ24 AD1 H_D#61
A[21]# BPM[2]# D[29]# D[61]#
ADDR GROUP 1
ADDR GROUP 1
H_A#22 A6 D3 BPM#3 T0407 H_D#30 AJ18 AA2 H_D#62
H_A#23 A[22]# BPM[3]# BPM#4 T0408 H_D#31 D[30]# D[62]# H_D#63
XDP/ITP SIGNALS
B13 A[23]# PRDY# E4 AF19 D[31]# D[63]# AC4
C H_A#24 E14 F7 BPM#5 R0406 1 56OHM 2 AF21 AB1 C
A[24]# PREQ# +VCCP1.05_CPU_C6_OFF 10 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 10
H_A#25 A10 L2 H_TCK R0405 1 56OHM 2 AH21 AA4
A[25]# TCK GND 10 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 10
H_A#26 B7 N2 H_TDI R0408 1 56OHM 2 AE22 Y5
A[26]# TDI +V1.05S_VTT_CPU 10 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 10
H_A#27 D13 M1 H_TDO R0407 1 56OHM 2
H_A#28 A[27]# TDO H_TMS GTL_REF
A8 A[28]# TMS P1 R0410 1 56OHM 2 AJ26 GTLREF COMP[0] AE14 H_COMP0 R0411 1 2 27.4OHM 1%
H_A#29 H_TRST# R0409 56OHM AD13 H_COMP1 R0413 1 54.9Ohm 1%
H_A#30
C4
A14
A[29]# TRST# J4
G26 XDP_DBRESET#
1 2 Johnny COMP[1]
E16 H_COMP2 R0412 1
2
2 27.4OHM 1%
A[30]# RSVD14 MISC COMP[2]
H_A#31 B11 A[31]# Res for H_TDO mount R0414 @
COMP[3] F15 H_COMP3 R0415 1 2 54.9Ohm 1%
D11 H5 H_PROCHOT# 1KOhm 1% 2 1CPU_TEST1 P31
10 H_ADSTB#1 ADSTB[1]# PROCHOT# TEST1
THRMDA T5 CPU_THRM_DA 50
1KOhm 1% 2 1CPU_TEST2 T31 TEST2 DPRSTP# G2 H_DPRSTP# 10,80
THERM
G30 U4 R0416 @ G6
30 H_A20M# A20M# THRMDC CPU_THRM_DC 50 DPSLP# H_DPSLP# 10
J28 V31 GND
10 H_PBE# FERR# DPWR# H_DPWR# 10
H_IGNNE# H27 T1 GND 1CPU_BSEL0 R30 G4
IGNNE# THERMTRIP# PM_THRMTRIP# 10,30,68 T0409 TPC26T BSEL[0] PWRGOOD H_PWRGD 10
29 CPU_BSEL1 M31 BSEL[1] SLP# J2 H_CPUSLP# 10
K1 U28 K27 CPU_RSVD12
10 H_STPCLK# STPCLK# 29 CPU_BSEL2 BSEL[2] RSVD12 T0427
HCLK
10 H_INTR H31
L28
LINT0
P29 INT441 Jesse 0606
10 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 29
10 H_SMI# J26 SMI# BCLK[1] R28 CLK_CPU_BCLK# 29
AE16
AF17
RSVD7
K31 CPU_VSS0 1 2 R0440 @ Johnny Layout Note
RSVD8 VSS0
+VCCP1.05_CPU_C6_OFF
AD15 RSVD9
0Ohm Notice Intel's update COMP 0 2 connect with Z0=27.4 ohm,L<0.5"
AD17 RSVD10