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ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 8-Bit mP Compatible A D Converters

December 1994

ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 8-Bit mP Compatible A D Converters
General Description
The ADC0801 ADC0802 ADC0803 ADC0804 and ADC0805 are CMOS 8-bit successive approximation A D converters that use a differential potentiometric ladder similar to the 256R products These converters are designed to allow operation with the NSC800 and INS8080A derivative control bus with TRI-STATE output latches directly driving the data bus These A Ds appear like memory locations or I O ports to the microprocessor and no interfacing logic is needed Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input voltage value In addition the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution
Y Y

Y Y Y

Y Y Y Y

Differential analog voltage inputs Logic inputs and outputs meet both MOS and TTL voltage level specifications Works with 2 5V (LM336) voltage reference On-chip clock generator 0V to 5V analog input voltage range with single 5V supply No zero adjust required 0 3 standard width 20-pin DIP package 20-pin molded chip carrier or small outline package Operates ratiometrically or with 5 VDC 2 5 VDC or analog span adjusted voltage reference

Key Specifications
Y Y Y

Features
Y Y

Compatible with 8080 mP derivatives no interfacing logic needed - access time - 135 ns Easy interface to all microprocessors or operates ``stand alone''

Resolution Total error Conversion time

g

LSB g

8 bits LSB and g 1 LSB 100 ms

Typical Applications

TL H 5671 ­ 1

8080 Interface

Error Specification (Includes Full-Scale Zero Error and Non-Linearity) Part Number FullVREF 2 e 2 500 VDC VREF 2 e No Connection Scale (No Adjustments) (No Adjustments) Adjusted LSB
g

ADC0801 g ADC0802 ADC0803 g ADC0804 ADC0805
TL H 5671­31
TRI-STATE is a registered trademark of National Semiconductor Corp Z-80 is a registered trademark of Zilog Corp C1995 National Semiconductor Corporation

LSB

LSB
g 1 LSB g 1 LSB

TL H 5671

RRD-B30M115 Printed in U S A

Absolute Maximum Ratings

(Notes 1

2) Storage Temperature Range Package Dissipation at TA e 25 C ESD Susceptibility (Note 10)
b 65 C to a 150 C

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) (Note 3) 6 5V Voltage b 0 3V to a 18V Logic Control Inputs b 0 3V to (VCC a 0 3V) At Other Input and Outputs Lead Temp (Soldering 10 seconds) Dual-In-Line Package (plastic) 260 C Dual-In-Line Package (ceramic) 300 C Surface Mount Package Vapor Phase (60 seconds) Infrared (15 seconds) 215 C 220 C

875 mW 800V

Operating Ratings (Notes 1 2) Temperature Range TMINsTAsTMAX ADC0801 02LJ ADC0802LJ 883 b55 CsTAs a 125 C b 40 C s TA s a 85 C ADC0801 02 03 04LCJ b 40 C s TA s a 85 C ADC0801 02 03 05LCN ADC0804LCN 0 CsTAs a 70 C ADC0802 03 04LCV 0 CsTAs a 70 C ADC0802 03 04LCWM 0 CsTAs a 70 C Range of VCC 4 5 VDC to 6 3 VDC

Electrical Characteristics
The following specifications apply for VCC e 5 VDC TMINsTAsTMAX and fCLK e 640 kHz unless otherwise specified Parameter ADC0801 Total Adjusted Error (Note 8) ADC0802 Total Unadjusted Error (Note 8) ADC0803 Total Adjusted Error (Note 8) ADC0804 Total Unadjusted Error (Note 8) ADC0805 Total Unadjusted Error (Note 8) VREF 2 Input Resistance (Pin 9) Analog Input Voltage Range DC Common-Mode Error Power Supply Sensitivity Conditions With Full-Scale Adj (See Section 2 5 2) VREF 2 e 2 500 VDC With Full-Scale Adj (See Section 2 5 2) VREF 2 e 2 500 VDC VREF 2-No Connection ADC0801 02 03 05 ADC0804 (Note 9) (Note 4) V( a ) or V(b) Over Analog Input Voltage Range VCC e 5 VDC g 10% Over Allowed VIN( a ) and VIN(b) Voltage Range (Note 4) 25 0 75 Gnd ­ 0 05
g

Min

Typ

Max
g g g g1 g1

Units LSB LSB LSB LSB LSB kX kX

80 11 VCC a 0 05
g

VDC LSB LSB

g

g

AC Electrical Characteristics
The following specifications apply for VCC e 5 VDC and TA e 25 C unless otherwise specified Symbol TC TC fCLK CR tW(WR)L tACC t1H t0H Parameter Conversion Time Conversion Time Clock Frequency Clock Duty Cycle Conversion Rate in Free-Running Mode Width of WR Input (Start Pulse Width) Access Time (Delay from Falling Edge of RD to Output Data Valid) TRI-STATE Control (Delay from Rising Edge of RD to Hi-Z State) Delay from Falling Edge of WR or RD to Reset of INTR Input Capacitance of Logic Control Inputs TRI-STATE Output Capacitance (Data Buffers) Logical ``1'' Input Voltage (Except Pin 4 CLK IN) VCC e 5 25 VDC 20 Conditions fCLK e 640 kHz (Note 6) (Note 5 6) VCC e 5V (Note 5) (Note 5) INTR tied to WR with CS e 0 VDC fCLK e 640 kHz CS e 0 VDC (Note 7) CL e 100 pF CL e 10 pF RL e 10k (See TRI-STATE Test Circuits) Min 103 66 100 40 8770 100 135 125 200 200 640 Typ Max 114 73 1460 60 9708 Units ms 1 fCLK kHz % conv s ns ns ns

tWI tRI CIN COUT

300 5 5

450 75 75

ns pF pF

CONTROL INPUTS Note CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately VIN (1) 15 VDC

2

AC Electrical Characteristics (Continued) The following specifications apply for VCC e 5VDC and TMIN s TA s TMAX unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units CONTROL INPUTS Note CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately VIN (0) IIN (1) IIN (0) Logical ``0'' Input Voltage (Except Pin 4 CLK IN) Logical ``1'' Input Current (All Inputs) Logical ``0'' Input Current (All Inputs) VCC e 4 75 VDC VIN e 5 VDC VIN e 0 VDC
b1

08 0 005
b 0 005

VDC mADC mADC

1

CLOCK IN AND CLOCK R VT a VTb VH VOUT (0) VOUT (1) CLK IN (Pin 4) Positive Going Threshold Voltage CLK IN (Pin 4) Negative Going Threshold Voltage CLK IN (Pin 4) Hysteresis (VT a )b(VTb) Logical ``0'' CLK R Output Voltage Logical ``1'' CLK R Output Voltage IO e 360 mA VCC e 4 75 VDC IO eb360 mA VCC e 4 75 VDC 24 27 15 06 31 18 13 35 21 20 04 VDC VDC VDC VDC VDC

DATA OUTPUTS AND INTR VOUT (0) Logical ``0'' Output Voltage Data Outputs INTR Output Logical ``1'' Output Voltage Logical ``1'' Output Voltage TRI-STATE Disabled Output Leakage (All Data Buffers) IOUT e 1 6 mA VCC e 4 75 VDC IOUT e 1 0 mA VCC e 4 75 VDC IO eb360 mA VCC e 4 75 VDC IO eb10 mA VCC e 4 75 VDC VOUT e 0 VDC VOUT e 5 VDC VOUT Short to Gnd TA e 25 C VOUT Short to VCC TA e 25 C Supply Current (Includes Ladder Current) ADC0801 02 03 04LCJ 05 ADC0804LCN LCV LCWM fCLK e 640 kHz VREF 2 e NC TA e 25 C and CS e 5V 11 19 18 25 mA mA 24 45
b3

04 04

VDC VDC VDC VDC mADC mADC mADC mADC

VOUT (1) VOUT (1) IOUT ISOURCE ISINK

3 45 90 6 16

POWER SUPPLY ICC

Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to Gnd unless otherwise specified The separate A Gnd point should always be wired to the D Gnd Note 3 A zener diode exists internally from VCC to Gnd and has a typical breakdown voltage of 7 VDC Note 4 For VIN( b ) t VIN( a ) the digital output code will be 0000 0000 Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply Be careful during testing at low VCC levels (4 5V) as high level analog inputs (5V) can cause this input diode to conduct­especially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4 950 VDC over temperature variations initial tolerance and loading Note 5 Accuracy is guaranteed at fCLK e 640 kHz At higher clock frequencies accuracy can degrade For lower clock frequencies the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns Note 6 With an asynchronous start pulse up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process The start request is internally latched see Figure 2 and section 2 0 Note 7 The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams) Note 8 None of these A Ds requires a zero adjust (see section 2 5 1) To obtain zero code at other analog input voltages see section 2 5 and Figure 5 Note 9 The VREF 2 pin is the center point of a two-resistor divider connected from VCC to ground In all versions of the ADC0801 ADC0802 ADC0803 and ADC0805 and in the ADC0804LCJ each resistor is typically 16 kX In all versions of the ADC0804 except the ADC0804LCJ each resistor is typically 2 2 kX Note 10 Human body model 100 pF discharged through a 1 5 kX resistor

3

Typical Performance Characteristics

Logic Input Threshold Voltage vs Supply Voltage

Delay From Falling Edge of RD to Output Data Valid vs Load Capacitance

CLK IN Schmitt Trip Levels vs Supply Voltage

fCLK vs Clock Capacitor

Full-Scale Error vs Conversion Time

Effect of Unadjusted Offset Error vs VREF 2 Voltage

Output Current vs Temperature

Power Supply Current vs Temperature (Note 9)

Linearity Error at Low VREF 2 Voltages

TL H 5671 ­ 2

4

TRI-STATE Test Circuits and Waveforms
t1H t1H CL e 10 pF t0H t0H CL e 10 pF

tr e 20 ns

tr e 20 ns

TL H 5671 ­ 3

Timing Diagrams (All timing is measured from the 50% voltage points)

Output Enable and Reset INTR

Note Read strobe must occur 8 clock periods (8 fCLK) after assertion of interrupt to guarantee reset of INTR

TL H 5671 ­ 4

5

Typical Applications (Continued)
6800 Interface Ratiometric with Full-Scale Adjust

Note before using caps at VIN or VREF 2 see section 2 3 2 Input Bypass Capacitors

Absolute with a 2 500V Reference

Absolute with a 5V Reference

For low power see also LM385-2 5

Zero-Shift and Span Adjust 2VsVINs5V

Span Adjust 0VsVINs3V

TL H 5671 ­ 5

6

Typical Applications (Continued)
Directly Converting a Low-Level Signal A mP Interfaced Comparator

For VIN( a ) l VIN( b ) Output e FFHEX VREF 2 e 256 mV For VIN( a ) k VIN( b ) Output e 00HEX

1 mV Resolution with mP Controlled Range
VREF 2 e 128 mV 1 LSB e 1 mV VDAC s VIN s (VDAC a 256 mV)

Digitizing a Current Flow

TL H 5671 ­ 6

7

Typical Applications (Continued)
Self-Clocking Multiple A Ds External Clocking

100 kHz s fCLK s 1460 kHz

Use a large R value to reduce loading at CLK R output

Self-Clocking in Free-Running Mode

mP Interface for Free-Running A D

After power-up a momentary grounding of the WR input is needed to guarantee operation

Operating with ``Automotive'' Ratiometric Transducers Ratiometric with VREF 2 Forced

VIN( b ) e 0 15 VCC 15% of VCC s VXDR s 85% of VCC
TL H 5671 ­ 7

8

Typical Applications (Continued)
mP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis)

See Figure 5 to select R value DB7 e ``1'' for VIN( a ) l VIN( b ) a (VREF 2) Omit circuitry within the dotted area if hysteresis is not needed

Handling g 10V Analog Inputs

Low-Cost mP Interfaced Temperature-to-Digital Converter

Beckman Instruments

694-3-R10K resistor array

mP Interfaced Temperature-to-Digital Converter

Circuit values shown are for 0 C s TA s a 128 C Can calibrate each sensor to allow easy replacement then A D can be calibrated with a pre-set input voltage

TL H 5671 ­ 8

9

Typical Applications (Continued)
Handling g 5V Analog Inputs Read-Only Interface

TL H 5671­33

TL H 5671 ­ 34

Beckman Instruments

694-3-R10K resistor array

mP Interfaced Comparator with Hysteresis

Protecting the Input

Diodes are 1N914
TL H 5671 ­ 9

A Low-Cost 3-Decade Logarithmic Converter

TL H 5671­35

Analog Self-Test for a System

TL H 5671­36

LM389 transistors A B C D e LM324A quad op amp

TL H 5671 ­ 37

10

Typical Applications (Continued)
3-Decade Logarithmic A D Converter

Noise Filtering the Analog Input

Multiplexing Differential Inputs

fC e 20 Hz Uses Chebyshev implementation for steeper roll-off unity-gain 2nd order low-pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used

Output Buffers with A D Data Enabled

Increasing Bus Drive and or Reducing Time on Bus

TL H 5671 ­ 10

A D output data is updated 1 CLK period prior to assertion of INTR

Allows output data to set-up at falling edge of CS

11

Typical Applications (Continued)
Sampling an AC Input Signal

Note 1 Oversample whenever possible keep fs l 2f( b 60) to eliminate input frequency folding (aliasing) and to allow for the skirt response of the filter Note 2 Consider the amplitude errors which are introduced within the passband of the filter

70% Power Savings by Clock Gating

(Complete shutdown takes

30 seconds )

Power Savings by A D and VREF Shutdown

TL H 5671 ­ 11

Use ADC0801 02 03 or 05 for lowest power consumption Note Logic inputs can be driven to VCC with A D supply at zero volts Buffer prevents data bus from overdriving output of A D when in shutdown mode

12

Functional Description
1 0 UNDERSTANDING A D ERROR SPECS A perfect A D transfer characteristic (staircase waveform) is shown in Figure 1a The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB (19 53 mV with 2 5V tied to the VREF 2 pin) The digital output codes that correspond to these inputs are shown as Db1 D and D a 1 For the perfect A D not only will centervalue (Ab1 A A a 1 ) analog inputs produce the correct output ditigal codes but also each riser (the transitions between adjacent output codes) will be located g LSB away from each center-value As shown the risers are ideal and have no width Correct digital output codes will be provided for a range of analog input voltages that extend g LSB from the ideal center-values Each tread (the range of analog input voltage that provides the same digital output code) is therefore 1 LSB wide

Figure 1b shows a worst case error plot for the ADC0801 All center-valued inputs are guaranteed to produce the correct output codes and the adjacent risers are guaranteed to be no closer to the center-value points than g LSB In
Transfer Function

other words if we apply an analog input equal to the centervalue g LSB we guarantee that the A D will produce the correct digital code The maximum range of the position of the code transition is indicated by the horizontal arrow and it is guaranteed to be no more than LSB The error curve of Figure 1c shows a worst case error plot for the ADC0802 Here we guarantee that if we apply an analog input equal to the LSB analog voltage center-value the A D will produce the correct digital code Next to each transfer function is shown the corresponding error plot Many people may be more familiar with error plots than transfer functions The analog input voltage to the A D is provided by either a linear ramp or by the discrete output steps of a high resolution DAC Notice that the error is continuously displayed and includes the quantization uncertainty of the A D For example the error at point 1 of Figure 1a is a LSB because the digital code appeared LSB in advance of the center-value of the tread The error plots always have a constant negative slope and the abrupt upside steps are always 1 LSB in magnitude Error Plot

a) Accuracy e g 0 LSB A Perfect A D Transfer Function Error Plot

b) Accuracy e g Transfer Function

LSB Error Plot

c) Accuracy e g

LSB

TL H 5671 ­ 12

FIGURE 1 Clarifying the Error Specs of an A D Converter 13

Functional Description (Continued)
2 0 FUNCTIONAL DESCRIPTION The ADC0801 series contains a circuit equivalent of the 256R network Analog switches are sequenced by successive approximation logic to match the analog difference input voltage VIN( a ) b VIN(b) to a corresponding tap on the R network The most significant bit is tested first and after 8 comparisons (64 clock cycles) a digital 8-bit binary code (1111 1111 e full-scale) is transferred to an output latch and then an interrupt is asserted (INTR makes a highto-low transition) A conversion in process can be interrupted by issuing a second start command The device may be operated in the free-running mode by connecting INTR to the WR input with CS e 0 To ensure start-up under all possible conditions an external WR pulse is required during the first power-up cycle On the high-to-low transition of the WR input the internal SAR latches and the shift register stages are reset As long as the CS input and WR input remain low the A D will remain in a reset state Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a low-tohigh transition

A functional diagram of the A D converter is shown in Figure 2 All of the package pinouts are shown and the major logic control paths are drawn in heavier weight lines The converter is started by having CS and WR simultaneously low This sets the start flip-flop (F F) and the resulting ``1'' level resets the 8-bit shift register resets the Interrupt (INTR) F F and inputs a ``1'' to the D flop F F1 which is at the input end of the 8-bit shift register Internal clock signals then transfer this ``1'' to the Q output of F F1 The AND gate G1 combines this ``1'' output with a clock signal to provide a reset signal to the start F F If the set signal is no longer present (either WR or CS is a ``1'') the start F F is reset and the 8-bit shift register then can have the ``1'' clocked in which starts the conversion process If the set signal were to still be present this reset pulse would have no effect (both outputs of the start F F would momentarily be at a ``1'' level) and the 8-bit shift register would continue to be held in the reset mode This logic therefore allows for wide CS and WR signals and the converter will start after at least one of these signals returns high and the internal clocks again provide a reset signal for the start F F

TL H 5671 ­ 13

Note 1 CS shown twice for clarity Note 2 SAR e Successive Approximation Register

FIGURE 2 Block Diagram

14

Functional Description (Continued)
After the ``1'' is clocked through the 8-bit shift register (which completes the SAR search) it appears as the input to the D-type latch LATCH 1 As soon as this ``1'' is output from the shift register the AND gate G2 causes the new digital word to transfer to the TRI-STATE output latches When LATCH 1 is subsequently enabled the Q output makes a high-to-low transition which causes the INTR F F to set An inverting buffer then supplies the INTR input signal Note that this SET control of the INTR F F remains low for 8 of the external clock periods (as the internal clocks run at of the frequency of the external clock) If the data output is continuously enabled (CS and RD both held low) the INTR output will still signal the end of conversion (by a highto-low transition) because the SET input can control the Q output of the INTR F F even though the RESET input is constantly at a ``1'' level in this operating mode This INTR output will therefore stay low for the duration of the SET signal which is 8 periods of the external clock frequency (assuming the A D is not started during this interval) When operating in the free-running or continuous conversion mode (INTR pin tied to WR and CS wired low see also section 2 8) the START F F is SET by the high-to-low transition of the INTR signal This resets the SHIFT REGISTER which causes the input to the D-type latch LATCH 1 to go low As the latch enable input is still present the Q output will go high which then allows the INTR F F to be RESET This reduces the width of the resulting INTR output pulse to only a few propagation delays (approximately 300 ns) When data is to be read the combination of both CS and RD being low will cause the INTR F F to be reset and the TRI-STATE output latches will be enabled to provide the 8bit digital outputs 2 1 Digital Control Inputs The digital control inputs (CS RD and WR) meet standard T2L logic voltage levels These signals have been renamed when compared to the standard A D Start and Output Enable labels In addition these inputs are active low to allow an easy interface to microprocessor control busses For non-microprocessor based applications the CS input (pin 1) can be grounded and the standard A D Start function is obtained by an active low pulse applied at the WR input (pin 3) and the Output Enable function is caused by an active low pulse at the RD input (pin 2) 2 2 Analog Differential Voltage Inputs and Common-Mode Rejection This A D has additional applications flexibility due to the analog differential voltage input The VIN(b) input (pin 7) can be used to automatically subtract a fixed voltage value from the input reading (tare correction) This is also useful in 4 mA ­ 20 mA current loop conversion In addition commonmode noise can be reduced by use of the differential input The time interval between sampling VIN( a ) and VIN(b) is 4clock periods The maximum error voltage due to this slight time difference between the input voltage samples is given by DVe(MAX) e (VP) (2qfcm)

where DVe is the error voltage due to sampling delay VP is the peak value of the common-mode voltage fcm is the common-mode frequency As an example to keep this error to LSB ( E 5 mV) when operating with a 60 Hz common-mode frequency fcm and using a 640 kHz A D clock fCLK would allow a peak value of the common-mode voltage VP which is given by DVe(MAX) (fCLK) VP e (2qfcm) (4 5) or (5 c 10b3) (640 c 103) (6 28) (60) (4 5) which gives VP j 1 9V The allowed range of analog input voltages usually places more severe restrictions on input common-mode noise levels An analog input voltage with a reduced span and a relatively large zero offset can be handled easily by making use of the differential input (see section 2 4 Reference Voltage) VP e 2 3 Analog Inputs 2 3 1 Input Current Normal Mode Due to the internal switching action displacement currents will flow at the analog inputs This is due to on-chip stray capacitance to ground as shown in Figure 3

f J
45
CLK

TL H 5671 ­ 14

rON of SW 1 and SW 2 j 5 kX r e rON CSTRAY j 5 kX c 12 pF e 60 ns

FIGURE 3 Analog Input Impedance

15

Functional Description (Continued)
The voltage on this capacitance is switched and will result in currents entering the VIN( a ) input pin and leaving the VIN(b) input which will depend on the analog differential input voltage levels These current transients occur at the leading edge of the internal clocks They rapidly decay and do not cause errors as the on-chip comparator is strobed at the end of the clock period Fault Mode If the voltage source applied to the VIN( a ) or VIN(b) pin exceeds the allowed operating range of VCC a 50 mV large input currents can flow through a parasitic diode to the VCC pin If these currents can exceed the 1 mA max allowed spec an external diode (1N914) should be added to bypass this current to the VCC pin (with the current bypassed with this diode the voltage at the VIN( a ) pin can exceed the VCC voltage by the forward voltage of this diode) 2 3 2 Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resistances of the analog signal sources This charge pumping action is worse for continuous conversions with the VIN( a ) input voltage at full-scale For continuous conversions with a 640 kHz clock frequency with the VIN( a ) input at 5V this DC current is at a maximum of approximately 5 mA Therefore bypass capacitors should not be used at the analog inputs or the VREF 2 pin for high resistance sources (l 1 kX) If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size the detrimental effects of the voltage drop across this input resistance which is due to the average value of the input current can be eliminated with a full-scale adjustment while the given source resistor and input bypass capacitor are both in place This is possible because the average value of the input current is a precise linear function of the differential input voltage 2 3 3 Input Source Resistance Large values of source resistance where an input bypass capacitor is not used will not cause errors as the input currents settle out prior to the comparison time If a low pass filter is required in the system use a low valued series resistor (s 1 kX) for a passive RC section or add an op amp RC active low pass filter For low source resistance applications (s 1 kX) a 0 1 mF bypass capacitor at the inputs will prevent noise pickup due to series lead inductance of a long wire A 100X series resistor can be used to isolate this capacitor both the R and C are placed outside the feedback loop from the output of an op amp if used 2 3 4 Noise The leads to the analog inputs (pin 6 and 7) should be kept as short as possible to minimize input noise coupling Both noise and undesired digital clock coupling to these inputs can cause system errors The source resistance for these inputs should in general be kept below 5 kX Larger values of source resistance can cause undesired system noise pickup Input bypass capacitors placed from the analog inputs to ground will eliminate system noise pickup but can create analog scale errors as these capacitors will average the transient input switching currents of the A D (see section 2 3 1 ) This scale error depends on both a large source
TL H 5671 ­ 15

resistance and the use of an input bypass capacitor This error can be eliminated by doing a full-scale adjustment of the A D (adjust VREF 2 for a proper full-scale reading see section 2 5 2 on Full-Scale Adjustment) with the source resistance and input bypass capacitor in place 2 4 Reference Voltage 2 4 1 Span Adjust For maximum applications flexibility these A Ds have been designed to accommodate a 5 VDC 2 5 VDC or an adjusted voltage reference This has been achieved in the design of the IC as shown in Figure 4

FIGURE 4 The VREFERENCE Design on the IC Notice that the reference voltage for the IC is either of the voltage applied to the VCC supply pin or is equal to the voltage that is externally forced at the VREF 2 pin This allows for a ratiometric voltage reference using the VCC supply a 5 VDC reference voltage can be used for the VCC supply or a voltage less than 2 5 VDC can be applied to the VREF 2 input for increased application flexibility The internal gain to the VREF 2 input is 2 making the full-scale differential input voltage twice the voltage at pin 9 An example of the use of an adjusted reference voltage is to accommodate a reduced span or dynamic voltage range of the analog input voltage If the analog input voltage were to range from 0 5 VDC to 3 5 VDC instead of 0V to 5 VDC the span would be 3V as shown in Figure 5 With 0 5 VDC applied to the VIN(b) pin to absorb the offset the reference voltage can be made equal to of the 3V span or 1 5 VDC The A D now will encode the VIN( a ) signal from 0 5V to 3 5 V with the 0 5V input corresponding to zero and the 3 5 VDC input corresponding to full-scale The full 8 bits of resolution are therefore applied over this reduced analog input voltage range

16

Functional Description (Continued)

Add if VREF 2 s 1 VDC with LM358 to draw 3 mA to ground

TL H 5671 ­ 16

a) Analog Input Signal Example

b) Accommodating an Analog Input from 0 5V (Digital Out e e 00HEX) to 3 5V (Digital Out e FFHEX)

FIGURE 5 Adapting the A D Analog Input Voltages to Match an Arbitrary Input Signal Range 2 4 2 Reference Accuracy Requirements The converter can be operated in a ratiometric mode or an absolute mode In ratiometric converter applications the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A D converter and therefore cancels out in the final digital output code The ADC0805 is specified particularly for use in ratiometric applications with no adjustments required In absolute conversion applications both the initial value and the temperature stability of the reference voltage are important factors in the accuracy of the A D converter For VREF 2 voltages of 2 4 VDC nominal value initial errors of g 10 mVDC will cause conversion errors of g 1 LSB due to the gain of 2 of the VREF 2 input In reduced span applications the initial value and the stability of the VREF 2 input voltage become even more important For example if the span is reduced to 2 5V the analog input LSB voltage value is correspondingly reduced from 20 mV (5V span) to 10 mV and 1 LSB at the VREF 2 input becomes 5 mV As can be seen this reduces the allowed initial tolerance of the reference voltage and requires correspondingly less absolute change with temperature variations Note that spans smaller than 2 5V place even tighter requirements on the initial accuracy and stability of the reference source In general the magnitude of the reference voltage will require an initial adjustment Errors due to an improper value of reference voltage appear as full-scale errors in the A D transfer function IC voltage regulators may be used for references if the ambient temperature changes are not excessive The LM336B 2 5V IC reference diode (from National Semiconductor) has a temperature stability of 1 8 mV typ (6 mV max) over 0 CsTAs a 70 C Other temperature range parts are also available 2 5 Errors and Reference Voltage Adjustments 2 5 1 Zero Error The zero of the A D does not require adjustment If the minimum analog input voltage value VIN(MIN) is not ground a zero offset can be done The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing the A D VIN(b) input at this VIN(MIN) value (see Applications section) This utilizes the differential mode operation of the A D The zero error of the A D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN (b) input and applying a small magnitude positive voltage to the VIN ( a ) input Zero error is the difference between the actual DC input voltage that is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal LSB value ( LSB e 9 8 mV for VREF 2 e 2 500 VDC) 2 5 2 Full-Scale The full-scale adjustment can be made by applying a differential input voltage that is 1 LSB less than the desired analog full-scale voltage range and then adjusting the magnitude of the VREF 2 input (pin 9 or the VCC supply if pin 9 is not used) for a digital output code that is just changing from 1111 1110 to 1111 1111

17

Functional Description (Continued)
2 5 3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A D is shifted away from ground (for example to accommodate an analog input signal that does not go to ground) this new zero reference should be properly adjusted first A VIN( a ) voltage that equals this desired zero reference plus LSB (where the LSB is calculated for the desired analog span 1 LSB e analog span 256) is applied to pin 6 and the zero reference voltage at pin 7 should then be adjusted to just obtain the 00HEX to 01HEX code transition The full-scale adjustment should then be made (with the proper VIN(b) voltage applied) by forcing a voltage to the VIN( a ) input which is given by (VMAX b VMIN) VIN ( a ) fs adj e VMAXb1 5 256 where VMAX e The high end of the analog input range and VMIN e the low end (the offset zero) of the analog range (Both are ground referenced ) The VREF 2 (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX This completes the adjustment procedure 2 6 Clocking Option The clock for the A D can be derived from the CPU clock or an external RC can be added to provide self-clocking The CLK IN (pin 4) makes use of a Schmitt trigger as shown in Figure 6 conversion in process is not allowed to be completed therefore the data of the previous conversion remains in this latch The INTR output simply remains at the ``1'' level 2 8 Continuous Conversions For operation in the free-running mode an initializing pulse should be used following power-up to ensure circuit operation In this application the CS input is grounded and the WR input is tied to the INTR output This WR and INTR node should be momentarily forced to logic low following a power-up cycle to guarantee operation 2 9 Driving the Data Bus This MOS A D like MOS microprocessors and memories will require a bus driver when the total capacitance of the data bus gets large Other circuitry which is tied to the data bus will add to the total capacitive loading even in TRISTATE (high impedance mode) Backplane bussing also greatly adds to the stray capacitance of the data bus There are some alternatives available to the designer to handle this problem Basically the capacitive loading of the data bus slows down the response time even though DC specifications are still met For systems operating with a relatively slow CPU clock frequency more time is available in which to establish proper logic levels on the bus and therefore higher capacitive loads can be driven (see typical characteristics curves) At higher CPU clock frequencies time can be extended for I O reads (and or writes) by inserting wait states (8080) or using clock extending circuits (6800) Finally if time is short and capacitive loading is high external bus drivers must be used These can be TRI-STATE buffers (low power Schottky such as the DM74LS240 series is recommended) or special higher drive current products which are designed as bus drivers High current bipolar bus drivers with PNP inputs are recommended 2 10 Power Supplies Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise A low inductance tantalum filter capacitor should be used close to the converter VCC pin and values of 1 mF or greater are recommended If an unregulated voltage is available in the system a separate LM340LAZ-5 0 TO-92 5V voltage regulator for the converter (and other analog circuitry) will greatly reduce digital noise on the VCC supply 2 11 Wiring and Hook-Up Precautions Standard digital wire wrap sockets are not satisfactory for breadboarding this A D converter Sockets on PC boards can be used and all logic signal wires and leads should be grouped and kept as far away as possible from the analog signal leads Exposed leads to the analog inputs can cause undesired digital noise and hum pickup therefore shielded leads may be necessary in many applications

(

1 1 1 RC R j 10 kX fCLK j

TL H 5671­17

FIGURE 6 Self-Clocking the A D Heavy capacitive or DC loading of the clock R pin should be avoided as this will disturb normal converter operation Loads less than 50 pF such as driving up to 7 A D converter clock inputs from a single clock R pin of 1 converter are allowed For larger clock line loading a CMOS or low power TTL buffer or PNP input logic should be used to minimize the loading on the clock R pin (do not use a standard TTL buffer) 2 7 Restart During a Conversion If the A D is restarted (CS and WR go low and return high) during a conversion the converter is reset and a new conversion is started The output data latch is not updated if the

18

Functional Description (Continued)
A single point analog ground that is separate from the logic ground points should be used The power supply bypass capacitor and the self-clocking capacitor (if used) should both be returned to digital ground Any VREF 2 bypass capacitors analog input filter capacitors or input signal shielding should be returned to the analog ground point A test for proper grounding is to measure the zero error of the A D converter Zero errors in excess of LSB can usually be traced to improper board layout and wiring (see section 2 5 1 for measuring the zero error) 3 0 TESTING THE A D CONVERTER There are many degrees of complexity associated with testing an A D converter One of the simplest tests is to apply a known analog input voltage to the converter and use LEDs to display the resulting digital output code as shown in Figure 7 For ease of testing the VREF 2 (pin 9) should be supplied with 2 560 VDC and a VCC supply voltage of 5 12 VDC should be used This provides an LSB value of 20 mV If a full-scale adjustment is to be made an analog input voltage of 5 090 VDC (5 120­1 LSB) should be applied to the VIN( a ) pin with the VIN(b) pin grounded The value of the VREF 2 input voltage should then be adjusted until the digital output code is just changing from 1111 1110 to 1111 1111 This value of VREF 2 should then be used for all the tests The digital output LED display can be decoded by dividing the 8 bits into 2 hex characters the 4 most significant (MS) and the 4 least significant (LS) Table I shows the fractional binary equivalent of these two 4-bit groups By adding the voltages obtained from the ``VMS'' and ``VLS'' columns in Table I the nominal value of the digital display (when VREF 2 e 2 560V) can be determined For example for an output LED display of 1011 0110 or B6 (in hex) the voltage values from the table are 3 520 a 0 120 or 3 640 VDC These voltage values represent the center-values of a perfect A D converter The effects of quantization error have to be accounted for in the interpretation of the test results For a higher speed test system or to obtain plotted data a digital-to-analog converter is needed for the test set-up An accurate 10-bit DAC can serve as the precision voltage source for the A D Errors of the A D under test can be expressed as either analog voltages or differences in 2 digital words A basic A D tester that uses a DAC and provides the error as an analog output voltage is shown in Figure 8 The 2 op amps can be eliminated if a lab DVM with a numerical subtraction feature is available to read the difference voltage ``A ­ C'' directly The analog input voltage can be supplied by a low frequency ramp generator and an X-Y plotter can be used to provide analog error (Y axis) versus analog input (X axis) For operation with a microprocessor or a computer-based test system it is more convenient to present the errors digitally This can be done with the circuit of Figure 9 where the output code transitions can be detected as the 10-bit DAC is incremented This provides LSB steps for the 8-bit A D under test If the results of this test are automatically plotted with the analog input on the X axis and the error (in LSB's) as the Y axis a useful transfer function of the A D under test results For acceptance testing the plot is not necessary and the testing speed can be increased by establishing internal limits on the allowed error for each code 4 0 MICROPROCESSOR INTERFACING To dicuss the interface with 8080A and 6800 microprocessors a common sample subroutine structure is used The microprocessor starts the A D reads and stores the results of 16 successive conversions then returns to the user's program The 16 data bytes are stored in 16 successive memory locations All Data and Addresses will be given in hexadecimal form Software and hardware details are provided separately for each type of microprocessor 4 1 Interfacing 8080 Microprocessor Derivatives (8048 8085) This converter has been designed to directly interface with derivatives of the 8080 microprocessor The A D can be mapped into memory space (using standard memory address decoding for CS and the MEMR and MEMW strobes) or it can be controlled as an I O device by using the I O R and I O W strobes and decoding the address bits A0 x A7 (or address bits A8 x A15 as they will contain the same 8-bit address information) to obtain the CS input Using the I O space provides 256 additional addresses and may allow a simpler 8-bit address decoder but the data can only be input to the accumulator To make use of the additional memory reference instructions the A D should be mapped into memory space An example of an A D in I O space is shown in Figure 10

TL H 5671 ­ 18

FIGURE 7 Basic A D Tester

19

Functional Description (Continued)

FIGURE 8 A D Tester with Analog Error Output

TL H 5671 ­ 19

FIGURE 9 Basic ``Digital'' A D Tester

TABLE I DECODING THE DIGITAL OUTPUT LEDs OUTPUT VOLTAGE CENTER VALUES WITH VREF 2 e 2 560 VDC VMS GROUP 15 256 7 128 13 16 3 4 11 16 5 8 9 16 1 2 7 16 3 8 5 16 1 4 3 16 1 8 1 16 1 128 1 256 1 64 3 256 3 128 2 256 1 32 7 256 5 128 9 256 3 64 11 256 13 256 4 800 4 480 4 160 3 840 3 520 3 200 2 880 2 560 2 240 1 920 1 600 1 280 0 960 0 640 0 320 0 VLS GROUP 0 300 0 280 0 260 0 240 0 220 0 200 0 180 0 160 0 140 0 120 0 100 0 080 0 060 0 040 0 020 0

HEX

BINARY

FRACTIONAL BINARY VALUE FOR

MS GROUP F E D C B A 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 15 16 7 8

LS GROUP

Display Output e VMS Group a VLS Group

20

Functional Description (Continued)

TL H 5671 ­ 20

Note 1

Pin numbers for the DP8228 system controller others are INS8080A

Note 2 Pin 23 of the INS8228 must be tied to a 12V through a 1 kX resistor to generate the RST 7 instruction when an interrupt is acknowledged as required by the accompanying sample program

FIGURE 10 ADC0801 ­ INS8080A CPU Interface SAMPLE PROGRAM FOR FIGURE 10 ADC0801 ­ INS8080A CPU INTERFACE C3 00 03 RST 7 JMP LD DATA

0038


0100 0103 0106 0107 0109 010C 010E 010F 0110 0113


21 00 02 31 00 04 7D FE OF CA 13 01 D3 E0 FB 00 C3 OF 01


START RETURN LXI H 0200H LXI SP 0400H MOV A L CPI OF H JZ CONT OUT E0 H EI NOP JMP LOOP HL pair will point to data storage locations Initialize stack pointer (Note 1) Test of bytes entered If 4 16 JMP to user program Start A D Enable interrupt Loop until end of conversion

LOOP CONT


0300 0302 0303 0304


DB E0 77 23 C3 03 01


(User program to process data)


LD DATA


IN E0 H MOV M A INX H JMP RETURN Load data into accumulator Store data Increment storage pointer

Note 1 The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack Note 2 All address used were arbitrarily chosen

21

Functional Description (Continued)
The standard control bus signals of the 8080 CS RD and WR) can be directly wired to the digital control inputs of the A D and the bus timing requirements are met to allow both starting the converter and outputting the data onto the data bus A bus driver should be used for larger microprocessor systems where the data bus leaves the PC board and or must drive capacitive loads larger than 100 pF 4 1 1 Sample 8080A CPU Interfacing Circuitry and Program The following sample program and associated hardware shown in Figure 10 may be used to input data from the converter to the INS8080A CPU chip set (comprised of the INS8080A microprocessor the INS8228 system controller and the INS8224 clock generator) For simplicity the A D is controlled as an I O device specifically an 8-bit bi-directional port located at an arbitrarily chosen port address E0 The TRI-STATE output capability of the A D eliminates the need for a peripheral interface device however address decoding is still required to generate the appropriate CS for the converter It is important to note that in systems where the A D converter is 1-of-8 or less I O mapped devices no address decoding circuitry is necessary Each of the 8 address bits (A0 to A7) can be directly used as CS inputs one for each I O device 4 1 2 INS8048 Interface The INS8048 interface technique with the ADC0801 series (see Figure 11 ) is simpler than the 8080A CPU interface There are 24 I O lines and three test input lines in the 8048 With these extra I O lines available one of the I O lines (bit 0 of port 1) is used as the chip select signal to the A D thus eliminating the use of an external address decoder Bus control signals RD WR and INT of the 8048 are tied directly to the A D The 16 converted data words are stored at onchip RAM locations from 20 to 2F (Hex) The RD and WR signals are generated by reading from and writing into a dummy address respectively A sample interface program is shown below

TL H 5671 ­ 21

FIGURE 11 INS8048 Interface SAMPLE PROGRAM FOR FIGURE 11 INS8048 INTERFACE 04 10 04 50 99 FE 81 89 01 B8 20 B9 FF BA 10 23 FF 99 FE 91 05 96 21 EA 1B 00 00 81 A0 18 89 01 27 93 START JMP ORG JMP ORG ANL MOVX ORL MOV MOV MOV MOV ANL MOVX EN JNZ DJNZ NOP NOP ORG MOVX MOV INC ORL CLR RETR 10H 3H 50H 10H P1 0FEH A R1 1 P1 R0 20H R1 0FFH R2 10H A 0FFH P1 0FEH R1 A I LOOP R2 AGAIN Program starts at addr 10 Interrupt jump vector Main program Chip select Read in the 1st data to reset the intr Set port pin high Data address Dummy address Counter for 16 bytes Set ACC for intr loop Send CS (bit 0 of P1) Send WR out Enable interrupt Wait for interrupt If 16 bytes are read go to user's program

AGAIN

LOOP

INDATA

50H A R1 R0 A R0 P1 1 A 22

Input data CS still low Store in memory Increment storage counter Reset CS signal Clear ACC to get out of the interrupt loop

Functional Description (Continued)
4 2 Interfacing the Z-80 The Z-80 control bus is slightly different from that of the 8080 General RD and WR strobes are provided and separate memory request MREQ and I O request IORQ signals are used which have to be combined with the generalized strobes to provide the equivalent 8080 signals An advantage of operating the A D in I O space with the Z-80 is that the CPU will automatically insert one wait state (the RD and WR strobes are extended one clock period) to allow more time for the I O devices to respond Logic to map the A D in I O space is shown in Figure 13

ready decoded 4 5 line is brought out to the common bus at pin 21 This can be tied directly to the CS pin of the A D provided that no other devices are addressed at HX ADDR 4XXX or 5XXX The following subroutine performs essentially the same function as in the case of the 8080A interface and it can be called from anywhere in the user's program In Figure 15 the ADC0801 series is interfaced to the M6800 microprocessor through (the arbitrarily chosen) Port B of the MC6820 or MC6821 Peripheral Interface Adapter (PIA) Here the CS pin of the A D is grounded since the PIA is already memory mapped in the M6800 system and no CS decoding is necessary Also notice that the A D output data lines are connected to the microprocessor bus under program control through the PIA and therefore the A D RD pin can be grounded A sample interface program equivalent to the previous one is shown below Figure 15 The PIA Data and Control Registers of Port B are located at HEX addresses 8006 and 8007 respectively 5 0 GENERAL APPLICATIONS The following applications show some interesting uses for the A D The fact that one particular microprocessor is used is not meant to be restrictive Each of these application circuits would have its counterpart using any microprocessor that is desired 5 1 Multiple ADC0801 Series to MC6800 CPU Interface To transfer analog data from several channels to a single microprocessor system a multiple converter scheme presents several advantages over the conventional multiplexer single-converter approach With the ADC0801 series the differential inputs allow individual span adjustment for each channel Furthermore all analog input channels are sensed simultaneously which essentially divides the microprocessor's total system servicing time by the number of channels since all conversions occur simultaneously This scheme is shown in Figure 16

TL H 5671 ­ 23

FIGURE 13 Mapping the A D as an I O Device for Use with the Z-80 CPU Additional I O advantages exist as software DMA routines are available and use can be made of the output data transfer which exists on the upper 8 address lines (A8 to A15) during I O input instructions For example MUX channel selection for the A D can be accomplished with this operating mode 4 3 Interfacing 6800 Microprocessor Derivatives (6502 etc ) The control bus for the 6800 microprocessor derivatives does not use the RD and WR strobe signals Instead it employs a single R W line and additional timing if needed can be derived fom the w2 clock All I O devices are memory mapped in the 6800 system and a special signal VMA indicates that the current address is valid Figure 14 shows an interface schematic where the A D is memory mapped in the 6800 system For simplicity the CS decoding is shown using DM8092 Note that in many 6800 systems an al-

Note 1 Numbers in parentheses refer to MC6800 CPU pin out Note 2 Number or letters in brackets refer to standard M6800 system common bus code

TL H 5671 ­ 24

FIGURE 14 ADC0801-MC6800 CPU Interface 23

Functional Description (Continued)
0010 0012 0015 0018 001B 001C 001D 001F 0022 0024 0027 0028 002A 002C 002E 0031 0033 0034 0036 0038 003B 003D 003F SAMPLE PROGRAM FOR FIGURE 14 ADC0801-MC6800 CPU INTERFACE DF 36 DATAIN STX TEMP2 Save contents of X CE 00 2C LDX $002C Upon IRQ low CPU FF FF F8 STX $FFF8 jumps to 002C B7 50 00 STAA $5000 Start ADC0801 0E CLI 3E CONVRT WAI Wait for interrupt DE 34 LDX TEMP1 8C 02 0F CPX $020F Is final data stored 27 14 BEQ ENDP B7 50 00 STAA $5000 Restarts ADC0801 08 INX DF 34 STX TEMP1 20 F0 BRA CONVRT DE 34 INTRPT LDX TEMP1 B6 50 00 LDAA $5000 Read data A7 00 STAA X Store it at X 3B RTI 02 00 TEMP1 FDB $0200 Starting address for data storage 00 00 TEMP2 FDB $0000 CE 02 00 ENDP LDX $0200 Reinitialize TEMP1 DF 34 STX TEMP1 DE 36 LDX TEMP2 39 RTS Return from subroutine To user's program

Note 1 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned in the user's program

TL H 5671 ­ 25

FIGURE 15 ADC0801 ­ MC6820 PIA Interface

24

Functional Description (Continued)
SAMPLE PROGRAM FOR FIGURE 15 ADC0801 ­ MC6820 PIA INTERFACE 0010 0013 0016 0019 001A 001D 0020 0021 0023 0025 0028 002B 002C 002E 0031 0033 0034 0036 0038 003A 003D 003F 0040 0042 0045 0047 CE 00 38 FF FF F8 B6 80 06 4F B7 80 07 B7 80 06 0E C6 34 86 3D F7 80 07 B7 80 07 3E DE 40 8C 02 0F 27 0F 08 DF 40 20 ED DE 40 B6 80 06 A7 00 3B 02 00 CE 02 00 DF 40 39 DATAIN LDX STX LDAA CLRA STAA STAA CLI LDAB LDAA STAB STAA WAI LDX CPX BEQ INX STX BRA LDX LDAA STAA RTI FDB LDX STX RTS EQU EQU $0038 $FFF8 PIAORB PIACRB PIAORB $34 $3D PIACRB PIACRB TEMP1 $020F ENDP TEMP1 CONVRT TEMP1 PIAORB X $0200 $0200 TEMP1 $8006 $8007 Upon IRQ low CPU jumps to 0038 Clear possible IRQ flags

Set Port B as input

CONVRT

Starts ADC0801 Wait for interrupt Is final data stored

INTRPT

Read data in Store it at X Starting address for data storage Reinitialize TEMP1 Return from subroutine To user's program

TEMP1 ENDP

PIAORB PIACRB

The following schematic and sample subroutine (DATA IN) may be used to interface (up to) 8 ADC0801's directly to the MC6800 CPU This scheme can easily be extended to allow the interface of more converters In this configuration the converters are (arbitrarily) located at HEX address 5000 in the MC6800 memory space To save components the clock signal is derived from just one RC pair on the first converter This output drives the other A Ds All the converters are started simultaneously with a STORE instruction at HEX address 5000 Note that any other HEX address of the form 5XXX will be decoded by the circuit pulling all the CS inputs low This can easily be avoided by using a more definitive address decoding scheme All the interrupts are ORed together to insure that all A Ds have completed their conversion before the microprocessor is interrupted The subroutine DATA IN may be called from anywhere in the user's program Once called this routine initializes the

CPU starts all the converters simultaneously and waits for the interrupt signal Upon receiving the interrupt it reads the converters (from HEX addresses 5000 through 5007) and stores the data successively at (arbitrarily chosen) HEX addresses 0200 to 0207 before returning to the user's program All CPU registers then recover the original data they had before servicing DATA IN 5 2 Auto-Zeroed Differential Transducer Amplifier and A D Converter The differential inputs of the ADC0801 series eliminate the need to perform a differential to single ended conversion for a differential transducer Thus one op amp can be eliminated since the differential to single ended conversion is provided by the differential input of the ADC0801 series In general a transducer preamp is required to take advantage of the full A D converter input dynamic range

25

Functional Description (Continued)

Note 1 Numbers in parentheses refer to MC6800 CPU pin out Note 2 Numbers of letters in brackets refer to standard M6800 system common bus code
TL H 5671 ­ 26

FIGURE 16 Interfacing Multiple A Ds in an MC6800 System SAMPLE PROGRAM FOR FIGURE 16 INTERFACING MULTIPLE A Ds IN AN MC6800 SYSTEM ADDRESS HEX CODE MNEMONICS COMMENTS 0010 DF 44 DATAIN STX TEMP Save Contents of X 0012 CE 00 2A LDX $002A Upon IRQ LOW CPU 0015 FF FF F8 STX $FFF8 Jumps to 002A 0018 B7 50 00 STAA $5000 Starts all A D's 001B 0E CLI 001C 3E WAI Wait for interrupt 001D CE 50 00 LDX $5000 0020 DF 40 STX INDEX1 Reset both INDEX 0022 CE 02 00 LDX $0200 1 and 2 to starting 0025 DF 42 STX INDEX2 addresses 0027 DE 44 LDX TEMP 0029 39 RTS Return from subroutine 002A DE 40 INTRPT LDX INDEX1 INDEX1 x X 002C A6 00 LDAA X Read data in from A D at X 002E 08 INX Increment X by one 002F DF 40 STX INDEX1 X x INDEX1 0031 DE 42 LDX INDEX2 INDEX2 x X 26

Functional Description (Continued)
SAMPLE PROGRAM FOR FIGURE 16 INTERFACING MULTIPLE A Ds IN AN MC6800 SYSTEM ADDRESS HEX CODE MNEMONICS COMMENTS 0033 A7 00 STAA X Store data at X 0035 8C 02 07 CPX $0207 Have all A D's been read 0038 27 05 BEQ RETURN Yes branch to RETURN 003A 08 INX No increment X by one 003B DF 42 STX INDEX2 X x INDEX2 003D 20 EB BRA INTRPT Branch to 002A 003F 3B RETURN RTI 0040 50 00 INDEX1 FDB $5000 Starting address for A D 0042 02 00 INDEX2 FDB $0200 Starting address for data storage 0044 00 00 TEMP FDB $0000
Note 1 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned in the user's program

For amplification of DC input signals a major system error is the input offset voltage of the amplifiers used for the preamp Figure 17 is a gain of 100 differential preamp whose offset voltage errors will be cancelled by a zeroing subroutine which is performed by the INS8080A microprocessor system The total allowable input offset voltage error for this preamp is only 50 mV for LSB error This would obviously require very precise amplifiers The expression for the differential output voltage of the preamp is VO e VIN( a )bVIN(b) 1a 2R2 a R1

X
SIGNAL

Y X

Y

(

GAIN

(VOS2 b VOS1 b VOS3 g IXRX)

X

Y X

1

a

2R2 R1

Y

J

DC ERROR TERM GAIN where IX is the current through resistor RX All of the offset error terms can be cancelled by making g IXRX e VOS1 a VOS3 b VOS2 This is the principle of this auto-zeroing scheme The INS8080A uses the 3 I O ports of an INS8255 Programable Peripheral Interface (PPI) to control the auto zeroing and input data from the ADC0801 as shown in Figure 18 The PPI is programmed for basic I O operation (mode 0) with Port A being an input port and Ports B and C being output ports Two bits of Port C are used to alternately open or close the 2 switches at the input of the preamp Switch

SW1 is closed to force the preamp's differential input to be zero during the zeroing subroutine and then opened and SW2 is then closed for conversion of the actual differential input signal Using 2 switches in this manner eliminates concern for the ON resistance of the switches as they must conduct only the input bias current of the input amplifiers Output Port B is used as a successive approximation register by the 8080 and the binary scaled resistors in series with each output bit create a D A converter During the zeroing subroutine the voltage at Vx increases or decreases as required to make the differential output voltage equal to zero This is accomplished by ensuring that the voltage at the output of A1 is approximately 2 5V so that a logic ``1'' (5V) on any output of Port B will source current into node VX thus raising the voltage at VX and making the output differential more negative Conversely a logic ``0'' (0V) will pull current out of node VX and decrease the voltage causing the differential output to become more positive For the resistor values shown VX can move g 12 mV with a resolution of 50 mV which will null the offset error term to LSB of fullscale for the ADC0801 It is important that the voltage levels that drive the auto-zero resistors be constant Also for symmetry a logic swing of 0V to 5V is convenient To achieve this a CMOS buffer is used for the logic output signals of Port B and this CMOS package is powered with a stable 5V source Buffer amplifier A1 is necessary so that it can source or sink the D A output current

27

Functional Description (Continued)

Note 1 R2 e 49 5 R1 Note 2 Switches are LMC13334 CMOS analog switches Note 3 The 9 resistors used in the auto-zero section can be g 5% tolerance

FIGURE 17 Gain of 100 Differential Transducer Preamp

TL H 5671 ­ 27

FIGURE 18 Microprocessor Interface Circuitry for Differential Preamp

28

A flow chart for the zeroing subroutine is shown in Figure 19 It must be noted that the ADC0801 series will output an all zero code when it converts a negative input VIN(b) t VIN( a ) Also a logic inversion exists as all of the I O ports are buffered with inverting gates Basically if the data read is zero the differential output voltage is negative so a bit in Port B is cleared to pull VX more negative which will make the output more positive for the next conversion If the data read is not zero the output voltage is positive so a bit in Port B is set to make VX more positive and the output more negative This continues for 8 approximations and the differential output eventually converges to within 5 mV of zero The actual program is given in Figure 20 All addresses used are compatible with the BLC 80 10 microcomputer system In particular Port A and the ADC0801 are at port address E4 Port B is at port address E5 Port C is at port address E6 PPI control word port is at port address E7 Program Counter automatically goes to ADDR 3C3D upon acknowledgement of an interrupt from the ADC0801 5 3 Multiple A D Converters in a Z-80 Interrupt Driven Mode In data acquisition systems where more than one A D converter (or other peripheral device) will be interrupting program execution of a microprocessor there is obviously a need for the CPU to determine which device requires servicing Figure 21 and the accompanying software is a method of determining which of 7 ADC0801 converters has completed a conversion (INTR asserted) and is requesting an interrupt This circuit allows starting the A D converters in any sequence but will input and store valid data from the converters with a priority sequence of A D 1 being read first A D 2 second etc through A D 7 which would have the lowest priority for data being read Only the converters whose INT is asserted will be read The key to decoding circuitry is the DM74LS373 8-bit D type flip-flop When the Z-80 acknowledges the interrupt the program is vectored to a data input Z-80 subroutine This subroutine will read a peripheral status word from the DM74LS373 which contains the logic state of the INTR outputs of all the converters Each converter which initiates an interrupt will place a logic ``0'' in a unique bit position in the status word and the subroutine will determine the identity of the converter and execute a data read An identifier word (which indicates which A D the data came from) is stored in the next sequential memory location above the location of the data so the program can keep track of the identity of the data entered
TL H 5671 ­ 28

FIGURE 19 Flow Chart for Auto-Zero Routine

29

3D00 3D02 3D04 3D06 3D07 3D09 3D0B 3D0D 3D0E 3D10 3D13 3D15 3D16 3D17 3D1A 3D1B 3D1D 3D20 3D21 3D23 3D24 3D26 3D29 3D2A 3D2D 3D2E 3D2F 3D30 3D33 3D34 3D37 3D38 3D39 3D3B 3D3D

3E90 D3E7 2601 7C D3E6 0680 3E7F 4F D3E5 31AA3D D3E4 FB 00 C3163D 7A C600 CA2D3D 78 F600 1F FE00 CA373D 47 C3333D 79 B0 4F C3203D A9 C30D3D 47 7C EE03 D3E6

MVI 90 Out Control Port MVI H 01 MOV A H OUT C MVI B 80 MVI A 7F MOV C A OUT B LXI SP 3DAA OUT A IE NOP JMP Loop MOV A D ADI 00 JZ Set C MOV A B ORI 00 RAR CPI 00 JZ Done MOV B A JMP New C MOV A C ORA B MOV C A JMP Shift B XRA C JMP Return MOV B A MOV A H XRI 03 OUT C

Program PPI Auto-Zero Subroutine Close SW1 open SW2 Initialize SAR bit pointer Initialize SAR code Return Start Port B 4 SAR code Dimension stack pointer Start A D Loop until INT asserted

Loop Auto-Zero

Test A D output data for zero Shift B Clear carry Shift `1` in B right one place Is B zero If yes last approximation has been made

Set C Set bit in C that is in same position as `1` in B New C Done Clear bit in C that is in same position as `1` in B then output new SAR code Open SW1 close SW2 then proceed with program Preamp is now zeroed


DBE4 EEFF 57 78 E6FF C21A3D C33D3D Program for processing proper data values IN A XRI FF MOV D A MOV A B ANI FF JNZ Auto-Zero JMP Normal

Normal

3C3D 3C3F 3C41 3C42 3C43 3C45 3C48

Read A D Subroutine

Read A D data Invert data Is B Reg 4 0 If not stay in auto zero subroutine

Note All numerical values are hexadecimal representations

FIGURE 20 Software for Auto-Zeroed Differential A D 5 3 Multiple A D Converters in a Z-80 Interrupt Driven Mode (Continued) The following notes apply 1) It is assumed that the CPU automatically performs a RST 7 instruction when a valid interrupt is acknowledged (CPU is in interrupt mode 1) Hence the subroutine starting address of X0038 2) The address bus from the Z-80 and the data bus to the Z80 are assumed to be inverted by bus drivers 3) A D data and identifying words will be stored in sequential memory locations starting at the arbitrarily chosen address X 3E00 4) The stack pointer must be dimensioned in the main program as the RST 7 instruction automatically pushes the PC onto the stack and the subroutine uses an additional 6 stack addresses

5) The peripherals of concern are mapped into I O space with the following port assignments HEX PORT ADDRESS PERIPHERAL 00 MM74C374 8-bit flip-flop 01 A D1 02 A D2 03 A D3 04 A D4 05 A D5 06 A D6 07 A D7 This port address also serves as the A D identifying word in the program

30

TL H 5671 ­ 29

FIGURE 21 Multiple A Ds with Z-80 Type Microprocessor INTERRUPT SERVICING SUBROUTINE SOURCE LOC OBJ CODE STATEMENT COMMENT 0038 E5 PUSH HL Save contents of all registers affected by 0039 C5 PUSH BC this subroutine 003A F5 PUSH AF Assumed INT mode 1 earlier set 003B 21 00 3E LD (HL) X3E00 Initialize memory pointer where data will be stored 003E 0E 01 LD C X01 C register will be port ADDR of A D converters 0040 D300 OUT X00 A Load peripheral status word into 8-bit latch 0042 DB00 IN A X00 Load status word into accumulator 0044 47 LD B A Save the status word 0045 79 TEST LD A C Test to see if the status of all A D's have 0046 FE 08 CP X08 been checked If so exit subroutine 0048 CA 60 00 JPZ DONE 004B 78 LD A B Test a single bit in status word by looking for 004C 1F RRA a `1` to be rotated into the CARRY (an INT 004D 47 LD B A is loaded as a `1`) If CARRY is set then load 004E DA 5500 JPC LOAD contents of A D at port ADDR in C register 0051 0C NEXT INC C If CARRY is not set increment C register to point 0052 C3 4500 JP TEST to next A D then test next bit in status word 0055 ED 78 LOAD IN A (C) Read data from interrupting A D and invert 0057 EE FF XOR FF the data 0059 77 LD (HL) A Store the data 005A 2C INC L 005B 71 LD (HL) C Store A D identifier (A D port ADDR) 005C 2C INC L 005D C3 51 00 JP NEXT Test next bit in status word 0060 F1 DONE POP AF Re-establish all registers as they were 0061 C1 POP BC before the interrupt 0062 E1 POP HL 0063 C9 RET Return to original program 31

Ordering Information
TEMP RANGE
g Bit Adjusted g Bit Unadjusted g Bit Adjusted g 1Bit Unadjusted

0 C TO 70 C

0 C TO 70 C

0 C TO 70 C

b 40 C TO a 85 C

ADC0801LCN ADC0802LCWM ADC0803LCWM ADC0804LCWM M20B Small Outline ADC0802LCV ADC0803LCV ADC0804LCV V20A Chip Carrier ADC0804LCN N20A ADC0802LCN ADC0803LCN ADC0805LCN Molded DIP

ERROR

PACKAGE OUTLINE

TEMP RANGE Bit Adjusted Bit Unadjusted g Bit Adjusted g 1Bit Unadjusted
g g

b 40 C TO a 85 C

b 55 C TO a 125 C

ERROR

ADC0801LCJ ADC0802LCJ ADC0803LCJ ADC0804LCJ J20A Cavity DIP

ADC0801LJ ADC0802LJ ADC0802LJ 883 J20A Cavity DIP

PACKAGE OUTLINE

Connection Diagrams
ADC080X Dual-In-Line and Small Outline (SO) Packages ADC080X Molded Chip Carrier (PCC) Package

TL H 5671­30

TL H 5671 ­ 32

See Ordering Information

32

33

Physical Dimensions inches (millimeters)

Dual-In-Line Package (J) Order Number ADC0801LJ ADC0802LJ ADC0801LCJ ADC0802LCJ ADC0803LCJ or ADC0804LCJ ADC0802LJ 883 or 5962-9096601MRA NS Package Number J20A

SO Package (M) Order Number ADC0802LCWM ADC0803LCWM or ADC0804LCWM NS Package Number M20B 34

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N) Order Number AD