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5 4 3 2 1
Project code: 91.4HP01.001
PCB P/N : 48.4HP01.011
REVISION : 09929-1
PCB STACKUP
DDR3 800/1066/1333MHz
TOP
SYSTEM DC/DC
AMD Champlain CPU RT8223 45
D
DIMM1 16 S1G4 (45W) CRT INPUTS OUTPUTS
D
20 VCC
5V_S5(5A)
800/1066/1333MHz DCBATOUT
DDR3 800/1066/1333MHz
638-Pin uFCPGA638
4,5,6,7
LCD S 3D3V_S5(5A)
800/1066/1333 MHz 19 S SYSTEM DC/DC
DIMM2 & DIMM3 17 GND RT8209E 46
HDMI INPUTS OUTPUTS
OUT
HT 3.0 21 BOTTOM
IN
16X16 DCBATOUT 1D5V_S3
Madison & Park
DDR3 SYSTEM DC/DC
3 North Bridge ATI RT8015A 47
CLK GEN. AMD RS880M
16X
52,53,54,55,56
VRAM
57, 58, 59, 60 INPUTS OUTPUTS
ICS9LPRS480BKLFT 71.09480.A03 CPU I/F LVDS, CRT I/F PCI EXPRESS GRAPHIC
RTM880N-796-VB-GRT 71.00880.A03 DCBATOUT 1D8V_S0
INTEGRATED GRAHPICS PCIex1 LAN
Giga LAN TXFM RJ45 RT9025 48
27 27
C
21*21*1.84mm BCM57780 26 5V_S5 1D05V_S0 C
INT MIC 8,9,10
RT9161 48
30 Mini Card
A-Link 33 3D3V_S0 2D5V_S0
WLAN (200mA)
MIC In Codec AZALIA 4X1
Mini Card RT9025 48
30
ALC272 33
28 3D3V_S0 1V_VGA
(1.2A)
Line Out South Bridge RT9025,RT8209E 47
AMD SB820
LPC BUS 3D3V_S5 1D1V_S5
30 5V_S5 1D1V_S0
USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb) BIOS CHARGER
High Definition Audio KBC MXIC
LPC BQ24745 49
ATA 66/100 Novoton MX25L1605
DEBUG INPUTS OUTPUTS
NPCE781B 37 CONN.37
B ACPI 1.1 36 B
INT.SPKR CHG_PWR
LPC I/F
18V 6.0A
30 PCI/PCI BRIDGE DCBATOUT
OP AMP UP+5V
23*23*1.92mm Touch INT. 5V 100mA
29 Daughter Board
11,12,13,14,15 Pad 38 KB 36 Power Board(09744-1) CPU DC/DC
ISL6265HR 44
INPUTS OUTPUTS
CardReader Daughter Board VCC_CORE_S0_0
MS/MS Pro/xD Power Board(09741-1)
AU6437 0~1.55V 18A
/MMC/SD
5 in 1 VCC_CORE_S0_1
SATA USB 32 32 DCBATOUT
HDD SATA Daughter Board 0~1.55V 18A
22 Power Board(09742-1) VDDNB
USB Daughter Board 0~1.55V 18A
SATA 2 Port 25 USB Board
ODD SATA
A 23 JE70-DN A
Blue Tooth Camera
24 19 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
USB Title
1 Port 25 BLOCK DIAGRAM
Size Document Number Rev
A3
JE70-DN SB
Date: W ednesday, March 31, 2010 Sheet 1 of 63
5 4 3 2 1
5 4 3 2 1
page36
EC Functional Strap Definitions
Signal Comment
Test Mode Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to
determine the device operation mode as follows:
page9
TEST# No pull-down resistor: Normal operation mode (XORTR and TRIST strap pins
are ignored).
STRAP_DEBUG_BUS_GPIO_ENABLEb pin110
10 K external pull-down resistor:Test mode (ICT or XOR-Tree Test mode,
D Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC#) according to XORTR and TRIST strap pins). D
1 :Disable 0 : Enable
* XOR-Tree Mode Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to
select the XOR-Tree Test mode, if TEST is strapped low:
RS780: Enables Side port memory ( RS880 use HSYNC#)
XORTR# No pull-down resistor: Not allowed if TEST pin is strapped low.
*1 :Disable 0 : Enable
pin111 10 K external pull-down resistor:XOR-Tree Test mode .Note: TRIST strap
pin must be left unconnected.
SUS_STAT# ICT Mode Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to
Selects Loading of STRAPS From EEPROM select the ICT Test mode, if TEST is strapped low:
*1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, No pull-down resistor: Not allowed if TEST pin is strapped low.
or use default values if not connected TRIST# 10 K external pull-down resistor:ICT Test mode (see Section 3.4.1 on page
53), forces the device to float its output and I/O pins.Note: XORTR strap pin
pin112 must be left unconnected.
JTAG Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to select
the JTAG signals to device pins (see Table 4 on page 35 for details).
JEN0#, JENK# Both JEN0 and JENK, are pulled to 1 by an internal resistor
pin49,53 The external 10 K pull-down resistor must be connected to GND.
page15
Shared Host BIOS Memory. Sampled at VCC Power-Up reset or VCC_POR Input
reset, to determine the state of the shared BIOS memory.
C
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 SHBM C
No pull-down resistor:Disable the shared BIOS memory.
pin83
PULL USE PCI DISABLE ILA USE FC USE DEFAULT DISABLE PCI 10 K external pull-down resistor:Enable the shared BIOS memory
HIGH PLL AUTORUN PLL PCIE STRAPS MEM BOOT
Port80 (SDP) Visibility Mode Select. Sampled at VCC Power-Up reset or
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT VCC_POR Input reset, to select the Visibility mode for the Port80 (SDP).
SDP_VIS#
No pull-down resistor: SDP in Normal mode
PULL BYPASS ENABLE ILA BYPASS FC USE EEPROM ENABLE PCI pin41
PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT 10 K external pull-down resistor:SDP in Visibility mode.
LOW
XOR_OUT XOR-Tree Output. The device pins are internally connected in a XOR-tree structure
pin35
Note: SB820 has 15K internal PU FOR PCI_AD[27:23]
page15
page12 USB
PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 AZ_SDOUT GPIO200 GPIO199 Pair Device
B PULL ALLOW Watchdog USE non_Fusion EC CLKGEN LOW POWER 12 MINI2 CARD B
PCIE Gen2 Timer DEBUG CLOCK MODE ENABLED ENABLED MODE H,H = Reserved
HIGH 11 NC
DEFAULT Enabled STRAP DEFAULT DEFAULT
H,L = SPI ROM 10 NC
9 CCD
PULL FORCE Watchdog IGNORE FUSION EC CLKGEN PERFORMANCE L,H = LPC ROM (Default)
LOW PCIE Gen1 Timer DEBUG CLOCK MODE DISABLED DISABLED MODE 8 NC
L,L = FWH ROM
Disabled STRAP 7 Bluetooth
DEFAULT DEFAULT DEFAULT DEFAULT
6 USB3
OCP3# 5 USB2
NOTE: SB820 HAS INTERNAL 15K PULL UP RESISTOR FOR RTCCLK 4 CardReader
3 NC
OCP2# 2 USB4
1 MINI1 CARD
OCP0# 0 USB1
JE70-DN
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reference
Size Document Number Rev
A3
JE70-DN SB
Date: Thursday, November 19, 2009 Sheet 2 of 63
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
DY DY 3D3V_S0
1 R556 2 R603
0R0603-PAD 1 2 3D3V_48MPW R_S0
1
1
1
1
1
1
1
1
1
C808 C809 C519 C814 C825 C817 C512 C812 C517
1
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2R3J-GP C840 C838
DY SC1U10V2KX-1GP
2
2
2
2
2
2
2
2
2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2
2
3000mA.80ohm
D D
CLK_PCIE_PEG 1 2
DY DY EC62 SC22P50V2JN-4GP
CLK_PCIE_PEG# 1 2
DY EC63 SC22P50V2JN-4GP
3D3V_S0 1D1V_CLK_VDDIO
C830 CLK_NB_GFX 1 2
1 R565 2 R591 SC12P50V2JN-L1-GP DY EC65 SC22P50V2JN-4GP
0R0603-PAD 1 DY 2 1 2 CLK_NB_GFX# 1 2
1
1
1
1
1
1
1
C816 C820 C518 C813 C516 C815 C515 3D3V_CLK_VDD DY EC64 SC22P50V2JN-4GP
1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
10MR2J-L-GP 82.30005.A51
U75 X7 CLK_PCIE_SB 1 2
2
2
2
2
2
2
2
1D1V_CLK_VDDIO X-14D31818M-50GP C833 DY EC69 SC22P50V2JN-4GP
26 61 GEN_XTAL_IN CLK_PCIE_SB# 1 2
2
VDDATIG X1 GEN_XTAL_OUT SC12P50V2JN-L1-GP EC68 SC22P50V2JN-4GP
25 VDDATIG_IO X2 62 1 2 DY
48 CLK_PCIE_LAN 1 2
VDDCPU EC67 SC22P50V2JN-4GP
47 VDDCPU_IO SMBCLK 2 SMBC0_SB 12,16,17 DY
3 CLK_PCIE_LAN# 1 2
SMBDAT SMBD0_SB 12,16,17
16 DY EC66 SC22P50V2JN-4GP
VDDSRC
DY 17 VDDSRC_IO
11 30 CLK_NB_GPPSB 1 2
3D3V_CLK_VDD VDDSRC_IO ATIG0T_LPRS CLK_PCIE_PEG 52 EC71 SC22P50V2JN-4GP
ATIG0C_LPRS 29 CLK_PCIE_PEG# 52 DY
35 28 CLK_NB_GPPSB# 1 2
VDDSB_SRC ATIG1T_LPRS EC70 SC22P50V2JN-4GP
34 VDDSB_SRC_IO ATIG1C_LPRS 27 CLK_NB_GFX 9 DY
CLK_NB_GFX# 9
1 R303 2 40 VDDS