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Magpie
VC0918
MAGPIE TM
Mobile Phone Audio Processor ------ MIDI
Datasheet Detail
Version 1.1
Confidential
The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is
up-to-date.
Page 1 of 62 VC918 Datasheet Detail 1.1
Confidential Preliminary
Magpie
1 OVERVIEW ............................................................................................................................4
2 FEATURES..............................................................................................................................4
3 PIN LAYOUT ..........................................................................................................................6
4 PIN DEFINITION...................................................................................................................6
4.1 DIFFERENCE BETWEEN VC0918D AND VC0918S ........................................................... 7
5 SYSTEM BLOCK DIAGRAM..............................................................................................8
6 CHIP BLOCK DIAGRAM ....................................................................................................9
7 REGISTER MAP....................................................................................................................9
7.1 HOST CPU I/O REGISTER MAP ........................................................................................ 9
7.2 CHANNEL ATTRIBUTE REGISTER MAP ........................................................................... 21
7.2.1 Channel register allocation........................................................................................... 21
7.2.2 Channel register definition............................................................................................ 21
8 THE MAIN BUILDING BLOCKS......................................................................................25
8.1 MAIN BUILDING BLOCKS DESCRIPTION:......................................................................... 25
8.2 BUS INTERFACE (BIU) ................................................................................................... 26
8.2.1 Part of CPU interface ................................................................................................... 26
8.2.2 Selection of CPU interface............................................................................................ 26
8.2.3 Multiplex (parallel) interface ........................................................................................ 27
8.2.4 Serial interface .............................................................................................................. 27
8.2.5 Multiplex (parallel) interface characteristics ............................................................... 29
8.2.6 Serial interface characteristics ..................................................................................... 30
8.2.7 CPU Interface Applications .......................................................................................... 31
8.3 CLOCK SCHEME ............................................................................................................. 32
8.3.1 Clock structure .............................................................................................................. 33
8.3.2 Clock Generation .......................................................................................................... 33
8.3.3 Clock mode.................................................................................................................... 33
8.3.4 DAC_MCLK and I2S_MCLK mode control.................................................................. 33
8.3.5 PLL configuration ......................................................................................................... 34
8.4 RESET SCHEME .............................................................................................................. 34
8.5 INTERRUPT MODULE (INT) ............................................................................................ 34
8.5.1 Interrupt register ........................................................................................................... 34
8.5.2 Example of Serial interrupt processing flow:................................................................ 35
8.6 I2S INTERFACE .............................................................................................................. 35
8.6.1 I2S Master mode ........................................................................................................... 36
8.6.2 I2S Slave mode1 ............................................................................................................ 36
8.6.3 I2S slave mode2 ............................................................................................................ 36
9 WORK MODE AND POWER MANAGEMENT..............................................................37
9.1 OVERVIEW ..................................................................................................................... 37
9.2 WORKING MODE ............................................................................................................ 38
9.3 CHIP LEVEL OPERATION FLOW ....................................................................................... 38
9.3.1 Power Down to Standby mode ...................................................................................... 38
9.3.2 Standby mode to idle mode............................................................................................ 39
9.3.3 Idle mode to Normal mode ............................................................................................ 39
9.3.4 Normal mode to idle mode ............................................................................................ 39
9.3.5 Idle mode to Standby mode ........................................................................................... 40
Page 2 of 62 VC918 Datasheet Detail 1.1
Confidential Preliminary
Magpie
9.3.6 Clock start sequence in PLL working............................................................................ 40
9.3.7 Clock stop sequence in PLL bypass mode..................................................................... 40
9.3.8 Clock start sequence in PLL bypass mode .................................................................... 40
9.3.9 Clock stop sequence in PLL bypass mode..................................................................... 40
10 PERIPHERAL CIRCUIT ....................................................................................................40
10.1 LED CONTROL DESCRIPTION ......................................................................................... 41
10.2 VIBRATOR CONTROL ...................................................................................................... 44
10.3 MODE CONTROL ............................................................................................................ 48
10.4 CHANNEL SYNCHRONIZE CONTROL ............................................................................... 48
10.5 PIN MAPPING AND CONTROL REGISTER .......................................................................... 48
10.6 CIRCUIT EXAMPLE ......................................................................................................... 49
11 AUDIO PLAY BACK ...........................................................................................................49
11.1 MIDI PLAY BACK ........................................................................................................... 50
11.2 STREAMING PCM/ADPCM PLAY BACK ........................................................................ 51
11.3 REAL TIME EVENT TO COMMAND BUFFER ...................................................................... 52
12 ANALOG APPLICATION GUIDELINE ...........................................................................53
12.1 PLL APPLICATION NOTES .............................................................................................. 53
12.2 PR1 APPLICATION NOTES .............................................................................................. 53
12.3 PR2 APPLICATION NOTES .............................................................................................. 53
12.4 AUDIO DAC APPLICATION NOTES ................................................................................. 54
12.4.1 DAC peripheral connection reference schematic.......................................................... 54
12.4.2 References pins.............................................................................................................. 54
12.4.3 Power supply pins ......................................................................................................... 54
12.4.4 Analog outputs .............................................................................................................. 54
12.4.5 Control register for adjust DAC.................................................................................... 55
12.5 AUDIO POWER AMPLIFIER APPLICATION NOTES ........................................................... 56
12.5.1 Power amplifier peripheral connection ........................................................................ 56
12.5.2 PA feature highlight....................................................................................................... 56
13 ELECTRICAL CHARACTERISTICS...............................................................................58
13.1 ABSOLUTE MAXIMUM RANGE ........................................................................................ 58
13.2 DC CHARACTERISTICS .................................................................................................. 58
13.3 DIGITAL AC CHARACTERISTICS..................................................................................... 58
13.4 ANALOG CHARACTERISTICS .......................................................................................... 58
13.4.1 PLL AC Characteristics ................................................................................................ 58
13.4.2 Power Regulator Characteristics.................................................................................. 59
13.4.3 Audio DAC Characteristics........................................................................................... 59
13.4.4 Speaker Power Amplifier .............................................................................................. 60
13.5 POWER CONSUMPTION .................................................................................................. 61
14 MECHANICAL DIMENSIONS ..........................................................................................62
Page 3 of 62 VC918 Datasheet Detail 1.1
Confidential Preliminary
Magpie
1 Overview
VC0918 is a high-quality, low-power single-chip audio processor, specially designed to provide crispy
music ring tones and rich game sounds for mobile phones. The chip integrates 40-polyphony
Wavetable MIDI synthesizer, full MIDI GM Preset ROM, 16-bit 48 KHz Delta-Sigma DAC, Stereo
Headphone driver and Speaker Power Amplifier into a 6.5mm x 5.5mm LPCC Package. VC0918
supports SMF (Standard MIDI Format), VMD (Versatile MIDI). While generating MIDI music,
VC0918 can also play real-time Audio Stream in PCM or ADPCM format.
With a built-in Stereo DAC and Speaker Power Amplifier, VC0918 is a complete Mobile Audio
sub-system providing total solution for applications like Polyphonic Ring Tone, Game Background
Music, Streaming Audio Playback, etc. For product differentiation purpose, VC0918 also offers
several extra features, Vibrator controlled by Rhythm, RGB color LED controlled by Rhythm and
Caller ID, Hands-free Operation, Streaming Media Playback to Stereo Headphone, etc. VC0918
comes up with a small 40-pin LPCC package.
2 Features
General