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RCA for '80
`Dynamic Detail Processing'
A comb filter using a new
charge -coupled device IC, SOUND SYNTHESIS
synthesis sound (simulated 1;;EVI
45MHz
FIX IF
SOUND DET
VIDEO DET
SOUND
IF
DEMOD
AMP
,111. SOUND
( 3211
SPEAKERS
stereo effect) and a AFT +23V +23V
AFT
countdown vertical sweep are AGC
AGC -4.+23V
CHROMA AU7
major features of RCA's new SYNC SEP 3.58 OSC COLOR
+11V
=
RY KINE DRIVERS
top of the line chassis, the CHROMA
B -Y
PICTURE
TUBE
CTC101. SYNC
COMB FILTER
VERT PEAKING PW 5000 f.
VIDEO BRT VIDEO
Co/orTrali LIMITER ,1
B+ LOA CIRCUIT
BRIDGE +23V 1 VIDEO PEAKING +1W +210V p
By Walter H. Schwartz +150V GND +23V f O
ANODE
+23V VOLT
J11.116 VERT
COUNTDOWN
TO FOCUS
OUTPUT
VERY YOKE
X-RAY
The CTC101 is another step in the PROTECT SCREEN
evolution of RCA's single, main circuit +23V +55V +210V HORIZ
IHV T
SECONDARY
KINE FIL
board concept, which they returned to a i WINDINGS +210V
B+ AND +55V
8+ POWER
couple of years ago. There are many REGULATOR
HORIZ
OUTPUT
THEY
,IRARY
PULSE
SUPPLIES 23V
(HORIZ El+)
familiar areas of circuitry and some -10V
TO HORIZ
notably new ones. Starting at the IF input CIRCUITS
REG B
123V B GND AUX PULSES
START
we'll follow the signal covering the new VOLTAGE
OUTPUT SAMPLE
areas of circuitry most thoroughly.
Fig. 1 -Block diagram of the RCA CTC101 series.
Signal processing
The video IF consists of three IC stages processing circuit called the Dynamic exists a "burst" of energy containing the
with sound take off between the second Detail Processor, a comb filter (Fig. 3). video (luminance) information. The
and third stages. The sync/R-F AGC IC This comb filter uses a charge -coupled chroma information also occurs in
shares a package with the first two IF device to achieve the necessary one "bursts" of energy at horizontal rate
amplifiers, and the third IF and the horizontal line (63.5µsec) delay. intervals. However, because of the
4.5MHz amplifier/AFT are in the same In the NTSC interleaved color system, selection of the chroma subcarrier
package. Also in this last IC package are the video signals occur between 0 and frequency (3.58MHz); the energy bursts
the video detector and a video 4.2MHz. The subcarrier is inserted at are offset from the video energy bursts
preamplifier. 3.58MHz and modulated by chroma, by one-half the horizontal rate. Thus, the
producing sidebands which extend chroma information is "interleaved" with
Audio about 1MHz above and below the video information.
Output from the 4.5MHz amplifier is subcarrier. The comb filter operates on two basic
further amplified by a single transistor To keep these sidebands from principles. 1) From one line to the next
stage and fed through a crystal filter to appearing in the picture and generating the video information is basically the
the sound processor IC. This IC (Fig. 2) crosstalk and interference pattern, the same; as the picture is scanned
contains a 4.5MHz IF amplifier and video bandwidth in most receivers is vertically, there is very little change in
limiter, a quadrature detector, a dc limited to approximately 3MHz. This the video information from one
controlled volume attenuator, and a limitation of video bandwidth causes a horizontal line to the next. 2) The chroma
power amplifier, and a power regulator. loss of high frequency detail. The comb information is reversed by 180 degrees
U200 in turn, supplies audio signal to the filter makes it possible to keep the video from one line to the next, so the chroma
MSS001A, Dual Dimension Sound information between 3MHz and 4.2MHz, information on one line is 180 degrees
Module, which consists of two output and restore much picture detail. out of phase with the chroma information
stages fed audio with some phase The relationship between the on the previous line.
difference, each driving its own separate transmitted video information and the The composite video in the comb filter
speaker. scanning rate causes the video circuit is divided three ways. One path is
information to occur in "bursts" of through the 63.5µs (1H) CCD delay,
The comb filter energy at horizontal rate multiples; another is through a luminance
New in the CTC101 is a video every 15.73kHz from 0 to 4MHz there processing channel and the last is
38 / ET/D - November 1979
B GNO GEED NC GNO
lc 31 51 61 8/
REGULATED
POWER
SUPPLY
PW 600 COMB FILTER
.01
THERMAL H
CURRENT
SENSING
SHUTDOWN
AUDIO OUTPUT
POWER
AMP
GNO
13 9 INPUT POWER
7 AMP
GND DETECTOR VOLUME ATTENUATED
CONTROL AUDIO OUT
Fig. 2 -Sound IC block diagram.
CXANNEL
BUNKING Jt/
VIDEO
358 MX
EL-CHROPAP OUTPUT Fig. 3 -Comb filter block diagram.
,ov 10v C27 -E]
10V
C635
REG0..
4
)6v
BUFFER
effp
rev
Re.
C 66i.711
RV. 1 AF 8636 RARE 000 CR51
C63,1 2400 25V 2700 12E0 625 7.
pF f,
I6V
0605
C032
AMP
11
>4
.16v
REG
1503
5F
T16V
sgZE
ACC
-A 00111111.
REG R603
[5,] 20
thIC1011
1/2 :11?"
0603 0604 IOW CS, +11I V
NON LINEAR VERTICAL REOULATO
PROCESSOR 6602
PEAKING 7-2, liav
AMP 0602 CR eol
TRra-
0601
.1sv
0001...csol1n
HEouLATEo-
SOuRCE 100 pF :111,111A A
IV pp VERTICAL 1.
13 25V
-J
VIDEO DETECTOR
ji 0
Fig. 4 -Non Linear processor circuitry. Fig. 5-Chroma IC block diagram
through a chroma channel. signal present at the output of the 1H basically an analog storage
The signal supplied through the delay. However, the color information, semi -conductor. The CCD delay line
luminance processing channel is because of the inversion, is now in used in the CTC101 comb filter consists
amplified by the gain stage and applied phase with the 1 H delayed signal. When of 6831/2 storage elements. The video
to one input of it, the summing (or adder) these two signals are added together, information is "clocked" into these
circuit, the other input to the adder is the the video output is zero, but the chroma elements at a 10.7MHz rate, three times
1 H delayed signal (previous horizontal information is doubled. the chroma subcarrier frequency. As
line). Because the video information The output of the comb filter takes on each 10.7MHz clock pulse occurs, the
from one line to the next is basically the the "comb" effect. The video information video information is sampled, and a
same, the adder will double the energy occurs in groups around "charge" equal to the video information
amplitude of all the in -phase signal multiples of the horizontal rate with is applied to a CCD element.
components. Both signals contain every multiple of one-half the horizontal The action of each CCD element is
chroma information, which is also added rate being reduced to zero and every analogous to a capacitor storing a given
at the summing point of the comb filter. multiple of the horizontal rate being amount of charge. At the application of
However, because of the 180 degree processed to provide maximum output. each clock pulse, the charge in each
phase shift between adjacent lines, the The opposite is true for the color signals, CCD element is shifted to the next
chroma signal is cancelled. This almost every multiple of the horizontal rate element along the line. This information
completely eliminates the chroma being reduced to zero and every multiple is shifted from element to element at a
signals from the combed video of one-half horizontal rate being 10.7MHz rate with each shift
information. processed for maximum output. representing a delay of .0093µs. The
The composite video signal coupled The heart of the comb filter is total number of elements (683.5) times
to the chroma processing stage is first integrated circuit U601-a the delay of each particular element
inverted. It is next passed through an charge -coupled device which provides (.0093ps) provides a total delay of
amplifier which sets the proper gain, all the functions of comb filtering; it 63.5ps, which is the duration of one
then to one input of another adder provides the delay, the amplifiers for horizontal television scanning line.
circuit. video and chroma processing channels, U601 is powered from several power
Now inverted, the video signal present and the summing circuits. supplies. These are: regulated 16
at this point is out of phase with the video The charge -coupled device is volts B+ via pin 22; 9.1 volts B+ via pin
ETD - November 1979 / 39
9; -5 volts B- via pins 1, 5, 6, and 7. Video amplified signal will not be sufficient to detail signal at the emitter of Q605, the
information is coupled into U601 at pin turn CR603/CR605 'on,' some signal will "Y" amplifier. The rest of the luminance
11. The 10.7MHz clock pulse, pass due to R633. As the input signal circuitry resembles closely that of
developed from a 3.58MHz chroma strength increases above 5IRE, diodes previous modular ColorTrak chassis.
subcarrier frequency tripler circuit, is CR603/CR605 will begin conducting. As
inserted at pin 3. Pin 21 is the combed they conduct, the signal is fed back to Chroma processing
luminance output; pin 13 is the vertical the base of the nonlinear amplifier Chroma processing circuitry also
detail information output; pin 14 is the through R632 and C634 and to output resembles that of earlier ColorTrak
combed chroma information output. coupling capacitor C635. As the input chassis. A 24 pin IC (Fig. 5) performs
signal further increases above 40IRE, most color functions (there are in the
Video processing diode pair CR602/CR604 will begin chroma only a burst keyer, a chroma
The comb filtering process results in conducting. Their conduction will modify buffer, and the matrix and driver
some loss of video frequencies below the feedback path by paralleling R632 transistors, in addition to the IC). The IC
1MHz. To combat this, video below with another resistor R631. This reduces performs two major functions. One is the
1MHz is amplified by a bandpass amplifier the impedance of the feedback path, regeneration of the 3.58MHz chroma
and added back into the luminance. This reducing the gain of the amplifier. The subcarrier. The other is the signal
can cause some problems, however; nonlinear processed signal is applied to processing, (amplifiers, demodulators,
some stations transmit with minor the base of mixer transistor 0604 matrix amplifiers and drivers for the red,
modulation discrepancies which can, for through capacitor C635 where it is green and blue matrix transistors).
instance, cause a field to field shift in added to the nonpeaked vertical detail
black level. To avoid having this effect signal. The nonlinear processed signal Sweep
appear in the picture, the peaking is phase reversed from the vertical detail Both the horizontal and vertical output
automatically varies with video output signal being fed through C670. circuitry are quite similar to earlier
modulation level. This is achieved After these two signals are added chassis. The major development in the
through the use of a non-linear amplifier. together at the base of Q604, a sweep is the use of a horizontal oscillator/
RCA describes the operation of the difference signal will appear at the vertical countdown IC, U400 (Fig. 6).
amplifier as follows (Fig. 4): collector containing only the overshoots The voltage controlled oscillator in
"The gain of the circuit, Nonlinear (or peaking information) with no other U400 operates at 31.468 kHz, twice the
Processor Q603, is determined by the vertical detail restoration signals being horizontal rate (so it can be divided
ac modulation level of the input signal present. The peaking signal (overshoot) neatly by 525 for the vertical rate) and is
and feedback paths via CR603/CR605 is coupled to the video summing divided by two before being fed to a
and CR602/CR604. The output of the transistor Q605 through C635." buffer stage and the horizontal driver.
amplifier appears at the junction of the The luminance signal is developed by The vertical countdown is a two -mode
diode pairs. The output will be small for summing the combed luminance, the system. One mode is the countdown
input signals below 5IRE, because the vertical detail signal and the peaked operation, the other is a sync operation.
VERTICAL COUNTDOWN
Fig. 6-Horizontal oscillator/vertical 10 -STAGE RS
countdown IC block diagram. COUNTER
FLOP
Alm COINCIDENCE
TOGGLE
FLIP-
FLOP
t
a -STAGE VERT
SHIFTER BUFFER
U400
TO BASE
0406
HORIZONTAL
BUFFER
144
4-93V
REG.
"V, 23V
VCO
It (CLOCK)
'0 t HANLE ILL
510111. TIME
C °NS, ANT
SHORT IC TO TC1 R4SS
AGO REMOVE 8425 TO SSV P P
AND C44- IC 7Et.
DE
HORIZ PULSE
R4 5 HORIZONTAL OSCILLATOR
r s HURIZONTAL
LIf
RLA6
'OA 44
PAM FOR
HORIZONTAL ,As, 1 44 SLOWLY
AREO,IENC
4.11. ST OW, SYNC
40 / ETID - November 1979
The two modes of operation allow the checks for coincidence of the 525 count there will be a logic "1" on the "No" line
system to be compatible with and sync. As long as coincidence clearing the 3 -bit counter and keeping
nonstandard sync signals. The IC occurs, the coincidence gate clears the the circuit in the sync mode. If
internally switches between the two 3 -bit counter, allowing the 525 count to coincidence does occur, the output on
modes of operation depending upon the trigger an output pulse through the OR the "No" line will be "0," which
type of signal being received. Mode gate and R -S flip-flop, completing the eventually allows the 3 -bit counter to
switching occurs after eight consecutive cycle. increment by 1. However, operation
cycles of receiving vertical sync that is If no vertical sync is being received by continues in the sync mode until the 3 -bit
either in coincidence or not in coindence the countdown IC, the second input to counter receives eight input pulses at
with the 525 count from the countdown the AND gate remains at logic "0." This which time it triggers the toggle flip-flop
system. means that the one input to the changing the mode of operation back
The countdown IC uses logic circuits coincidence gate stays at logic "0." into the countdown mode.
to achieve the necessary functions. The Therefore, when the 525 count is The 3 -bit counter, which governs the
operation of the vertical countdown reached and applied to the coincidence switching between the two modes of
circuit operating in the countdown mode gate, the coincidence gate develops a operations, prevents switching between
with an NTSC signal present is as "1" on the "No" line and a "0" on the the two modes due to transient noise by
follows: A 10 -stage counter counts "Yes" line. This will not clear the 3 -bit requiring eight consecutive cycles of
every clock pulse from the 31.5kHz counter. As before, the 525 count line coincidence or noncoincidence before
VCO. After the counter has received 512 energizes the R -S flip-flop through the the changing modes of operation.
clock pulses, the greater than or equal to OR gate. The flip-flop again drives the
512 count line goes high, or to a logic output buffer stage and also sets a "1" Power supplies
"1." This places a logic "1" at one input into the 3 -bit counter stage. Also, the The power supply circuitry of the
of an AND gate. The other input of the output of the OR gate resets the CTC101 follows the pattern of that of
AND gate remains at zero until vertical 10 -stage counter to "O." Again, after 16 earlier chassis. A non -isolated,
sync occurs. When vertical sync occurs, counts, the R -S flip-flop is reset, bridge -rectified +150V supply is the
both inputs to the AND gate are ones, terminating the vertical output pulse. basic source of power for the CTC101
providing a "1" at the output which is This cycle continues until the 3 -bit and supplies the horizontal output
supplied to one input of the coincidence counter counts eight occurrences of no through a regulator which operates at
gate. The other input of the coincidence vertical sync occurring (indicated by the +123V. The remainder of the operating
gate is received from the 525 count line lack of a clear pulse on the "Yes" line of voltages are scan derived.
of the 10 -stage counter. With the the coincidence gate). After receiving
presence of an NTSC sync signal, the the eight consecutive pulses without Service
525 count line goes to a "1" at the same being cleared, the 3 -bit counter Service has been facilitated by a logical
time vertical sync occurs. This provides energizes the toggle flip-flop which shifts chassis layout, with circuit areas
a "1" at both inputs of the coincidence the mode of operation from the differentiated. The chassis is "road
gate causing a "1" to occur on the "Yes" countdown mode to the sync mode. mapped" and components are
line of the coincidence gate. This "1" is Vertical is then initiated by the designated and tabled. Component
applied to the clear line of a 3 -bit occurrence of vertical sync. If no vertical numbers correspond to the following
counter-clearing the counter-thus sync is present, the countdown circuit circuit areas:
keeping the toggle flip-flop from will "freerun." The OR gate, which 100 series -ac input, voltage regulator
changing states. triggers the output generating R -S and major transformers
In addition to feed an input to the flip-flop has two inputs-the output of 200 series -sound processing
coincidence gate, the 525 count line the AND gate and the 10 -stage counter 300 series-IF/AFT, AGC and sync
data is also supplied to one input of a 544 count line. With no incoming vertical processing
two -input OR gate. The output of the OR sync present, the AND gate will 400 series -horizontal deflection, X-ray
gate is coupled to an R -S flip-flop generate no output pulses; therefore, detection, pincushion processing
causing the output of the flip-flop to the OR gate will be activated by the 544 500 series -vertical deflection
change state (set) generating a vertical count line only. 600 series -dynamic detail processor
pulse via the output buffer stage. The If a nonstandard or a non-NTSC sync (comb filter)
pulse to the output buffer stage is also system is being received by the 700 series -luminance processing
counted by the 3 -bit counter. The logic instrument, the AND gate provides a -1" 800 series-chroma processing
"1" pulse at the output of the OR gate is pulse to the OR gate, provided that sync 4100 series -auxiliary control assembly
also coupled back to the reset line of the occurs between the 512 and 544 counts. mounted components
10 -stage counter forcing it to reset to a If sync does not occur before the 544 4200 series -auxiliary controls
"0" count. count, the 10 -stage counter is reset, 5000 series-kine drive circuits
The 10 -stage counter again begins. starting the cycle over. When vertical The CTC101 chassis has two ground
counting the clock pulses. After it has sync occurs, it causes a "1" pulse at the systems. The main chassis (isolated
counted the 16th clock pulse, the 16 input of the AND gate (the other input is ground) and a heat sink panel on the
count line goes to a logic "1." This line is supplied by the 512 count line). The right side of the chassis (hot ground).
connected to the R -S flip-flop, resetting resultant "1" at the output of the AND This heat sink panel is ground for the
the flip-flop; thus, the length of the gate is applied to the coincidence gate +123V regulator and the horizontal
vertical output pulse is 16 clock counts. and the OR gate generating a vertical output circuit. (Again, remember, this is
As long as an NTSC signal is being output pulse. always hot to earth ground; use an
received, the operation of the The coincidence gate compares the isolation transformer.) The remainder of
countdown remains in this mode. On occurrence of vertical sync to the 525 the supplies are referenced to isolated
every 525th count, the countdown circuit count line. If coincidence does not occur, ground. ETD
ETID - November 1979 141