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Programmes After Market Services (P.A.M.S.) Technical Documentation NME­2A Series Transceivers

Chapter 1 System Module GM8

Original 08/97

NME­2A System Module GM8

P.A.M.S. Technical Documentation

CHAPTER 4 ­ SYSTEM MODULE GM8 CONTENTS Page No
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External and Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM Card Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Names of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset and Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTRLU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Signals of CTRLU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Signals of CTRLU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bidirectional Signals of CTRLU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Signals of PWRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Signals of PWRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Components of DSPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Signals of DSPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Signals of DSPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bidirectional Signals of DSPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description of DSPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4­5 4­5 4­5 4­6 4­6 4­7 4­8 4­9 4 ­ 13 4 ­ 13 4 ­ 13 4 ­ 14 4 ­ 15 4 ­ 16 4 ­ 17 4 ­ 17 4 ­ 18 4 ­ 19 4 ­ 19 4 ­ 19 4 ­ 21 4 ­ 21 4 ­ 21 4 ­ 22 4 ­ 22 4 ­ 23 4 ­ 24 4 ­ 25 4 ­ 25 4 ­ 25 4 ­ 26

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NME­2A System Module GM8

AUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Components of AUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Signals of AUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Signals of AUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description of AUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Components of ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Signals of ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Signals of ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bidirectional Signals of ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description of ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Components of RFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Signals of RFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Signals of RFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bidirectional Signals of RFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description of RFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duplex Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre­Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Interstage Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Second LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . First Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . First IF Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . First IF Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver IF IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Second IF Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Second IF Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Up Conversion Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX interstage Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 ­ 26 4 ­ 27 4 ­ 27 4 ­ 27 4 ­ 28 4 ­ 28 4 ­ 28 4 ­ 29 4 ­ 29 4 ­ 31 4 ­ 31 4 ­ 33 4 ­ 336 4 ­ 33 4 ­ 34 4 ­ 34 4 ­ 34 4 ­ 35 4 ­ 35 4 ­ 35 4 ­ 35 4 ­ 36 4 ­ 36 4 ­ 37 4 ­ 37 4 ­ 38 4 ­ 38 4 ­ 39 4 ­ 39 4 ­ 40 4 ­ 40 4 ­ 41 4 ­ 41 4 ­ 42 4 ­ 43 4 ­ 43 4 ­ 44 4 ­ 44

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TX Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 45 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 45 Power Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 46 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 46 VCTCXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 47 VHF PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 48 VHF VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 48 UHF Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 49 UHF VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 49 UHF VCO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 50 PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 50 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 51 Part List of GM8 (EDMS Issue: 2.6 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 70

List of Figures
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 14 Reset & Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 15 Watchdog System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 16 Interconnection Diagram ­ Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 52 Power Distribution Diagram ­ Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 53 Block Diagram ­ Diagram of RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 54 Power Distribution ­ Diagram of RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 55 Interconnections ­ RF and BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 56 Block Diagram of Baseband (Version: 1.0 Edit: 192) . . . . . . . . . . . . . . . . . . 4 ­ 57 Circuit Diagram of MCU & Memories (Version: 1.0 Edit: 3) . . . . . . . . . . . . 4 ­ 58 Circuit Diagram of Power Supply (Version: 1.0 Edit 16) . . . . . . . . . . . . . . . . 4 ­ 59 Circuit Diagram of DSPU (Version:1.0 Edit 4) . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 60 Circuit Diagram of Audio (Version: 1.0 Edit 6) . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 61 Circuit Diagram of ASIC (Version: 1.0 Edit 15) . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 62 Circuit Diagram of RFI (Version: 1.0 Edit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 63 Block Diagram of RF (Version: 1.0 Edit 70) . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 64 Circuit Diagram of Receiver (Version: 1.0 Edit 208) . . . . . . . . . . . . . . . . . . . 4 ­ 65 Circuit Diagram of Transmitter (Version: 4.3 Edit 220) . . . . . . . . . . . . . . . . . 4 ­ 66 Circuit Diagram of Synthesizers (Version: 0.0 Edit 116) . . . . . . . . . . . . . . . . 4 ­ 67 Component Layout Diagram of Side 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 68 Component Layout Diagram of Side 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ­ 69

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NME­2A System Module GM8

Introduction
System Module GM8 is the baseband/RF module NME­2A cellular tranceiver. The GM8 module carries out all the system and RF functions of the tranceiver. System module GM8 is designed for a mobile phone, that operate in GSM system.

Technical Specifications
The entire transceiver is built on a single multilayer PCB. This board is enclosed in a housing consisting of a metal bottom part and a metallized top plastic part. The housing has walls to separate baseband from RF.

Modes of Operation
There are three different operation modes: ­ active mode ­ idle mode ­ power off mode In the active state all circuits are powered and part of the module may be in idle mode. The module is usually in the idle mode when there is no call and the phone is in SERV. In the idle mode circuits are reset, powered down and clocks are stopped or the frequency reduced. All the clocks except the main clock from VCTCXO can be stopped in that mode. Whether the SIM clock is stopped or not depends on the network. Currently the MCU only goes into sleep mode when in IDLE, not to MCU standby mode as the time to wake the SW is too long. In power off mode all circuits are disabled. Power is turned on and off by pressing the on/off key on the handset which activates a power FET on the transceiver. The power FET enables power to the handset and the transceiver. The Ignition Sense circuit will (when connected) turn the phone on when IGNS input goes high. This circuit is active for approximately 200ms. which is ample time for the phone to turn on.

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External and Internal Connections
The transceiver has three connectors, a 25 pole connector which basically implements the VDA recommendation for a GSM mobile phone, the antenna connector and a 16 pole connector for the Data Transfer implementing the M2BUS, the D­BUS and Flash programming. All internal connections on the board are by PCB wiring. The SIM card reader is soldered to the board. System Connector Pin: 1 2 3, 17 4, 16 5 Name: MIC NC RFGND VBATT IGNS Description: Handset mic Not used Battery GND Battery voltage · nominal voltage: 13.2 V IGNS input · when IGNS goes from low to high voltage the radio will be turned on Earphone signal · signal to handset pin 8 No connection Handset ground · handset connector pin 2 Antenna control · phone off: · phone on: · min ext load: · IMAX:

6 7 8 9

EAR NC RFGND AUTO ANTENNA

0...0.3 V VBATT 80 200 mA

10

CRM

CRM car radio mute 0...0.3 V · during a call: · standby mode: VBATT · min ext load: 80 200 mA · IMAX: M2BUS · handset pin 3, in parallel with pin 5 of data connector Not connected Not connected

11

MBUS

12 13

NC NC

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Pin: 14 15 18

Name: RFGND MIC_HF XPWRON

Description: HF Mic ground External HF microphone Power on/off control 0...0.2...0.7 V · input low: · connected to switch transistor pulled high to VBATT Audio to HF/handset speaker · impedance min: 3 4W · power max: Shielding Not connected Not connected Switched VBATT supply for handset · for HS pin 1 · value: 10.8...13.2...15.6 V Analog GND HF speaker ground

19

LSP

20 21 22 23

Shield GND NC NC VBSW_1

24 25 SIM Card Reader

AGND LSPGND

Pin Symbol: 1 2, 6 3 GND VSIM SIMDATA

Description: Ground

Values:

SIM card reader supply voltage · voltage: 4.5...4.65...4.8 V Data for SIM card · state "1": · state "0":

3.6...4.65...4.8 V 0...0.2...0.7V

4

SIMCLK

Clock for SIM card 3.6...4.65...4.8 V · state "1": · state "0": 0...0.2...0.7 V Reset for SIM card 3.6...4.65...4.8 V · output high: · output low: 0...0.2...0.7V Signal to ASIC · card not present: 3.6...4.65...4.8 V · card present: 0...0.2...0.7V Page 1 ­ 7

5

SIMRESET

7

CARDDET

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Data Connector Pin: 1, 9 2 Name: DGND MMODE Description Digital ground Minimum mode, input line Connect to DGND for normal operation. Connect to M2BUS before power­on when flash programming. Analog ground Transmitted DBUS data to the data card. 3.6...4.65...4.8 V · state "1": · state "0": 0...0.2...0.7 V Serial bidirectional data and control between the phone and accessories. Flash loading data from programmer 0...0.2...0.7 V · input low level: · input high level: 3.6...4.65...4.8 V Flash acknowledge data to programmer · output low level: 0...0.2...0.7 V · output high level: 3.6...4.65...4.8 V No connection No connection DBUS data bit sync 8 kHz clock. · high level: 3.6...4.65...4.8 V · low level: 0...0.2...0.7 V DBUS received data from data card. 3.6...4.65...4.8 V · state "1": · state "0": 0...0.2...0.7 V Not used. Programming voltage for flash. 11.4...12...12.6 V · value: DBUS data 512 kHz clock. 3.6...4.65...4.8 V · state "1": · state "0": 0...0.2...0.7 V Value

3 4

AGND TDA

5

M2BUS

6

RXD2

7

TXD2

8, 16 10 11

NC NC DSYNC

12

RDA

13 14 15

NC VF DCLK

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NME­2A System Module GM8

Internal Signals Symbol: SCLK Description: Synthesizer clock · load impedance: · frequency: Synthesizer data · load impedance: · data rate frequency: Synthesizer enable · PLL contr. disabled: · PLL activated: · current: Synthesizer enable · PLL contr. disabled: · PLL activated: · current: RX supply voltage on/off · RX supply voltage on: · RX supply voltage off: · current: Supply voltage on/off · RF regulators on: · RF regulators off: · current: TX supply voltage on/off · TX supply voltage on: · TX supply voltage off: · current: TX enable · transmitter power enable: · transmitter power disable: Values:

10 k 3.25 MHz 10 k 3.25 MHz 4.5...4.65...4.8 V 0...0.2...0.7 V 50 µA 4.5...4.65...4.8 V 0...0.2...0.7 V 50 µA 4.5...4.65...4.8 V 0...0.2...0.7 V 0.5 mA 4.5...4.65...4.8 V 0...0.2...0.7 V 1.0 mA 4.5...4.65...4.8 V 0...0.2...0.7 V 0.5 mA 4.5...4.65...4.8 V 0...0.2...0.7 V

SDATA

SENAR

SENAT

RXPWR

SYNTHPWR

TXPWR

TXP

AFC

Automatic frequency control voltage 0.35...4.35 V · voltage min/max: · resolution: 11 bits · load impedance (dynamic): 10 k TX transmit power control voltage · voltage range min/max: 0.3...4.2 V · impedance: 10 k Page 1 ­ 9

TXC

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Addendum to the Technical Documentation for NME­2A: Chapter 4: Technical Specification System Module GM8S. Internal Signal page 4­9: PA_CO New signals

Power amplifier supply compensation 1k2 ohm 15.6­10.2 Vdc

*Load Impedance

*DC range (VBATT Supply Switched on) PA_ADJ Power control loop DC­ADJ 0.3...4.6 Vdc 10k ohm

*Voltage range *Load Impedance

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NME­2A System Module GM8

Symbol: TXQP,TXQN

Description:

Values:

Differential TX quadrature signal · differential voltage swing: 1.15...1.2...1.25 VPP · d.c. level: 2.30...2.35...2.40 V · load impedance: 30 k Differential TX in phase signal 1.15...1.2...1.25 VPP · differential voltage swing: · d.c. level: 2.30...2.35...2.40 V · load impedance: 30 k Parallel AGC data 4.5...4.65...4.8 V · reduced front end gain: · normal front end gain: 0...0.2...0.7 V · current: 0.1 mA · PDATA1; AGC 3 dB reduction · PDATA2; AGC 6 dB reduction · PDATA3; AGC 12 dB reduction · PDATA4; AGC 24 dB reduction · PDATA5; AGC 12 dB reduction RX quadrature signal · output level: · source impedance: RX in phase signal · output level: · source impedance:

TXIP,TXIN

PDATA0­5

RXQ

15 mVPP 470 15 mVPP 470

RXI

RFC

High stability clock signal for the logic circuits 26 MHz · frequency: · signal amplitude: 1.0 VPP · load resistance: 10 k VCTCXO supply voltage · voltage: · current: Supply voltage for RF · voltage:

VREF

4.55...4.65...4.75 V 2.0 mA 10.8...13.2...15.6 V

VBATT_RF VBATT_I 6V5_RF

Supply voltage for the PA module · voltage: 10.8...13.2...15.6 V Supply voltage for 5 V regulators · voltage: 6.0...6.5...7.0 V

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Symbol: 8V5_RX_TX VAI

Description: Supply voltage for BB · voltage: 8.5 V regulator on/off · logic high "1": · logic low "0":

Values:

7.5...8.3...8.7 V 4.7 V 0V

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NME­2A System Module GM8

Baseband Block Description
General
The purpose of the baseband module is to control the phone, to process audio signals to and from the RF block and to and from the handset/ handsfree transducers. The module also includes a SIM card reader and furnishes external data and control lines.

Names of Functional Blocks
Name: CTRLU PWRU DSPU AUDIO ASIC RFI Function: Control unit for phone Power supply Digital signal processing block Audio coding D2CA GSM/PCN system ASIC; several functions RF baseband interface

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Clocking Scheme
RF System Clock 26 MHz

DSP Clock 60.2 MHz differential sine wave

RFI Clock 13 MHz Sleep Mode: 135.4kHz

RFI

VCTCXO

OSCILLATOR

HSE­6XA
ear mic

AUDIO CODEC

ASIC
DSP

SIMCLK 3.25 / 1.625 MHz

Codec Sync Clock 8 kHz

DBUSCLK 512kHz DBUSSYNC 8kHz

Codec Main Clock and data Transfer clock 512kHz

MCU Clock 26 MHz

MCU

Figure 1.

Clocking Scheme

Most of the clocks are generated from the 26 MHz VCTCXO frequency by the ASIC: ­ 26 MHz clock for the MCU. MCU`s internal clock frequency is half of that. ­ 13 MHz for the RFI. ­ The ASIC also generates 135.4 kHz sleep mode clock for the RFI ­ 3.25 MHz clock for SIM. When there is no data transfer between the SIM card and the phone the clock can be reduced to 1.625 MHz. Some SIM cards also allows the clock to be stopped in that mode. ­ 512 kHz main clock for the codec and for the data transfer between the DSP and the codec. ­ 8 kHz synchronization clock for data transfer between the DSP and the codec. ­ 512 kHz clock and 8 kHz sync. clock for the DBUS data transfer.

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The DSP has its own crystal oscillator. The DSP uses differential sinusoidal clock. The frequency is 60.2 MHz. The DSP clock buffer can be powered down via ASIC. The ASIC MCU generates 8 kHz clock to the codec for the control data transfer. In the idle mode all the clocks can be stopped except 26 MHz main clock coming from the VCTCXO. The VCTCXO signal is buffered to limit frequency pulling caused by the baseband circuits.

Reset and Power Control

CAR BATT VOLTAGE 10.8­­15.6 MIN / MAX

RFI

+­
OVER/ UNDER VOLTAGE DETECT+ reset in Reset Out Reset Out

RF PA

ASIC
DSP Vcc Reset in

SIMReset

resetreg

pre volt regulator

xpwron +­

tx off
XPWRON

HSE ­6XA
handset

on/off
PSL+
VL1 XRES reset in

on/off
IGNS

XPwrOff

approx 2Hz

MCU

Figure 2.

Reset & Power Control

There are two different ways to switch power on: ­ Pushing the on/off button of the handset the effect of which is to ground the input pin XPWRON of the System Connector or ­ Pulling the input IGNS high.

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All devices are powered up at the same time. The PSL+ supplies the reset to the ASIC at power up. The ASIC start delivering clock signals the to the DSP and the MCU. After about 20 µs the ASIC releases the resets to MCU, RFI and DSP. MCU and RFI reset is released after 256 13 MHz clock cycles. DSP reset release time from DSP clock activation can be selected from 0 to 255 13MHz clock cycles. In our case it is 255. SIM reset release time is according to GSM SIM specifications. To turn off power for the phone, the user presses the on/off key (or turns off the ignition key of the car). The MCU detects this. The MCU cuts off any ongoing call, exits all tasks, acts inoperative to the user and stops the PSL+ watchdog without resets. After power­down delay, the PSL+ cuts off the supply from all circuitry. When the IGNS line is connected the phone will turn on when this line goes high. The IGNS circuit pulls the XPWRON low for a approx. 200 msec as if the handset on/off button was being pushed. The power may be turned off by sending a turn off command on the M2BUS from handset or through the Data Connector. In the User Interface SW an automatic shutdown feature will be implemented. When no activity have been observed for a user settable period. the phone will turn off thus limiting the risk of draining the car battery.

Watchdog System
4

VBATT GND
PRE REG

reset

DSP

1
ASIC

1 4 5
POWER

2

PSL+

reset

3
XPWROFF

MCU

Figure 3.

Watchdog System

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Normal operation: ­ 1. MCU tests DSP ­ 2. MCU updates ASIC watchdog timer (> 2 Hz) ­ 3. MCU pulses the XPWROFF input on the PSL+ (about 2 Hz) Failed operation: ­ 4. ASIC resets MCU and DSP after about 0.5 s failure ­ 5. PSL+ switches power off about 1.5 s after the previous XPWROFF pulse

CTRLU
The Control block contains a microcomputer unit (MCU) and three memory circuits (FLASH, SRAM, EEPROM), a 20­bit address bus and an 8­bit data bus. Main Features of the CTRLU Block MCU functions: ­ system control ­ communication control ­ handset interface functions ­ authentication ­ RF monitoring ­ power up/down control ­ self­test and production testing ­ flash loading Main Components ­ Hitachi H8/536 H8/536 is a CMOS microcomputer unit (MCU) comprising a CPU core and on­chip supporting modules with 16­bit architecture. The data bus to outside world has 8 bits. ­ 1024k*8bit FLASH memory 100 ns maximum read access time contains the main program code for the MCU; part of the DSP program code also located on FLASH ASIC can address two 4 Mbit memories or one 8 Mbit memory. ­ 32k*8bit SRAM memory 100 ns maximum read access time

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­ 8k*8bit EEPROM memory 150 ns maximum read access time contains user defined information there is a register bit on the ASIC which must be set before the write operation to the EEPROM. Input Signals of CTRLU Name(from): VL1(PWRU) VREF(PWRU) Description: Power supply voltage for CTRLU block Reference voltage for MCU A/D converter

EROMSELX(ASIC) Chip select for the EEPROM memory ROMSELX(ASIC) ROMAD18(ASIC) RAMSELX(ASIC) RESETX(ASIC) NMI(ASIC) MCUCLK(ASIC) IRQX(ASIC) Chip select for the FLASH memory Chip select for the FLASH memory (FLASH1) Chip select for the SRAM memory Reset signal for MCU Non­maskable interrupt request Main clock for MCU Interrupt request

PCMCDO(AUDIO) Audio codec control data receiving TRF(RF) VF(data conn.) RXD2 (data conn.) MMODE RF module temperature detection Programming voltage for FLASH memory The use of handsfree monitoring FLASH programming data input on the production line Minimum mode for FLASH programming

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Output Signals of CTRLU Name(to): Description:

XPWROFF(PWRU) Power off control, PSL+ watchdog reset WSTROBEX(ASIC) MCU write strobe RSTROBEX(ASIC) MCU read strobe MCUAD(19:0)(ASIC) 20 bit MCU address bus MBUSDET(ASIC) PCMCLK(AUDIO) PCMCDI(AUDIO) MBUS activity detection Clock for audio cedec control data transfer Audio codec control data transmitting

XSELPCMC(AUDIO) Chip select for audio codec TXD2 (data connector) Verification output of the programmed data of FLASH during programming

Bidirectional Signals of CTRLU Name(to/from): Description:

MCUDA(7;0)(ASIC) MCU's 8 bit data bus M2BUS Asynchronous serial data bus

Block Description ­ MCU ­ memories The MCU has a 20 bits wide address bus A(19:0) and an 8­bit data bus with memories. The address bits A(19:16) are used for chip select decoding. The decoding is done in the ESA ASIC. The ASIC can address two 4 Mbit (or smaller) or one 8 Mbit flash memories. Hitachi HD647536 processor has internal ROM and RAM memories. ­ Flash programming In flash programming a special flash programming box and a PC is needed. Loading is done through the 16 pole Data Connector of the mobile phone. First MCU goes to minimum mode (MBUS command from PC or if MBUS is connected to MMODE line during power up). Then the flash software is loaded from PC to flash loading box. When the loading is complete, flash loading to mobile can be started by MBUS command from PC to the MCU. After that the MCU asks the test box to start flash loading to mobile. The box supplies 12 V programming voltage for flash and starts to send 250 bytes data blocks to the MCU via RXD2 line. The baud rate is 406 kbit/s. The MCU calculates the check sum,

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­

­

­

­

­

­

sends acknowledge via TXD2 line and sends the data to flash. When all the data are loaded the mobile resets and tells the flash loading box if the loading was successful or not. CTRLU ­ PWRU MCU controls the watchdog timer in PSL+. It sends a positive pulse at a rate of approximately 2 Hz to XPWROFF pin of the PSL+ to keep the power on. If MCU fails to deliver this pulse, the PSL+ will remove power from the system. When power off is requested by the user or by the MCU SW, (UI SW or CS SW), the MCU leaves the PSL+ watchdog without reset pulses. After the watchdog time has elapsed the PSL+ cuts off the supply voltages from the phone. CTRLU ­ ASIC MCU and ASIC have a common 8­bit data bus and a 9­bit address bus. Bits A(4:0) are used for normal addressing whereas bits A(19:16) are decoded in ASIC to chip select inputs for CTRLU memories. ASIC controls the main clock, main reset and interrupts to MCU. The internal clock of MCU is half the MCUCLK clock speed. RESETX (produced by ASIC) resets everything in MCU except the contents of the RAM. IRQX is a general purpose interrupt request line from ASIC. After IRQX request the interrupt register of the ASIC is read to find out the reason for interrupt. NMI interrupt is used only to wake up MCU from software standby mode. CTRLU ­ DSPU MCU and DSP communicate through the ASIC. ASIC has an MCU mailbox and a DSP mailbox. MCU writes data to DSP mailbox where DSP can only read the incoming data. In MCU mailbox the data transfer direction is the opposite. When power is switched on the MCU loads data from the Flash memory to the DSP`s external program memory through this mailbox. CTRLU ­ AUDIO When the the chip select signal XSELPCMC goes low, MCU writes or reads control data to or from the speech codec registers at the rate defined by PCMCLK. PCMCDI is an output data line from MCU to codec and PCMCDO is an input data line from codec to MCU. The data and control flows on separate serial busses. CTRLU ­ RF MCU has internal 8 channel 10 bit AD converter. Following signals are used to monitor RF: TRF RF temperature (currently not in use) CTRLU ­ ACCESSORIES M2BUS is used to control external accessories. This interface can also be used for factory testing and maintenance purposes.

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­ MINIMUM ­ MODE This special mode can be reached through a M2BUS command or by connecting the pin MMODE of the Data Connector to the M2BUS while the phone is powered up.

PWRU
The protection against overvoltage or wrong polarity on the supply lines is included in this block which further creates the supply voltages for the baseband block, for the RF synthesizer and switches the supply to the handset and audio power amplifier. Main Components ­ Pre regulator Stabilizes the input supply voltage to 6.5 V for the PSL+and supplies regulated power for RF module. ­ PSL+ and ASIC Generates voltages for baseband and reset signal for the ASIC. Contains power on switch, supply voltage detector and watchdog. ­ Supply voltage monitor Supervises the supply voltage within the specified Window. ­ Power switch Switches on the supply voltage for the pre­regulator handset and audio power amplifier. Input Signals of PWRU Name(from): Description:

XPWRON(handset) Power on/off button of handset (or IGNS sense ON signal) XPWROFF(CTRLU) Power off control, watchdog pulses from MCU VBATT(sys.conn) 8V5_RX_X(RF) IGNS(sys.conn.) Car battery voltage Regulated voltage from RF module Ignition sense from car ignition key

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Output Signals of PWRU Name(from): XRES(ASIC) VL1(CTRLU, ASIC,RFI) VL2(DSPU) VA1(AUDIO,UIF) VA2(RFI) Description: Master reset Logic supply voltage Logic supply voltage Analog supply voltage Analog supply voltage

VREF(CTRLU,RF) Reference voltage 4.65 V ±2 % VBATT_RF (RF; TX+RX) VBSW_I(data conn) 6V5_RF VBATT_I(RF PA) VBDET(ASIC) IGNDET(ASIC) PAOFF(RF PA) ANTC(sys.conn) Block Description The PSL+ IC produces the following regulated supply voltages: ­ 2 * VL 150 mA for logic ­ VA1 ­ VA2 ­ VREF 40 mA for audios 80 mA for RFI 5 mA reference Supply for RF regulators VBATT switched for LF amplifier and for the handset Regulated supply of the baseband that supplies power to(RF synth,TX) a part of the RF module too Battery voltage to RF PA, fused and protected against overvoltage Indicates VBATT is within window allowing transmission Indicates logic level of ignition sense input line Disables RF PA when supply voltage is outside the allowed window Antenna control, current limited output that follows VBATT

In addition it has internal watchdog voltage detection. The watchdog will cut off output voltages if it is not reset once every 1.5 (±0.75) second. The voltage detector resets the phone if the supply voltage falls below 6.4 V .

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The IGNS input signal from the System Connector is low pass filtered to remove very short pulses and is then fed to a differentiation circuit which will turn the power on by pulling XPWRON low. The filtered IGNS is also fed to the ASIC allowing the MCU SW to monitor the actual logic state of this pin. The IGNS turn on pulse is in the order of 200 msec. When the phone is off no part of the circuit is powered up. The phone can only be powered up by pushing the on/off button or pulling the IGNS line high. When the on/off button is pushed the power FET turns the pre­regulator and PSL+on. The PSL+ keeps the pre­regulator on. The IGNS circuit provides the same effect as pushing the on/off button. The phone is turned off by pushing the on/off button. The handset transmit an off message to the MCU which will stop emitting watchdog pulses for the PSL+. The PSL+ times out and the phone turns off.

DSPU
Main interfaces of the DSP: ­ MCU via ASIC mailbox ­ ASIC ­ audio codec ­ data bus interface (DBUS) for accessories ­ digital audio interface (DAI) for type approval measurements Main features of the DSP block: ­ speech processing ­ speech coding/decoding ­ RPE­LTP­LPC (Regular pulse excitation long term prediction linear predictive coding) ­ voice activity detection (VAD) for discontinuous transmission (DTX) ­ comfort noise generation during silence ­ acoustic echo cancellation ­ channel coding and transmission ­ block coding (with ASIC) ­ convolutional coding ­ interleaving ­ ciphering (with ASIC) ­ burst building and writing it to ASIC

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­ Reception ­ reading the A/D conversion results from ASIC ­ impulse response calculation ­ matched filtering ­ bit detection (with Viterbi on ASIC) ­ de­interleaving of soft decisions ­ convolutional decoding (with Viterbi) ­ block decoding (with ASIC) ­ Adjacent cell monitoring ­ signal strength measurements ­ neighbor timing measurements ­ neighbor parameter reception ­ control functions ­ RF controls ­ synthesizer control ­ power ramp programming ­ automatic gain control (AGC) ­ automatic frequency control (AFC) ­ frame structure control (with ­ controlling the operations during a TDMA frame ASIC) ­ controlling the multi­frame structure ­ channel configuration control ­ test functions ­ functions for RF measurements ­ debugging functions for product development

Main Components of DSPU ­ AT&T DSP 1616­X11 Digital signal processor with 12 kword internal ROM ­ Two 32k *8 70 ns SRAMs for DSP external memory ­ 60.2 MHz crystal oscillator to generate differential small signal clock for the DSP

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Input Signals of DSPU Name(from): VL1(PWRU) VL2(PWRU) Description: Logic supply voltage for DSP clock and buffer Logic supply voltage

DSPCLKEN(ASIC) Clock enable for DSP clock oscillator circuit DSP1RSTX(ASIC) Reset for the DSP PCMDATRCLKX (ASIC) CODEC_CLK PCM data input clock, DBUS data output clock PCM data output clock

PCMOUT(AUDIO) Received audio in PCM format DBUSCLK DBUSSYNC RDA(data conn.) INT0, INT1(ASIC) PCMCOSYCLKX (ASIC) Output Signals of DSPU Name(to): PCMIN(AUDIO) IOX(ASIC) RWX(ASIC) Description: Transmitted audio in PCM format I/O enable, indicates access to DSP address space Read/write X DBUS data output clock DBUS data bit sync clock DBUS received data Interrupts for the DSP PCM data bit sync clock

DSPAD(16;9)(ASIC)Address bus and control signals DBUSDET(ASIC) TDA(data conn.) RDA line for DBUS activity detection by ASIC DBUS transmitted data

Bidirectional Signals of DSPU Name(from/to): Description:

DSPDA(15;0)(ASIC) 16 bit data bus

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Block Description of DSPU The Control unit communicates with the DSP circuitry through a mailbox in the ESA ASIC. The part of the DSP SW that resides in external SRAM is loaded from Flash Prom is software is loaded through this mailbox at start up. The DSP includes two serial busses. One is used for speech data transfer between the DSP and the codec. The other is used as an external data bus and it is connected to the Data Connector. This bus can be used by data accessories and also as a digital audio interface (DAI) in audio type approval measurements. The clocks (512 kHz main clock and 8 kHz sync. clock) are generated by the ASIC. In transmit mode the DSP codes the speech and routes the resulting transmit slots to the ESA. The ESA ASIC controls timing, and at specified intervals sends these bits to the RFI for DA conversion. In digital receive mode the RFI AD converts the IF signal from the RF unit under the control of the ESA. The DSP controls the ESA and receives the converted bits. After channel and speech decoding, bits are converted into an analog signal in the PCM codec, routed and fed to the earpiece/ loudspeaker. The DSP controls the RF module through the ESA ASIC, where all necessary timing functions are implemented, and control I/O lines are provided eg. for synthesizer loading. The DSP emulator can be connected to DSP pins TCK, TMS, TDO, TDI, GND and VDD. The DSP clock buffer can be turned off via a control pin on the ASIC to save current when the DSP clock is not needed.

AUDIO
The AUDIO block consists of an audio codec , conditioning amplifiers for the audio inputs and outputs and a power amplifier for the external loudspeaker. The codec contains microphone and earpiece amplifiers and all the necessary switches for signal routing. The codec is controlled by the MCU. The PCM data comes from and goes to the DSP. The power amplifier drives the external loudspeaker for handsfree function, and a highpass filter removes unwanted low frequency noise picked up by the handsfree microphone.

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Main Components of AUDIO ­ Class B amplifier built using an op amp and discrete power transistors. ­ Audio codec ST5080 ­ Contains: PCM codec, audio routing switches, microphone and earpiece amplifiers for 2 connections (internal and external devices) and DTMF generator. High pass filter/amplifier for the handsfree microphone. Power amplifier for the external handsfree loudspeaker. Input Signals of AUDIO Name(from): VA1(PWRU) VBSW_1(PWRU) PCMIN(DSPU) SYNC(ASIC) Description: Analog supply voltage Switched VBATT supply for the pre­regulator power amplifier (and handset) Received audio in PCM format 8 kHz frame sync

CODEC_CLK(ASIC) 512 kHz codec main clock PCMCDI(CTRLU) Audio codec control data

PCMCLK(CTRLU) Clock for audio codec control data transfer XSELPCMC (CTRLU) Audio codec chip select

HFMIC(syst.conn.) External microphone NOK_OEM(ASIC) MIC(syst.conn) Output Signals of AUDIO Name(to): PCMOUT(DSPU) Description: Transmitted audio in PCM format Control line to set the mic sensitivity according to VDA recommendations Handset microphone

PCMCDO(CTRLU) Audio codec control data EAR(syst.conn.) LSP(syst.conn) Audio to handset Audio to handsfree loudspeaker

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Block Description of AUDIO The handset microphone is connected to the codec through an attenuator. The external handsfree microphone is DC­biased by approx. 8V. The handsfree mic signal is amplified and filtered and fed to the codec. The gain of the ext. microphone input can be selected to one of two settings, one adjusted for the standard Nokia microphone and a less sensitive one adjusted for the VDA recommended sensitivity. The microphone signal is A/D converted in thee PCM codec (A­law) and delivered to the DSP. Digital downlink signal from the DSP is fed to the D/A converter of the codec. After the conversion the signal is low pass filtered and fed to a attenuator operating as volume control and routing switches to direct it to the earpiece of the handset or the power amplifier for the loudspeaker. There are 8 separate volume settings. They cover a range of 15 dB for the earpiece and a range of 31 dB for the handsfree speaker. The audio codec communicates with the DSP (analog speech) through an SIO (signals: PCMIN, SYNC, CODEC_CLK and PCMOUT) . The MCU controls the audio codec function through a separate serial bus (signals: PCMCDO, PCMCDI, PCMCLK and XSELPCMC). Gainsetting, routing , tone generation etc in the codec is controlled through writing to registers in the codec. The 512 kHz clock and 8 kHz sync signal are produced by the ASIC clock signals. The codec generates DTMF tones (key beeps), ringing and warning tones etc. for the external speaker. Some tones come also from the network.

ASIC
The ASIC takes care of the following functions : ­ interface between MCU, DSP and RFI ­ hardware accelerator functions to DSP SW ­ clock generation, clock distribution and clock disable/enable ­ RF controls ­ Timers ­ M2BUS and D­BUS detect and D­BUS clock and sync generation ­ SIM interface ­ Control inputs and outputs for the system connector. Main Components of ASIC ­ ESA ASIC ­ RFC buffer, a package of logic level inverters

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Input Signals of ASIC Name(from): VL1(PWRU) VL2(PWRU) IOX(DSPU) RWX(DSPU) WSTROBEX (CTRLU) RSTROBEX (CTRLU) RFC(RF) XRES(PWRU) Description: Logic supply voltage Logic supply for SIM reader I/O enable, indicates access to DSP address space Read/write X MCU's write strobe MCU's read strobe Reference clock from VCTCXO Master reset Address bus and control signals

DSPAD(16;0)(DSPU)

MCUAD(19;16,4;0) MCU's address bus (CTRLU) DAX(RFI) Data acknowledge

MBUSDET(CTRLU) MBUS activity detection DBUSDET(DSPU) DBUS activity detection IGNDET(PWRU) VBDET(PWRU) transmission SIM_DETECT (SIM reader) PAOFF(PWRU) Output Signals of ASIC Name(to): Description: Logic level of IGNS Indicating VBATT is within window to allow Logic signal indicating that a SIM card is present Indicating that operation of the RF PA stage is disabled

INT0,INT1(DSPU) Interrupts for DSP NMI(CTRLU) IRQX(CTRLU) RESETX (CTRLU,RFI) Not maskable interrupt request Interrupt request Master (power up) reset

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Name(to):

Description:

DSP1RSTX(DSPU) Reset for the DSP WRX(RFI) RDX(RFI) RFIAD(3;0)(RFI) SCLK(RF) SDATA(RF) SENAR(RF) SENAT(RF) RXPWR(RF) TXPWR(RF) SYNTHPWR(RF) TXP(RF) Write strobe Read strobe RFI address bus Synthesizer load clock Synthesizer load data Receiver synthesizer enable Transmit synthesizer enable RX circuitry power enable TX circuitry power enable Synthesizer circuitry power enable Transmit enable

MCUCLK(CTRLU) Main clock for MCU DSPCLKEN(DSPU) DSP clock circuit enable RFICLK(RFI) RFI2CLK(RFI) CODEC_CLK (DSPU,AUDIO) PCMDATRCLKX (DSPU) SYNC(AUDIO) PCMCOSYCLKX (DSPU) DCLK(DSPU) DSYNC(DSPU) SIMCLK(UIF) VSIM(UIF) RFI master clock RFI sleep clock PCM data clock Inverted PCM data clock, used as input clock for codec and DBUS interface Bit sync clock Bit sync clock, inverted DBUS data clock DBUS bit sync clock SIM data clock SIM power control

ROMSELX(CTRLU) Chip select for the FLASH memory ROMAD18 (CTRLU) Chip select for the FLASH memory (FLASH1)

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Name(to): EROMSELX (CTRLU)

Description: Chip select for the EEPROM memory

RAMSELX(CTRLU) Chip select for the SRAM memory CRM(sys.conn) NOKIA_OEM (AUDIO) PA_ADJ EAL(sys.conn) Car radio mute Set ext. mic. sensitivity to VDA recommended value Power adjustment for RF PA. External alert

Bidirectional Signals of ASIC Name(from/to): DSPDA(15;0) (DSPU) MCUDA(7;0) (CTRLU) RFIDA(11;0)(RFI) SIMDATA(UIF) Block Description of ASIC PSL+ supplies the reset to the ASIC at power up. The ASIC starts the clocks to the DSP and the MCU. After about 20 µS the ASIC releases the resets to all circuitry. MCU and RFI reset is released after 256 13 MHz clock cycles. DSP reset release time from DSP clock activation can be selected from 0 to 255 13 MHz clock cycles. In our case 255 is selected. SIM reset release time is according to GSM SIM specifications. Two inverters buffers the 26MHz clock from the VCTCXO to the ASIC to minimize the effect on the clock signal caused by varying load on the clock. In the ASIC the clock is further buffered, divided and gated for the MCU, RFI, SIM. The ASIC. It also generates main and sync clocks for audio codec, DSP`s SIOs and DBUS. The clock outputs can be disabled in order to save current when the clock is not needed. The DSP oscillator buffer can be turned off by the ASIC. Interface to the MCU consists of 8 bit data bus ,5 bit lower address bus, 4 bit upper address bus, RSTRBEX, WSTROBEX, IRQX and NMI. ASIC is in the same memory space as MCU memories (memory mapped on the MCU). The ASIC generates chip select's from the address bits A16­19. There is also M2BUS detector, netfree counter and D­BUS detector in the ASIC. Netfree interrupt IRQX occurs if no activity is detected in M2BUS in about 3 ms. NMI is used to wake up the MCU from sleep mode. Description: 16 bit data bus MCU's 8 bit data bus 12 bit data bus Serial data to SIM

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MCU and DSP communicate through ASIC. ASIC has an MCU mailbox and a DSP mailbox. MCU writes data to DSP mailbox where DSP can only read the incoming data. In MCU mailbox the data transfer direction is the opposite. The size of the mailbox is 64 * 8 bit. The SIM interface is the electrical interface between the smart card used in the GSM and the MCU via the ASIC. ASIC converts the serial data received from the SIM to parallel data for MCU and converts parallel data from MCU to serial mode for the card. The SIM interface also takes care of the power up and down procedure to the card, frame and parity error checking. The communication between card and ASIC is asynchronous and half duplex. Four signals are used between the ASIC and the SIM card: SIMDATA, SIMCLK,SIMRESET and VSIM. The clock frequency is 3.25 MHz. When there is no data transfer between the SIM card and the Mobile the clock can be reduced to 1.625 MHz. Some SIM cards also allows the clock to be stopped in that mode. Supply voltage VSIM can be switched off by the ASIC. The supply voltage is 4.65 V. The carddetect input on the ASIC is connected to the carddetect switch of the SIM reader and when the pin goes low (card not present) the ASIC will drive the SIM Interface down in a controlled and well specified manner. The carddetect switch is activated by the SIM­card and wil open/close while the contacts of the SIM card are engaged with the SIM reader. The interface to the DSP consists of 6 bit address bus, 16 bit data bus, IOX and RWX lines. Data bus is latched using IOX, address bus is not. The ASIC also generates interrupt INT0 when an edge occurs in DBUS line (if the mask bit is off). INT1 is used as RX interrupt and as MFI modulator interrupt to the DSP. The Viterbi block is used to perform GSM/PCN convolutional decoding and bit detection according to viterbi algorithm. It can be controlled and accessed thoroughly by the DSP. Coder is used to perform block encoding, decoding, and ciphering according to GSM algorithm A5 (only A5 not A5­2). The ASIC takes care of the interface between the DSP and the RFI: TX modulator, RX filter, TX and RX sample buffers and controlling state machine. The interface to RFI consists 12 bit data bus, 4 bit address bus, RDX and WRX. There is data acknowledge (DAX) from RFI to ASIC. Also in this block are the serial RF synthesizer interface (SCLK, SDAT) and the digital RF control signals (RXPWR, TXPWR, TXP, SYNTHPWR)

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RFI
The RFI block consists of the RFI ASIC and its reference voltage generator. This block is an interface between the RF and baseband sections. The RFI block has the following functions: ­ Receive and A/D convert the II and Q signals delivered by the IF amplifier of the RF module ­ Produce I and Q TX modulation signals through D/A conversion plus filtering ­ Prepare the Automatic Frequency Control signal via D/A conversion ­ Prepare TX power ramp TXC via D/A conversion ­ Hold AGC setting data in a register Main Components of RFI ­ RFI ASIC ­ 4.096 V external voltage reference LM4040 for RFI Input Signals of RFI Name(from): VL1(PWRU) VA2(PWRU) RESETX(PWRU) Description: Logic supply voltage Analog supply voltage Master (power up) reset

RFIAD(3;0)(ASIC) RFI address bus RDX(ASIC) WRX(ASIC) RFICLK(ASIC) RFI2CLK(ASIC) RXQ(RF) RXI(RF) Read strobe Write strobe RFI master clock RFI sleep clock RX quadrature signal RX in phase signal

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NME­2A System Module GM8

P.A.M.S. Technical Documentation

Output Signals of RFI Name(to): DAX(ASIC) AFC(RF) TXC(RF) TXQP,TXQN(RF) TXIP,TXIN(RF) PDATA(5;0)(RF) VREF_2(PWRU) Bidirectional Signals of RFI Name(to): Description: Description: Data acknowledge Automatic frequency control voltage TX transmit power control voltage Differential TX quadrature signal Differential TX in phase signal Parallel AGC data for controlling the RF AGC amplifiers Reference used by VBATT window comparator

RFIDA(11;0)(ASIC) 12 bit data bus Block Description of RFI The RFI provides A/D conversion of the in­phase (RXI) and quadrature (RXQ) signals in the receive path. It has got 12 bit sigma­delta A/D converters and the sample rate is 541.667 kHz. Analog transmit path includes 8 bit D/A converters to generate the in­phase (TXI) and quadrature (TXQ) signals. RFI has differential outputs for TXI and TXQ. The sample rate is 1.0833 MHz. There is a 11 bit D/A converter for automatic frequency correction. The sample rate is 1.3542 kHz. Power ramp is done with 10 bit D/A converter. The sample frequency is 1.0833 MHz. Digital AGC control is done with PDATA outputs. The RFI has 12 bit data bus to the ASIC. The registers in the RFI are accessed using 4 address bits. Control and clock signals are produced by the ASIC. The RFI has external 4.096 V voltage reference.

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RF Block Description
The RF block carries out all the RF functions of the transceiver. The RF block works in GSM system.

Regulators
There are three regulators in the RF unit. The 1'st regulator is used for the synthesizers. The 2'nd regulator is used for the receiver and the transmitter discrete circuits. The 3'rd regulator (8.3V) is used for the TX ramping circuit and RX amplifiers. The regulators reduce the car supply voltage to the fixed 5.0 V and 8.3 V. The receiver, synthesizer and transmitter circuits can be switched ON and OFF separately. Switching sequence timing depends on the operation mode of the phone.

Power Distribution
All currents in the power distribution diagram (see RF Power Distribution Diagram) are values with the sub modules in "on" condition. Activity percentages in SPEECH mode are 22.5 % for RXPWR, 15.8 % for TXPWR and 100 % for SYNTHPWR. In IDLE mode, activities are 0.36 %, 0.0 % and 1.61 %, respectively. Switching of the supply voltage for each block is controlled independently, and for example TXPWR and RXPWR are not on, at the same time.

Current Consumption
In the following table the RF current consumption can be seen with different status of the control signals. The VCTCXO is not included in the results. SYNTHPWR: RXPWR: TXPWR: TXP: Typ. load Notes: current: 0.1 mA Leakage current 45 mA Synthesizers and VCTCXO active 60 mA Receive mode 4500 mA Transmission

L H

L L

L L

L L

H H

H L

L H

L H

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Receiver
The received RF signal from the antenna is fed via a duplex filter to the receiver unit. The duplex filters receiver branch is a bandpass filter. The signal is amplified by a discrete low noise preamplifier. The gain of the amplifier is controlled by the AGC control line (PDATA0). The nominal gain of 15 dB is reduced in strong field conditions by about 30 dB. After the preamplifier the signal is filtered by a dielectric filter. The filter and the duplex filter rejects outband spurious signals coming from the antenna and spurious emissions coming from inside the receiver unit. After the filter a second LNA is placed in order to have enough gain before the mixer. The received signal is down converted by a passive double balanced mixer. The first IF is 71 MHz. The IF­signal is filtered using a SAW filter. This filter reject adjacent channels signal, intermodulation signals and the second mirror. The AGC dynamic range is split up in two amplifiers. First AGC­amplifier with maximum 45 dB, and second AGC­amplifier with maximum 12 dB gain. Last mentioned amplifier is integrated in the receiver IC. The 57 dB gain is regulated in 3 dB step, using AGC control line PDATA 1­4. The second IF center frequency is 13 MHz. The second IF mixer is integrated in the receiver IC. The 13 MHz filter is a cheap ceramic filter. Also this filter has adjacent channel and intermodulations rejection. Before the 13 MHz IF signal is A/D­converted, the signal is amplified and split up in two quadrature signals, using high and low pass filters. Duplex Filter The duplex filter consists of two filters, RX and TX filter branch. The TX filter is a notch­filter and it rejects the noise power at the RX frequency band and TX harmonic signals. The RX filter (bandpass) rejects outband blocking and spurious signals coming from the antenna. Parameter Center frequency: Pass band width (BW): Insertion loss at BW: Ripple at BW: Terminating impedance: V.S.W.R. at BW: TX attenuation: · 935...960 MHz · 1780...1830 MHz · 2670...2745 MHz

Value TX 902.5 Mhz
±12.5 MHz

Value RX 947.5 MHz
±12.5 MHz

1.5 dB max. 1.2 dB max. 50 1.8 max. 30 dB min. 30 dB min. 30 dB min.

2.6 dB max. 1.5 dB max. 50 1.8 max.

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Parameter RX attenuation: · D.C...915 MHz · 980...1031 MHz · 1870...1920 MHz · 2805...2880 MHz Permissible input power: Pre­Amplifier

Value TX

Value RX

35 dB min. 23 dB min. 30 dB min. 15 dB min. 8.0 W (avg)

The pre­amplifier amplifies the received signal coming from the antenna. Parameter Frequency band: Supply voltage (min/max): Current consumption (max): Insertion gain (min/typ): Gain flatness: Noise figure (max): Reverse isolation (min): Gain reduction PDATA0=1 (typ): IIP3: (min/typ): Input VSWR; Zo=50 (max): Output VSWR; Zo=50 (max): RX Interstage Filters The RX interstage filter is a dielectric filter. The filter rejects the outband spurious and blocking signals coming from the antenna. Parameter Terminating impedance: Operation temperature range: Center frequency: Bandwidth (BW): Insertion loss in BW (max): Ripple at BW:

Value 935...960 Mhz 7.65...9.35 V 10 mA 14.5...15 dB
±0.5 dB

2.0 dB 15 dB 35 dB 0 dBm 2.0 2.0

Value 50 ­25...+85°C 947.5 MHz
±12.5 MHz

2.0 dB 1.0 dB
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Parameter V.S.W.R. at BW: Attenuation · D.C...890 MHz (min/max): · 890...915 MHz (min/max): · 980...1031 MHz (min/max): · 1077...1102 MHz (min/max): · 1870...1920 MHz (min/max): · 1941...2062 MHz (min/max): · 3015...3093 MHz (min/max): Second LNA This LAN adds gain before the mixer. Parameter Frequency band : Supply Voltage (min/max): Current consumption (max) : Insertion gain (typ) Gain Flatness: Noise figure (max): IIP3 (typ): Input VSWR; Zo=50 (max) Output VSWR; Zo=50 (max) First Mixer

Value 1.8 30...15 dB 12...15 dB 12...15 dB 40...50 dB 30...50 dB 30...48 dB 3.0...12 dB

Value 935...960 Mhz 7.65...9.35V 14mA 8dB +/­ 0.5dB 2.8dB 13dBm 2.0 2.0

The first mixer is a passive single balanced mixer. The mixer down converts the received RF signal to the 1st IF signal, 71 MHz. Parameter RX frequency range (min/max): LO frequency range (min/max): IF range (typ): Input intercept point, IIP3 LO power level (min):

Value 935...960 Mhz 1006...1031 Mhz 71 Mhz +10 dBm 3 dBm Original 08/97

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NME­2A System Module GM8

Noise figure (typ): Conversion gain (typ): First IF Amplifier

7 dB, SSB ­7 dB

The first IF amplifier is based on discrete components. It compensates for missing amplification in the frontend. Parameter Supply voltage (min/typ/max): Current consumption (typ/max): Frequency range: Conversion gain (typ): Noise figure (typ): Input intercept point (typ): Input compression point (typ): Parameter In/out matching (typ): First IF Filter The channel selectivity of the receiver is split up in first and second IF filters. The 71 MHz filter is a low loss SAW filter from Siemens. The filter has single­ended input and balanced output. Parameter Center frequency: Operation temperature range: Input impedance: Output impedance: Insertion loss (nom/max): Group delay distortion (nom/max): 2 dB bandwidth (min): 3 dB bandwidth (min): ±200 kHz (min): ±400 kHz (min):

Value 8.5 V 20 mA 71 Mhz 16 dB 3 dB +3 dBm 0 dBm Value 50

Value 71 MHz ­20...+80 °C 3.5 k//6.9 pF balanced 3.4 k//6.7 pF balanced 11.5...13.5 dB 700...1300 ns
±80 kHz ±120 kHz

0 dB 23 dB
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±600 kHz (min): ±800 kHz (min): ±1600 kHz (min): Spurious rejection at fo­26 MHz: AGC Amplifier

36 dB 40 dB 42 dB 60 dB

The total dynamic AGC range for the receiver is 93 dB. The AGC amplifier from AT&T has 0...45 dB AGC gain. The gain step is adjusted in 3 dB step, using the interface lines data[1]­data[5]. Parameter Supply voltage (min/max): Current consumption (max): Frequency range (min/max): Amplifier gain (nom): Parameter

Value 4.5...5.5 V 16 mA 4...100 MHz, 3 dB cutoff 45 dB Value

Amplifier gain control range (min/max): 0...45 dB AGC step size: Noise figure: Output intercept point (max): Absolute gain inaccuracy (max): Relative gain inaccuracy (max): Receiver IF IC The receiver integrated circuit is a semi­custom bipolar IC PMB2403 V1.4. The IC consist of the second IF mixer, 12 dB AGC amplifier and two dividers. AGC amplifier + 2nd mixer Supply voltage (min/max): Supply current (max): Input frequency range (min/max): Local freq. range of mixer (min/max): Conversion gain (nom):

3 dB 10 dB 10 dB
±0.5 dB over temp, range ±0.3 dB

Value 4.5...5.5 V 31 mA 45...100 MHz 170...400 MHz 12 dB Original 08/97

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Output compression point (min): AGC gain step (min/max): Absolute gain inaccuracy (max): Dividers Input frequency range (min/max): Divider ratio (nom): Input power level (nom): Output power level (min): Second IF Filter

0.4 VPP 0...12 dB
±0.5 dB over temp. range

Value 180...400 MHz 1/2/4 ­10 dBm ­5 dBm

The second IF is a ceramic filter. This filter is inserted to obtain channel selectivity in the receiver. Parameter Terminating impedance (nom): Operating temp. range (min/max): Center frequency: 1 dB bandwidth (min): 5 dB bandwidth (max): Insertion loss (max): Group delay distortion (max): Parameter Attenuation · fo ±400 kHz (min/nom): · fo ±600 kHz (min/nom): Second IF Amplifier The second IF amplifier compensates for losses in the gain compensating network, and in the quadrature split. Parameter Supply voltage: Current consumption: Frequency range:

Value 330 ­30...+85 °C 13 MHz
±90 kHz ±220 kHz

6 dB 1500 ns at BW Value

25...30 dB 40...45 dB

Value 8.5 V 10 mA 13 MHz
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Conversion gain: Noise figure: Input intercept point: Input compression point: Input impedance: Output impedance: Phase Split

20 dB 3 dB +3 dBm 0 dBm 330 1000

The phase splitter consists of two filters, a highpass and lowpass. The phase difference between the two output signals is 90 deg. Parameter Frequency: Imbalance amplitude (max): Imbalance phase (max): Attenuation from input RXI or RXQ: Output impedance:

Value 13 Mhz 1 dB 2 deg 9 dB 470

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Transmitter
The transmitter frequency is generated by mixing the buffered UHF VCO signal by the 116 MHz ( 232 MHz from the VHF VCO divided by 2). Reject the noise in hte RX band from the modulator and PA Stage. The mixer is double balanced diode mixer, from the LO port , which is fed by the UHF signal. The final TX frequency is filtered before it is modulated in the modulator. The TX signal is amplified and filtered before it feeds the integrated power amplifier with app. 8 dBm. The interstage filters reject the unwanted mixer products, and together with the TX part of the duplex filter, reject the noise in the RX band from the modulator and the P/A. The power amplifier delivers the transmitter output to the duplex filter, which rejects the harmonics and wideband noise in the RX band. Max outputpower at the antenna connector: 39dBM=8W From the RF interface circuit (RFI), the power level and the up­ and down ramping is controlled by the TXC signal. The amplitude of this signal, which has a raised cosine form, controls the power level from 13 dBm to 39 dBm. A directional coupler gives the feedback signal in the power control loop, to which the raised cosine is an external signal reference. Modulator Circuit The modulator is a quadrature modulator IC PMB 2200 from Siemens. The RF signal is first doubled and then divided (with two) to get accurate 90 degrees phase shifted signals to the I/Q mixers. After mixing, the signals are combined and amplified. The balanced output is loaded and converted to single ended of a transformer, which also add some bandpass filtering. Parameter Supply voltage (min/max): Supply current (typ/nom/max): Transmit frequency input LO input frequency (min/max): LO input power level (min/max): Modulator Inputs (I/Q): Input bias current, balanced (max): External d.c. reference (min/max):

Value 4.5...5.5 V 32...40...48 mA, norm operation Value 800...970 MHz ­20...4 dBm Value 6.0...12 µA 2.1...2.6 V
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Differential input amplit. (min/typ/max): 0.8...1.0...1.2 VPP Differential offset voltage (typ/max): Input impedance (min): Gain unbalance (max): Modulator Output: Available RF power (min/max):

1.0...3.0 mV 70 k 0.2 dB Value ­9...­3 dBm, ZLOAD =200 42 dB 40 dB

Available saturated RF power (min/typ): ­5...0 dBm, ZiL=50 k Suppression of 3rd order prods (min): Single sideband suppression: Up Conversion Mixer The mixer is a double balanced diode mixer. The local signal coming from the UHF synthesizer is balanced. The RF signal a on 116 MHz is the output from the VHF PLL divided by two in the RX IC. Parameter Input frequency: LO frequency range (min/max): TX frequency range (min/max): Conversion loss (nom/max): IIP3 (min): LO ­ RF isolation (min): LO power level (max): TX Interstage Filters The TX interstage filters reject other signals than the final TX frequency from the mixer products. After the modulator they also they also reject the wideband noise from this circuit. Here only the dielectric filter is described. The other filter is realized with discrete components after the mixer. Parameter Terminating impedance: Operating temp. range (min/max): Center frequency: Bandwidth BW (min):

Value 116 MHz 1006...1031 MHz 890...915 MHz 10...12 dB 3.0 dBm 20 dB 6.0 dBm

Value 50 ­25...+85 °C 902.5 MHz
±12.5 MHz

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Insertion loss at BW (nom/max): Ripple at BW (nom/max): V.S.W.R. at BW (nom/max): Attenuation (min/typ) · DC...800 MHz: · 935...960 MHz: · 1006...1031 MHz: · 1032...3000 MHz: TX Amplifiers

2.3...3.0 dB 0.5...1.0 dB 1.7...2.0 dB 30...49 dB 12...18 dB 30...48 dB 3...16 dB

The TX amplifier are bipolar transistor amplifiers. They amplifies the filtered TX signal coming from the down conversion mixer. TX amplifier 1 parameters Operation frequency range: Supply voltag