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Block Diagram of System/RF Blocks
System Module UP8T
NSE3
Original 11/97
3/A31
Circuit Diagram of Baseband
System Module UP8T
(Version 12 Edit 8) for layout version 14
NSE3
Original 11/97
3/A32
Circuit Diagram of Power Supply (Version 14
System Module UP8T
Edit 41) for layout version 14
NSE3
Original 11/97
3/A33
Circuit Diagram of SIM Connectors (Version 14
System Module UP8T
Edit 9) for layout version 14
NSE3
Original 11/97
3/A34
Circuit Diagram of CPU Block (Version 14
System Module UP8T
Edit 23) for layout version 14
NSE3
NSE3
(NSE1)
Original 11/97
3/A35
Circuit Diagram of Audio
System Module UP8T
(Version 14 Edit 27) for layout version 14
NSE3
Original 11/97
3/A36
Circuit Diagram of IR Module (Version 14
System Module UP8T
Edit 21) for layout version 14
NSE3
Original 11/97
3/A37
Circuit Diagram of RF Block (Version
System Module UP8T
14 Edit 26) for layout version 14
NSE3
Original 11/97
3/A38
Layout Diagram of UPT8T Top (Version 14)
System Module UP8T
NSE3
testpoint J102 J103 J107 J110 J111 J221 J222 J229 J230 J231 J232 J233
name FBUS_RX MBUS LGND VPP WDDISX 5V DSPXF MAD selftest MAD selftest VSIM VB (battery voltage in baseband) RFCLK
condition power on power on flash programming power on flash programming power on test mode set externally test mode set externally SIM power on battery connected active state
dclevel pulsed DC (0V/2.8V) pulsed DC (0V/2.8V) 0V nominal 5V (5V flash) or 3.0V (3V flash) reset state 0V, normal state 2.8V nominal 5.0V (5V flash) or 3.0V (3V flash) pulse active 0V, nonactive 2.8V
aclevel
testpoint J502
name Power control op.amp output voltage to N550 ( Vpd, pin ) RFC ( 13 MHz sinewave ) VRX ( regulated supply for RX ) VTX ( regulated supply for TX ) VSYN_1 ( regulated supply for VCOs) VREF_2 ( ref. voltage for N500 ) AFC ( autom. freq. cntrl ) VXO ( regulated supply for VCTCXO ) 71 MHz IF input to N620
condition power level depended
dclevel pulsed DC 0V 2.8 V min 2.7 / max 2.85 V, pulsed 2.8 V min 2.7 / max 2.85 V, pulsed 2.8 V min 2.7 / max 2.85 V 1.5 V +/ 1.5% 0 2.3 V, typ. 1.15 V ( room temp. ) 2.8 V min 2.7 / max 2.85 V
aclevel
J506 J510 J514 J516 J518
typ. 1.0 Vpp min 0.5/max 2.0 Vpp
nominal 2.8V (3V SIM card) or 5.0V (5V SIM card) nominal 3.6V (min 3.0, max 4.2) typ. 1.0Vpp (min 0.5Vpp, max 2.0Vpp) nominal 5.5V (min 5V, max 6V) CCONT switch mode regulator ripple voltage
J520 J522 J530 & J532
95 dBm @ X540 (ext. RF connector )
typ. ca. 1.2 V pulsed
J234
VSRM
power on
typ 100 140 uVpp balanced voltage at 71 MHz typ. ca. 700 uVrms
J540
13 MHz output from N620 to Z620
J236 J250 J252 J253 J254 J255
RAMSELX GND COBBARSTX COBBAWRX COBBARDX COBBACLK
active state power on active state active state active state
pulse active 0V, nonactive 2.8V 0V reset state 0V, normal state 2.8V pulse active 0V, nonactive 2.8V pulse active 0V, nonactive 2.8V pulsed DC (0V/2.8V) J550 & J552 J562 116 MHz TX IF to N500 RXC ( receive gain control voltage )
95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain
typ. ca. 1.5 V pulsed
typ. ca. 1.1 1.2 V pulsed RX gain setting depended control range is 0.5 1.45 V, ,pulsed. typ. 1.31.4 V for calibrated maximum gain
typ. ca. 100 mVrms each
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3/A39
Layout Diagram of UPT8T Bottom (Version 14)
System Module UP8T
NSE3
testpoint J101 J104 J108 J220 J223 J224 J225 J226 J227 J228 J235 J251 J256
name FBUS_TX CCONTCSX (CCONT chip select) CHRG_CTRL V5V CCONTINT (charger, RTC interrupt) VCOBBA EXTSYSRESETX VCXOPWR PURX (power on reset) SLEEPCLK (32kHz clock) ROM1SELX AGND COBBADAX
condition active state active state charger connected active state interrupt active state power on power on power up/down power on active state pcb ground active state
dclevel pulsed DC (0V72.8V) pulse active 0V, nonactive 2.8V pulsed DC (0V/2.8V) nominal 5.0V (min 4.8V, max 5.2V) pulse active 2.8V, nonactive 0V nominal 2.8V (min 2.7V, max 2.85V) reset state 0V, normal state 2.8V active state 2.8V, nonactive 0V reset state 0V, normal state 2.8V pulsed DC (0V/2.8V) pulse active 0V, nonactive 2.8V 0V pulse active 0V, nonactive 2.8V
aclevel
testpoint J500
name Control voltage for UHF VCO module G600 Control voltage for VHF VCO circuit VSYN_2 ( regulated supply for PLLS ) 13 MHz IF output to N250
condition channel 60 channel 1 channel 124
dclevel 2.25 +/ 0.25 V > 0.8 V < 3.7 V typ. 2.0 2.2 V min 0.5 / max 4.0 V 2.8 V min 2.7 / max 2.85 V
aclevel
J504 J508 J534&J5 36
95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain 95 dBm @ X540 (ext. RF connector ) RXC at level of full calibrated gain
typ ca. 1.0 1.1 V pulsed min. 0.7 / max. 1.4 V
typ. 50 mVpp balanced voltage at 13 MHz
J538
13 MHz output from Z620 to N620
typ. ca. 1.5 V pulsed
typ. ca 600 uVrms
J542 J554 J556 J558 J560
VHF VCO output ( 232 MHz ) TXC ( TX power control voltage ) TXP ( TX enable ) TXQP ( other half of balanced Qsignal ) TXIP ( other half of balanced Isignal )
@level 19 typ. ca. 0.6 V pulse @level 5 typ ca. 1.8 V pulse 2.8 V logic level pulse, ( max. 0.8 V "0" / min 2.0 V "1" ) 0.8 V pulsed 0.8 V pulsed
typ. 400 mVpp. > 100 mVpp required
400 mVpp 400 mVpp
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3/A310