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SERVICE MANUAL
bbk965S
VOL1 VOL2
CONTENTS
1. SAFETY PRECAUTIONS 1
2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY
SENSITIVE(ES)DEVICES 1
3. CONTROL BUTTON LOCATIONS AND EXPLANATIONS 2
4. PREVERTION OF STATIC ELECTRICITY DISCHARGE 3
5. ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT 4
5.1 OPTICAL PICKUP UNIT EXPLOSED VIEW AND PART LIST 4
5.2 BRACKET EXPLOSED VIEW AND PART LIST 6
5.3 MISCELLANEOUS 7
6. ELECTRICAL CONFIRMATION 8
6.1 VIDEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION 8
6.2 VIDEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION 9
7. MPEG BOARD CHECK WAVEFORM 10
8. AM29LV160D 11
8.1 HY57V641620HG 16
8.2 MT1389 19
9. SCHEMATIC & PCB WIRING DIAGRAM 22
10. SPARE PARTS LIST 34
1. SAFETY PREAUTIONS
1.1 GENERAL GUIDELINES
1. When servicing, observe the original lead dress. if a short circuit is found, replace all parts which have
been overheated or damaged by the short circuit.
2. After servicing, see to it that all the protective devices such as insulation barrier, insulation papers
shields are properly installed.
3. After servicing, make the following leakage current checks to prevent the customer from being exposed
to shock hazards.
2.PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO
ELECTROSTATICALLY SENSITIVE(ES)DEVICES
Some semiconductor(solid state)devices can be damaged easily by static electricity. Such components
commonly are called Electrostatically Sensitive(ES)Devices. Examples of typical ES devices are integrated
circuits and some field-effect transistors and semiconductor chip components. The following techniques
should be used to help reduce the incidence of component damage caused by electro static discharge(ESD).
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain
off any ESD on your body by touching a known earth ground. Alternatively, obtain and wear a commercially
availabel discharging ESD wrist strap, which should be removed for potential shock reasons prior to
applying power to the unit under test.
2. After removing an electrical assembly equipped with ES devices,place the assembly on a conductive
surface such as alminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as anti-static
(ESD protected)can generate electrical charge sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ES
devices.
6. Do not remove a replacement ES device from its protective package until immediately before you are
ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by
conductive foam, alminum foil or comparable conductive material).
7. Immediately before removing the protective material from the leads of a replacement ES device, touch
the protective material to the chassis or circuit assembly into which the device will be installed.
Caution
Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can
generate static electricity(ESD).
notice (1885x323x2 tiff)
1
3.Control Button Locations and Explanations
Front Panel Illustration
2 3
VOL1 VOL2
4 5 6 7 8 9 10 11 12 13 14
IR SENSOR 6 MIC 2 VOLUME knob 11 PAUSE button
2 Disc tray 7 MIC 1 VOLUME knob 12 STOP button
3 VFD display window 8 MIC 2 VOLUME knob 13 REW button
4 POWER switch 9 OPEN/CLOSE button 14 button
5 MIC 1 jack 10 PLAY button
2
4.PREVENTION OF STATIC ELECTRICITY DISCHARGE
The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human
body. Use due caution to electrostatic breakdown when servicing and handling the laser diode.
4.1.Grounding for electrostatic breakdown prevention
Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged
by static electricity in the working environment.Proceed servicing works under the working environment where
grounding works is completed.
4.1.1. Worktable grounding
1. Put a conductive material(sheet)or iron sheet on the area where the optical pickup is placed,and ground the
sheet.
4.1.2.Human body grounding
1 Use the anti-static wrist strap to discharge the static electricity from your body.
safety_3 (1577x409x2 tiff)
4.1.3.Handling of optical pickup
1. To keep the good quality of the optical pickup maintenance parts during transportation and before
installation, the both ends of the laser diode are short-circuited.After replacing the parts with new ones,
remove the short circuit according to the correct procedure. (See this Technical Guide).
2. Do not use a tester to check the laser diode for the optical pickup .Failure to do so willdamage the laser
diode due to the power supply in the tester.
4.2. Handling precautions for Traverse Unit (Optical Pickup)
1. Do not give a considerable shock to the traverse unit(optical pickup)as it has an extremely high-precise
structure.
2. When replacing the optical pickup, install the flexible cable and cut is short land with a nipper. See the
optical pickup replacement procedure in this Technical Guide. Before replacing the traverse unit, remove
the short pin for preventingstatic electricity and install a new unit.Connect the connector as short times as
possible.
3. The flexible cable may be cut off if an excessive force is applied to it.Use caution when handling the cable.
4. The half-fixed resistor for laser power adjustment cannot be adjusted. Do not turn the resistor.
3
5. Assembling and disassembling the mechanism unit
5.1 Optical pickup Unit Explosed View and Part List
Pic (1)
4
Materials to Pic (1)
No. PARTS CODE PARTS NAME Q ty
14692200 SF-HD60 1
1 1EA0311A06300 ASSY, CHASSIS, COMPLETE 1
2 1EA0M10A15500 ASSY, MOTOR, SLED 1
Or 1EA0M10A15501 ASSY, MOTOR, SLED 1
3 1EA2451A24700 HOLDER, SHAFT 3
4 1EA2511A29100 GEAR, RACK 1
5 1EA2511A29200 GEAR, DRIVE 1
6 1EA2511A29300 GEAR, MIDDLE, A 1
7 1EA2511A29400 GEAR, MIDDLE, B 1
8 1EA2744A03000 SHAFT, SLIDE 1
9 1EA2744A03100 SHAFT, SLIDE, SUB 1
10 1EA2812A15300 SPRING, COMP, TYOUSEI 3
11 1EA2812A15400 SPRING, COMP, RACK 1
21 1EA0B10B20100 ASSY, PWB 1
Or 1EA0B10B20200 ASSY, PWB 1
31 SEXEA25700--- SPECIAL SCREW BIN+-M2X11 3
32 SEXEA25900--- SPECIAL SCREW M1.7X2.2 2
33 SFBPN204R0SE- SCR S-TPG PAN 2X4 2
34 SFSFN266R0SE- SCR S-TPG FLT 2.6X6 1
35 SWXEA15400--- SPECIAL WASHER 1.8X4 X0.25 2
Note : This parts list is not for service parts supply.
5
5.2 Bracket Explosed View and Part List
Pic (2)
Materials to Pic(2)
1.bracket 14. front silicon rubber
2.belt 15. Back silicon rubber
3.screw 16. Pick-up
4.belt wheel 17. Pick-up
5.gearwheel 18. switch
6.iron chip 19. Five-pin flat plug
7. Immobility mechanism equipment 20. screw
8. Magnet 21. PCB
9. Platen 22. motor
10. Bridge bracket 23. Motor wheel
11. screw 24. screw
12. screw 25.tray
13. Big bracket
Before going process with disassembly and installation, please carefully both
peruse the chart and confirm the materials.
6
5.3 MISCELLANEOUS
5.3.1 Protection of the LD(Laser diode)
Short the parts of LD circuit pattern by soldering.
5.3.2 Cautions on assembly and adjustment
Make sure that the workbenches,jigs,tips,tips of soldering irons and measuring instruments are
grounded,and that personnel wear wrist straps for ground.
Open the LD short lands quickly with a soldering iron after a circuit is connected.
Keep the power source of the pick-up protected from internal and external sources of electrical
noise.
Refrain from operation and storage in atmospheres containing corrosive gases (such as H2S,SO2,
NO2 and Cl2)or toxic gases or in locations containing substances(especially from the organic silicon,cyan,
formalin and phenol groups)which emit toxic gases.It is particularly important to ensure that none of the
above substances are present inside the unit.Otherwise,the motor may no longer run.
7
6.Electrical Confirmation
6.1. Video Output (Luminance Signal) Confirmation
DO this confirmation after replacing a P.C.B.
Measurement point Mode Disc
Color bar 75% DVDT-S15
Video output terminal PLAY(Title 46):DVDT-S15 or
PLAY(Title 12):DVDT-S01 DVDT-S01
Measuring equipment,tools Confirmation value
200mV/dir,10 sec/dir 1000mVp-p±30mV
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohms.
2.Confirm that luminance signal(Y+S)level is 1000mVp-p±30mV
8
6.2 Video Output(Chrominance Signal) Confirmation
Do the confirmation after replacing P.C.B.
Measurement point Mode Disc
Color bar 75% DVDT-S15
Video output terminal PLAY(Title 46):DVDT-S15 or
PLAY(Title 12):DVDT-S01 DVDT-S01
Measuring equipment,tools Confirmation value
Screwdriver,Oscilloscope
200mV/dir,10 sec/dir 621mVp-p±30mV
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohme.
2.Confirm that the chrominance signal(C)level is 621 mVp-p±30mV
9
7.MPEG BOARD CHECK WAVEFORM
7.1 27MHz WAVEFORM
DIAGRAM
7.2 IC5L0380R PIN.2 WAVEFORM DIAGRAM
10
8. Am29LV160D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation s Embedded Algorithms
-- Full voltage range: 2.7 to 3.6 volt read and write -- Embedded Erase algorithm automatically
operations for battery-powered applications preprograms and erases the entire chip or any
-- Regulated voltage range: 3.0 to 3.6 volt read and combination of designated sectors
write operations and for compatibility with high -- Embedded Program algorithm automatically
performance 3.3 volt microprocessors writes and verifies data at specified addresses
s Manufactured on 0.23 µm process technology s Minimum 1,000,000 write cycle guarantee
-- Fully compatible with 0.32 µm Am29LV160B device per sector
s 20-year data retention at 125°C
s High performance
-- Reliable operation for the life of the system
-- Access times as fast as 70 ns
s Package option
s Ultra low power consumption (typical values at
5 MHz) -- 48-ball FBGA
-- 200 nA Automatic Sleep mode current -- 48-pin TSOP
-- 200 nA standby mode current -- 44-pin SO
-- 9 mA read current s CFI (Common Flash Interface) compliant
-- 20 mA program/erase current -- Provides device-specific information to the
system, allowing host software to easily
s Flexible sector architecture
reconfigure for different Flash devices
-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode) s Compatibility with JEDEC standards
-- One 8 Kword, two 4 Kword, one 16 Kword, and -- Pinout and software compatible with single-
thirty-one 32 Kword sectors (word mode) power supply Flash
-- Supports full chip erase -- Superior inadvertent write protection
-- Sector Protection features: s Data# Polling and toggle bits
A hardware method of locking a sector to prevent -- Provides a software method of detecting program
any program or erase operations within that sector or erase operation completion
Sectors can be locked in-system or via s Ready/Busy# pin (RY/BY#)
programming equipment
-- Provides a hardware method of detecting
Temporary Sector Unprotect feature allows code program or erase cycle completion (not available
changes in previously locked sectors on 44-pin SO)
s Unlock Bypass Program Command s Erase Suspend/Erase Resume
-- Reduces overall programming time when issuing -- Suspends an erase operation to read data from,
multiple program command sequences or program data to, a sector that is not being
s Top or bottom boot block configurations erased, then resumes the erase operation
available s Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading
array data
This Data Sheet states AMD's current technical specifications regarding the Product described herein. This Data Publication# 22358 Rev: B Amendment/+3
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Issue Date: November 10, 2000
11
PRODUCT SELECTOR GUIDE
Family Part Number Am29LV160D
Speed Option Voltage Range: VCC = 2.73.6 V -70 -90 -120
Max access time, ns (tACC) 70 90 120
Max CE# access time, ns (tCE) 70 90 120
Max OE# access time, ns (tOE) 30 35 50
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
RY/BY# DQ0DQ15 (A-1)
VCC
Sector Switches
VSS
Erase Voltage Input/Output
RESET# Generator Buffers
WE# State
Control
BYTE#
Command
Register
PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
Logic
OE#
Y-Decoder Y-Gating
STB
Address Latch
VCC Detector Timer
X-Decoder Cell Matrix
A0A19
Am29LV160D 12
CONNECTION DIAGRAMS
A15 1 48 A16
A14 2 47 BYTE#
A13 3 46 VSS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
A19 9 40 DQ5
NC 10 39 DQ12
WE# 11 Standard TSOP 38 DQ4
RESET# 12 37 VCC
NC 13 36 DQ11
NC 14 35 DQ3
RY/BY# 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 VSS
A2 23 26 CE#
A1 24 25 A0
A16 1 48 A15
BYTE# 2 47 A14
VSS 3 46 A13
DQ15/A-1 4 45 A12
DQ7 5 44 A11
DQ14 6 43 A10
DQ6 7 42 A9
DQ13 8 41 A8
DQ5 9 40 A19
DQ12 10 39 NC
DQ4 11 38 WE#
VCC 12 Reverse TSOP 37 RESET#
DQ11 13 36 NC
DQ3 14 35 NC
DQ10 15 34 RY/BY#
DQ2 16 33 A18
DQ9 17 32 A17
DQ1 18 31 A7
DQ8 19 30 A6
DQ0 20 29 A5
OE# 21 28 A4
VSS 22 27 A3
CE# 23 26 A2
A0 24 25 A1
13
CONNECTION DIAGRAMS
RESET# 1 44 WE#
A18 2 43 A19
A17 3 42 A8
A7 4 41 A9
A6 5 40 A10
A5 6 39 A11
A4 7 38 A12
A3 8 37 A13
A2 9 36 A14
A1 10 35 A15
A0 11 34 A16
CE# 12 SO 33 BYTE#
VSS 13 32 VSS
OE# 14 31 DQ15/A-1
DQ0 15 30 DQ7
DQ8 16 29 DQ14
DQ1 17 28 DQ6
DQ9 18 27 DQ13
DQ2 19 26 DQ5
DQ10 20 25 DQ12
DQ3 21 24 DQ4
DQ11 22 23 VCC
FBGA
Top View, Balls Facing Down
A6 B6 C6 D6 E6 F6 G6 H6
A13 A12 A14 A15 A16 BYTE# DQ15/A-1 VSS
A5 B5 C5 D5 E5 F5 G5 H5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
A4 B4 C4 D4 E4 F4 G4 H4
WE# RESET# NC A19 DQ5 DQ12 VCC DQ4
A3 B3 C3 D3 E3 F3 G3 H3
RY/BY# NC A18 NC DQ2 DQ10 DQ11 DQ3
A2 B2 C2 D2 E2 F2 G2 H2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A1 B1 C1 D1 E1 F1 G1 H1
A3 A4 A2 A1 A0 CE# OE# VSS
Special Handling Instructions Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
Special handling is required for Flash Memory products
The package and/or data integrity may be compromised
in FBGA packages.
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
A
14
PIN CONFIGURATION LOGIC SYMBOL
A0A19 = 20 addresses
20
DQ0DQ14 = 15 data inputs/outputs A0A19 16 or 8
DQ15/A-1 = DQ15 (data input/output, word mode),
DQ0DQ15
A-1 (LSB address input, byte mode)
(A-1)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable CE#
OE# = Output enable OE#
WE# = Write enable
WE#
RESET# = Hardware reset pin
RESET#
RY/BY# = Ready/Busy output
(N/A SO 044) BYTE# RY/BY#
(N/A SO 044)
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS = Device ground
NC = Pin not connected internally
15
HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM
8.1 HY57V641620HG
DESCRIPTION
The Hyundai HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
· Single 3.3±0.3V power supply Note) · Auto refresh and self refresh
· All device pins are compatible with LVTTL interface · 4096 refresh cycles / 64ms
· JEDEC standard 400mil 54pin TSOP-II with 0.8mm · Programmable Burst Length and Burst Type
of pin pitch
- 1, 2, 4, 8 or Full page for Sequential Burst
· All inputs and outputs referenced to positive edge of
system clock - 1, 2, 4 or 8 for Interleave Burst
· Data mask function by UDQM or LDQM · Programmable CAS Latency ; 2, 3 Clocks
· Internal four banks operation
.
16
HY57V641620HG
PIN CONFIGURATION
VDD 1 54 VSS
DQ0 2 53 DQ15
VDDQ 3 52 VSSQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VSSQ 6 49 VDDQ
DQ3 7 48 DQ12
DQ4 8 47 DQ11
VDDQ 9 46 VSSQ
DQ5 10 45 DQ10
DQ6 11 44 DQ9
VSSQ 12 43 VDDQ
DQ7 13 54pin TSOP II 42 DQ8
VDD 14 400mil x 875mil 41 VSS
LDQM 15 0.8mm pin pitch 40 NC
/WE 16 39 UDQM
/CAS 17 38 CLK
/RAS 18 37 CKE
/CS 19 36 NC
BA0 20 35 A11
BA1 21 34 A9
A10/AP 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 VSS
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
CLK Clock
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
CKE Clock Enable
of the states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
BA0,BA1 Bank Address
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
A0 ~ A11 Address
Auto-precharge flag : A10
Row Address Strobe,
RAS, CAS and WE define the operation
RAS, CAS, WE Column Address Strobe,
Refer function truth table for details
Write Enable
LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
17
HY57V641620HG
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic Internal Row
& timer counter
CLK 1Mx16 Bank 3
Row active Row 1Mx16 Bank 2
CKE Pre
X decoders
Decoders 1Mx16 Bank 1
X decoders
CS 1Mx16 Bank 0
State Machine
X decoders
RAS DQ0
Sense AMP & I/O Gate
X decoders
Memory DQ1
I/O Buffer & Logic
CAS refresh Cell
Array
WE Column Column
Active
Pre
UDQM Decoders DQ14
DQ15
LDQM Y decoders
Column Add
Bank Select Counter
A0 Address
A1 Registers
Address buffers
Burst
Counter
A11
BA0
CAS Latency
BA1 Mode Registers Data Out Control Pipe Line Control
18
8.2 MT1389 MT1389
Progressive-Scan DVD Player SOC
Specifications are subject to change without notice
MediaTek MT1389 is a DVD player system-on-chip (SOC) which incorporates advanced features like high
quality TV encoder and state-of-art de-interlace processing. The MT1389 enables consumer electronics
manufacturers to build high quality, cost-effective DVD players, portable DVD players or any other home
entertainment audio/video devices.
Based on MediaTek's world-leading DVD player SOC architecture, the MT1389 is the 3rd generation of the DVD
player SOC. It integrates the MediaTek 2nd generation front-end analog RF amplifier and the Servo/MPEG AV
decoder.
The progressive scan of the MT1389 utilized a proprietary advanced motion-adaptive de-interlace algorithm to
achieve the best movie/video playback. It can easily detect 3:2/2:2 pull down source and restore the correct
original pictures. It also supports a patent-pending edge-preserving algorithm to remove the saw-tooth effect.
Key Features
RF/Servo/MPEG Integration
CVBS, Y/C, High Performance Audio Processor
DVD
Component Motion-Adaptive, Edge-Preserving De-interlace
PUH
Module SDPIF 108MHz/12-bit, 6 CH TV Encoder
MT1389L
Applications
FLASH Audio DAC Standard DVD Players
Portable DVD Players
Front-panel
DRAM
Remote
DVD Player System Diagram Using MT1389
19
MT1389
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
General Feature List
1024-bytes on-chip RAM
Super Integration DVD player single chip Up to 4M bytes FLASH-programming
High performance analog RF amplifier interface
Servo controller and data channel processing Supports 5/3.3-Volt. FLASH interface
MPEG-1/MPEG-2/JPEG video Supports power-down mode
Dolby AC-3/DTS/DVD-Audio Supports additional serial port
Unified memory architecture
Versatile video scaling & quality DVD-ROM/CD-ROM Decoding Logic
enhancement High-speed ECC logic capable of correcting
OSD & Sub-picture one error per each P-codeword or
2-D graphic engine Q-codeword
Built-in clock generator Automatic sector Mode and Form detection
Built-in high quality TV encoder Automatic sector Header verification
Built-in progressive video processor Decoder Error Notification Interrupt that
Audio effect post-processor signals various decoder errors
Audio input port Provide error correction acceleration
High Performance Analog RF Amplifier Buffer Memory Controller
Programmable fc Supports 16Mb/32Mb/64Mb/128Mb SDRAM
Dual automatic laser power control Supports 16-bit SDRAM data bus
Defect and blank detection Provide the self-refresh mode SDRAM
RF level signal generator Block-based sector addressing
Support 3.3 Volt. DRAM Interface
Speed Performance on Servo/Channel Decoding
DVD-ROM up to 4XS Video Decode
CD-ROM up to 24XS Decodes MPEG1 video and MPEG2 main level,
main profile video (720/480 and 720x576)
Channel Data Processor Smooth digest view function with I, P and B
Digital data slicer for small jitter capability picture decoding
Built-in high performance data PLL for Baseline, extended-sequential and
channel data demodulation progressive JPEG image decoding
EFM/EFM+ data demodulation Support CD-G titles
Enhanced channel data frame sync protection
& DVD-ROM sector sync protection Video/OSD/SPU/HLI Processor
Arbitrary ratio vertical/horizontal scaling of
Servo Control and Spindle Motor Control video, from 0.25X to 256X
Programmable frequency error gain and 65535/256/16/4/2-color bitmap format OSD,
phase error gain of spindle PLL to control 256/16 color RLC format OSD
spindle motor on CLV and CAV mode Automatic scrolling of OSD image
Built-in ADCs and DACs for digital servo Slide show transition as DVD-Audio
control Specification
Provide 2 general PWM
Tray control can be PWM output or digital 2-D Graphic Engine
output Support decode Text and Bitmap
Support line, rectangle and gradient fill
Embedded Micro controller Support bitblt
Built-in 8032 micro controller Chroma key copy operation
Built-in internal 373 and 8-bit programmable Clip mask
lower address port
20
MT1389
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Audio Effect Processing TV Encoder
Dolby Digital (AC-3)/EX decoding Six 108MHz/12bit DACs
DTS/DTS-ES decoding Support NTSC, PAL-BDGHINM, PAL-60
MLP decoding for DVD-Audio Support 525p, 625p progressive TV format
MPEG-1 layer 1/layer 2 audio decoding Automatically turn off unconnected channels
MPEG-2 layer1/layer2 2-channel audio Support PC monitor (VGA)
High Definition Compatible Digital (HDCD) Support Macrovision 7.1 L1, Macrovision
Windows Media Audio (WMA) 525P and 625P
Advanced Audio Coding (AAC) CGMS-A/WSS
Dolby ProLogic II Closed Caption
Concurrent multi-channel and downmix out
IEC 60958/61937 output Progressive Output
- PCM / bit stream / mute mode Automatic detect film or video source
- Custom IEC latency up to 2 frames 3:2 pull down source detection
Pink noise and white noise generator Advanced Motion adaptive de-interlace
Karaoke functions Edge Preserving
- Microphone echo Minimum external memory requirement
- Microphone tone control
- Vocal mute/vocal assistant Audio Input
- Key shift up to +/- 8 keys Line-in/SPDIF-in for versatile audio
- Chorus/Flanger/Harmony/Reverb processing
Channel equalizer
3D surround processing include virtual Outline
surround and speaker separation 256-pin LQFP package
3.3/1.8-Volt. Dual operating voltages
21
U404
LM117
+5V
IN
OUT
GND
3
2
1
+5V V402
R405 8050D
TC402 75R
47uF/16V R407 R408 R409
R412 1K
75R
REQUIER +4V TO LI
GHT
TC403
47uF/16V R415
A
A
+5V +5V R414 1K
R413 1K
0R LED403
R411 V404 R402 R403
8050D 470R 4.7K
FRONT SCHEMATIC DIAGRAM
1K LED402
+5V
C
K
K
TC401
C405 C404 R404 C401 47uF/16V P2/S2
1
R401 B V401 101 681 62K 103
2
LED404 LED405 LED406 LED407 LED408 LED409 1K 8050D
KI2 +5V
1
1
(DNS) (DNS) R406
C403 C402 0R KI1
E
R418 R417
22
2
103 103
2
DO
1
9. SCHEMATIC & PCB WIRING DIAGRAM
1
CE
CL VD401 KS1
1N4148 R416
2
2
DI
LED401 K406 47R
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LED#
1
2
K401
R410
DI
CL
CE
DO
SW1 1 2 V403
KI5
KI4
KI3
KI2
KI1
VSS
KS6
OSD
VDD
TEST